Prosecution Insights
Last updated: April 19, 2026
Application No. 18/465,825

DIFFERENTIAL CASCODE AMPLIFIER ARRANGEMENT WITH REDUCED COMMON MODE GATE RF VOLTAGE

Non-Final OA §103§DP
Filed
Sep 12, 2023
Examiner
NGUYEN, HIEU P
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co. Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
1123 granted / 1220 resolved
+24.0% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
25 currently pending
Career history
1245
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1220 resolved cases

Office Action

§103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement filed on 09/12/2023 has been considered and placed in the application file. Double Patenting Claims 23-47 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 11,601,098. Although the conflicting claims are not identical, they are not patentably distinct from each other because all of the limitations/features of the present claims are present in the patented claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim is are rejected under 35 U.S.C. 103 as being unpatentable over Moreira (U.S. 8,816,769). Regarding claim 23, Moreira (hereinafter, Ref~769) discloses (please see Figs. 1-9 and related text for details) a differential radio frequency (RF) cascode amplification circuit (e.g., 200 of Fig. 9) comprising: a first cascode amplification leg (see left amplification leg of Fig. 2) comprising a first input transistor (208 of Fig. 2) and a first group of cascode transistors (210 and/or 206 of Fig. 2) including a first output transistor (206 of Fig. 2), wherein the first cascode amplification leg is configured to amplify a first input RF signal (VIN+ of Fig. 2) of a differential RF input signal (Vin of Fig. 2); a second cascode amplification leg (see right amplification leg of Fig. 2) comprising a second input transistor (208 of Fig. 2) and a second group of cascode transistors (210 and/or 206 of Fig. 2) including a second output transistor (206 of Fig. 2), wherein the second cascode amplification leg is configured to amplify a second input RF signal (Vin- of Fig. 2) of the differential RF input signal; and at least one capacitive coupling arrangement (C1:C3 of Fig. 2 can be read as the claimed arrangement OR at least it is functionally equivalent to it. Specifically C3 directly coupled between gates of said cascode transistors, while C1-C2 coupled indirectly between gates of said cascode transistors) coupled between a first gate node of a first cascode transistor of the first group of cascode transistors and a second gate node of a second cascode transistor of the second group of cascode transistors (please note that Ref~769 teaches that the LC tank is configured to provide the selected harmonics to at least gates of the upper transistors as advertised in the abstract, thus one skilled in the art would obviously employ/extend the feature to gate connected transistors 106 and 110 of the transistor stack as described, e.g., in col. 3, between lines 1-10), wherein the at least one capacitive coupling arrangement capacitively couples the first gate node and the second gate node to an intermediate gate node (disposed between resistor pair of Fig. 2. Please note that the gate of transistors 210 would be configured in the same manner compared to transistors 206 of Fig. 2 when employed said feature) of the at least one capacitive coupling arrangement, the intermediate gate node being devoid of a physical connection to a ground as seen, since it is being connected to Vbias, meeting claim 23. Allowable Subject Matter Claims 24-46 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Allowable Subject Matter Claim 47 is allowed. The following is an examiner’s statement of reasons for allowance: Claim 47 is allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “based on the coupling, creating an AC reference voltage at an intermediate gate node of the capacitive coupling arrangement; based on the coupling and the creating, capacitively coupling via respective first and second capacitors the first and second gate nodes to the intermediate gate node, thereby eliminating a physical ground connection to the first and second capacitors; and based on the eliminating, reducing parasitic inductance at the first and second gate nodes” structurally and functionally interconnected with other limitations in the manner as cited in the claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Sep 12, 2023
Application Filed
Dec 29, 2023
Response after Non-Final Action
Feb 03, 2026
Non-Final Rejection — §103, §DP (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.1%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1220 resolved cases by this examiner. Grant probability derived from career allow rate.

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