Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the communication filed on 2/12/2026.
Claims 1-27 are examined and rejected.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's submission filed on 2/12/2026 has been entered.
Response to Arguments
Applicant’s arguments dated 2/12/2026 with respect to claim(s) 1-20 have been considered.
Examiner describes the reply to applicant’s arguments as below – Neither reference’s of does not teach - ‘executing the plurality of instructions in a random order based on the randomly reordered execution order’, the process is not applying watermark.
In summary applicant argues that combination of references Miller – Jeong – Shenn-Orr does not teach above claimed combination of limitations.
Examiner does not find argument persuasive.
Examiner replies to arguments is as follows -
Examiner interprets the following claim limitation as following as the claim contain multiple parts to function of executing instructions.
A - Randomly reorder execution order – example ordering of instructions (firmware) in order of example - 3 5 2 1 4.
B - Execute the execution order in the order of 3 5 2 1 4.
Analyzing arguments, A and B as taught by references –
A - randomly reorder an execution order of the plurality of instructions is covered by Miller 22-23, 25 and Fig 7 para 47-49 teaches randomly changing firmware instructions with random number as seed and further changing locations of firmware codes stored in tables which covers the claimed limitation. Additionally, randomizing instructions is known concept in the art of security where random number are introduced in any data stream and randomized as a preventive measure against attackers on system.
B - execute instructions in a random order based on the randomly reordered execution order Shen Orr teaches Fig 1 para 19-20 and 22-23 teaches randomization of memory address(s) and further randomization instructions for address space layout which covers claimed limitation. Further analyzing the reference teaching – randomization of instructions and executing of randomized instructions is covered by reference Shen-Orr.
Thus, examiner concludes that combination of reference’s teaches the claimed limitation.
Examiner is open for phone call interview to discuss further with applicant’s representative for the purpose of compact prosecution.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-27 are rejected under 35 U.S.C. 103 as being unpatentable by U.S. Publication 2020/0410102 to Miller et al. (hereinafter known as “Miller”) and in view of U.S. Publication 2023/0004644 to Jeong et al. (hereinafter known as “Jeong”) and further in view of U.S. Publication 2019/0213330 to Shen-Orr et al. (hereinafter known as “Shen-Orr”).
As per claim 1 Miller teaches, an apparatus for secure processing, comprising: a memory comprising instructions; and a processor coupled to the memory, wherein the processor is configured to:
receive a plurality of instructions for execution (Miller para 21-22 teaches firmware code or boot loader code which is interpreted as execution instructions);
receive an indication that the plurality of instructions are independent instructions (Miller para 22 teaches firmware or control data which is interpreted as independent instructions);
randomly reorder an execution order of the plurality of instructions (Miller 22-23, 25 and Fig 7 para 47-49 teaches randomly changing firmware instructions with random number as seed and further changing locations of firmware codes stored in tables which covers the claimed limitation) and ;
execute the plurality of instructions (Miller Fig 7 para 48-49 teaches element 164 randomizer which selectively reorders firmware code and locations of control data (interpreted as instructions) in random order); and
Although Miller teaches outputs with random number and address tables randomly mixed up (interpreted as random reordered instructions), Jeong further teaches, output a plurality of results corresponding to the plurality of instructions (Jeong para 22 and 27-28 where outputs based on random number and counter to countermeasure side-channel attack).
Miller-Jeong are analogous with secure firmware (instructions) from intrusion.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Miller-Jeong before him or her, to combine, Miller’s protection of firmware with random number generator for modified tables (Miller abstract) with Jeong’s teaching of random number generator resistant to side-channel attack (abstract). The suggestion/motivation for doing so would have been to prevent firmware defending against a side-channel attack using a random frequency generated based on an entropy source of a true random number generator and a method for operating the generator (Jeong para 1).
Miller-Jeong does not teach however Shenn-Orr teaches,
execute instructions in a random order based on the randomly reordered execution order (Shen Orr teaches Fig 1 para 19-20 and 22-23 teaches randomization of memory address(s) and further randomization instructions for address space layout which covers claimed limitation).
Miller-Jeong- Shenn-Orr are analogous with secure instructions to prevent attack / intrusion.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Miller-Jeong-Shenn-Orr before him or her, to combine, Miller-Jeong’s protection of firmware with random number generator for modified tables with Shenn-Orrs teaching of execute instructions in a random order based on the randomly reordered execution order (Shenn-Orr Fig 1). The suggestion/motivation for doing so would have been to prevent side-channel attack based on deducing if data in cached or un-cached region (Shenn-Orr para 2).
Further examiner describes that claim function is interpreted as per specification Fig 4 of executing instructions in random order of randomly organized instructions or encrypted instructions (as encrypted instructions are randomized or masked instructions). Additionally, Miller Fig 7 para 48-49 teaches randomizer of address and executing instructions in randomized order which also covers the claimed limitation, yet for distinct teaching purpose examiner is including new reference of Shenn-Orr.
As per claim 2 combination of Miller – Jeong – Shen Orr teaches, the apparatus of claim 1, wherein the indication comprises a dedicated instruction (Miller Fig 7 para 48-49 teaches randomizer which selectively reorders control data or firmware code which is interpreted as dedicated instruction as known in art).
As per claim 3 combination of Miller – Jeong – Shen Orr teaches, the apparatus of claim 2, wherein the dedicated instruction indicates a number of subsequent instructions comprise the plurality of instructions for execution (Miller Fig 7 para 48-49 teaches where randomizing of firmware, control data and address table is interpreted as plural instructions).
As per claim 4 combination of Miller – Jeong – Shen Orr teaches, the apparatus of claim 2, wherein the dedicated instruction includes a parameter, the parameter indicating that a subsequent instruction is an instruction of the plurality of instructions for execution (Miller Fig 7 para 48-49 teaches where firmware, address table is interpreted as additional parameter).
As per claim 5 combination of Miller – Jeong – Shen Orr teaches, the apparatus of claim 4, wherein the parameter of the dedicated instruction indicates an end to the plurality of instructions for execution (Miller Fig 7 para 48-49 teaches randomized firmware, control data which is further used to decode randomized instructions for firmware location interpreted as end of instruction).
As per claim 6 combination of Miller – Jeong – Shen Orr teaches, the apparatus of claim 1, wherein the indication comprises at least one of a flag, register setting, or voltage on a pin (Miller Fig 2 para 29 and 32 teaches memory register setting).
As per claim 7 combination of Miller – Jeong – Shen Orr teaches, the apparatus of claim 1, wherein, to randomly reorder the execution order of the plurality of instructions, the processor is configured to apply a random permutation to the execution order of the plurality of instructions (Miller 22-23, 25 – Fig 7 para 48-49 teaches Fig 7 element 164 - unit randomizer which operates to select ordering and locations of control data in random order).
As per claim 8 combination of Miller – Jeong – Shen Orr teaches, the apparatus of claim 7, further comprising a reordering buffer, and wherein, to randomly reorder the execution order of the plurality of instructions, the processor is further configured to load the plurality of instructions into the reordering buffer based on the random permutation to the execution order (Miller 52 and 55-56 teaches Fig 10 element 256 as local buffer memory and stores requisite translation tables to allow firmware to be used by the controller which is further randomized by element 164 for security purpose).
As per claim 9 combination of Miller – Jeong – Shen Orr teaches, the apparatus of claim 8, wherein, to execute the plurality of instructions in the random order, the processor is further configured to execute the plurality of instructions loaded into the reordering buffer in the random order (Miller 52 and 55-56 teaches Fig 10 element 256 as local buffer memory and stores requisite translation tables).
Claims 10 and 19,
Claims 10 and 19 are rejected in accordance with claim 1.
Claims 11 and 20,
Claims 11 and 20 are rejected in accordance with claim 2.
Claims 12 and 21,
Claims 12 and 21 are rejected in accordance with claim 3.
Claims 13 and 22,
Claims 13 and 22 are rejected in accordance with claim 4.
Claims 14 and 23,
Claims 14 and 23 are rejected in accordance with claim 5.
Claims 15 and 24,
Claims 15 and 24 are rejected in accordance with claim 6.
Claims 16 and 25,
Claims 16 and 25 are rejected in accordance with claim 7.
Claims 17 and 26,
Claims 17 and 26 are rejected in accordance with claim 8.
Claims 18 and 27,
Claims 18 and 27 are rejected in accordance with claim 9.
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Porteboeuf et al US Patent 11537715
McKeen et al US Patent 9684608
Teglia et al US Publication 202500137535
Bachwani et al US Publication 20160188492
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIRAL S LAKHIA whose telephone number is (571)270-3363. The examiner can normally be reached on 8 am - 6 pm.
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/VIRAL S LAKHIA/Primary Examiner, Art Unit 2431
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