DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 7, 8, 10-12, 14, 15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,321,625 to Gambetta et al. (“Gambetta”) in view of US Pub. No. 2022/0114468 to Bravyi et al. (“Bravyi”).
As to independent claim 15, and similarly recited independent claims 1 and 8, Gambetta teaches:
a system (Fig. 2) comprising: a memory that stores program instructions (Fig. 2: 208, 201, 224, 226); a processor that executes the program instructions stored in the memory (Fig. 2: 226, 201, 230), wherein executing the program instructions cause the system to: receive a quantum circuit design comprising (Abstract, 2:25-37, 48-65, 6:32-44, 7:19-41. Gambetta teaches producing a configuration of a first quantum circuit and identifying a portion of that first quantum circuit that can be transformed to satisfy a constraint on the quantum circuit design. Gambetta also explains quantum processor configuration information can include restrictions on which qubits can interact, and that transformation operations can adapt a generic quantum circuit to a specific quantum processor configuration.); and
generate, using a machine learning model, a replacement circuit based on the one or more circuit restrictions (5:11-20, 8:17-49. Gambetta teaches a transformation operation reconfigures a quantum circuit into a different but equivalent quantum circuit. A transformation generator may use a model trained to generate transformation operations, including examples such as RNN/LSTM and GAN models. Because the transformation operation is generated or selected to satisfy the quantum circuit design constraint, the resulting replacement/transformed circuit is based on the circuit restriction.); and generate a modified quantum circuit design by replacing a portion of the quantum circuit with the replacement circuit (4:24-34, 6:55-65, 7:1-17, 8:50-54. Gambetta teaches pattern-based optimization can replace a circuit portion with a known replacement, and that three CNOT gates arranged in a suitable configuration may be replaced with a different, equivalent configuration, and that a CNOT operation may be replaced by a multi-CNOT circuit to satisfy a processor connectivity restriction. Gambetta further teaches executing the resulting transformed quantum circuit.).
Gambetta does not explicitly teach the received quantum circuit design comprises a Clifford circuit representation, or that the replacement circuit is generated based on the Clifford circuit representation, or that the modified quantum circuit design is generated by replacing the Clifford circuit representation with the replacement circuit.
Bravyi teaches the Clifford specific limitations. Bravyi teaches Clifford circuits represent a useful subset of quantum circuits and that Clifford circuits are composed of quantum gates including Hadamard, Phase, and CNOT gates (¶ 0035). Bravyi further teaches each Clifford circuit implements an element of the Clifford group and that a given Clifford group element may be implemented by many different Clifford circuits (¶ 0035). Bravyi also teaches receiving a Clifford representation as an input, namely to receive as input a first Clifford group element (Abstract, ¶ 0010, 0124).
Bravyi further teaches replacing or optimizing Clifford representation with another Clifford implementation. Bravyi discloses identifying a second Clifford group element that implements the first Clifford group element and has lower entangling-gate cost (¶ 0126, Abstract). Bravyi also teaches a compiling component that receives a suboptimal n-qubit Clifford operator and identifies an optimial n-qubit Clifford operator that implements the suboptimal operator using fewer CNOT gates (¶ 0117). Bravyi further explains that, for purposes of its disclosure, Clifford circuits are used interchangeably with Clifford operators, and that a Clifford operator can be represented in tableaux format (¶ 0128). Thus, Bravyi’s first Clifford group element, suboptimal Clifford operator, Clifford circuit, or Clifford tableaux representation corresponds to the claimed Clifford circuit representation, and Bravyi’s optimal Clifford operator/circuit corresponds to the claimed replacement circuit for that Clifford representation.
It would have been obvious to a PHOSTIA to modify Gambett’s machine-learning quantum circuit optimizer so that the circuit portion being optimized is the Clifford circuit representation taught by Bravyi, and so that Gambetta’s machine learning model generates a replacement circuit for that Clifford representation based on circuit restrictions. A PHOSITA would have recognized Bravyi’s Clifford circuit representation as a known type of quantum circuit portion suitable for optimization by Gambetta’s machine-learning based transformation system.
As to claim 7 and similarly recited claim 14, the computer-implemented method of claim 1, wherein the one or more circuit restrictions comprises gate times, error rates or connectivity restrictions (Gambetta: 4:44-50, ).
As to claim 17 and similarly recited claims 3 and 10, the system of claim 15, wherein the generating the replacement circuit comprises: generating a plurality of circuits based on the Clifford circuit representation; and selecting the replacement circuit from the plurality of circuits based on a defined preference metric (Bravyi: ¶ 0055, 0056, Gambetta: 16:31-37, 51-53. Bravyi teaches generating/selecting Clifford circuits based on a Clifford representation and a defined preference meteric, namely CNOT cost. Gambetta teaches generating multiple candidate replacement circuits and selecting/evaluating one based on a defined preference metric, such as efficiency, gate count, and execution time.).
As to claim 18 and similarly recited claims 4 and 11, the system of claim 17, wherein the defined preference metric comprises at least one of a number of Controlled Not (CNOT) gates, a number of circuit layers with CNOT gates, circuit length or circuit noise (Bravyi: ¶ 0038).
As to claim 19 and similarly recited claims 5 and 12, the system of claim 15, wherein the computer executable components further comprise: a performance component that determines a performance metric between the quantum circuit design and the modified quantum circuit design; and a training component that retrains the machine learning component based on maximizing the performance metric and the modified quantum circuit design (Gambetta: 8:55-58, 9:3-6, 34-56. Gambetta’s “efficiency score”, “score improvement”, and “train a model” read on the claim limitations.).
Claims 6, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gambetta in view of Bravyi and in further view of NPL Quantum Circuit Optimization with Deep Reinforcement Learning to Fosel et al. (“Fosel”).
The combination of Gambetta and Bravyi teach all the limitations of claims 1, 8, and 15 from which claims 6, 13, and 20 depend. The combination, however, does not teach the machine learning component comprises a reinforcement learning model.
Fosel teaches an approach to quantum circuit optimization based on reinforcement learning in which an agent, realized by a deep convolutional neural network, learns strategies to optimize arbitrary circuits on a specific architecture (Abstract).
It would have been obvious to a PHOSITA to implement Gambetta’s machine learning model as a reinforcement learning model, as taught by Fosel, to perform quantum circuit optimization by learning optimization strategies for arbitrary circuits on a specific architecture and optimize user chosen targets.
Allowable Subject Matter
Claims 2, 9, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2, 9, and 16 would be allowable if amended in the manner above because the prior art of record does not teach or suggest a method, CRM, or system having all the combinations of steps or elements as recited in and required by dependent claims 2, 9, or 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851
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