Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species D and Species E, identified as encompassing Claims 1-7 and 10-16 in the reply filed on February 12, 2026 is acknowledged.
Note by the Examiner
For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the same area" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim. The limitation is not defined in a prior claim nor further defined in the specification. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, and 13-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Moitzi et al. (US 2021/0112666 A1), hereinafter as M1.
Regarding Claim 1, M1 discloses a power device cell (see FIG. 1, elements 1 and 5, [0060] “component carrier 1”, [0064] “component 5” where the component is described as an electronic power device [0019] “at least one component is in particular selected from a group consisting of an electronic component”), comprising:
a metallic body (see FIG. 1, element 4, [0064] “electrically conductive base structure 4 which can form a kind of lead frame”) having a first main surface (see FIG. 1 where the first main surface is at the top of the base structure 4), a second main surface opposite the first main surface (see FIG. 1 where the second main surface is at the bottom of the base structure 4), and a side face vertically extending between the first main surface and the second main surface (see FIG. 1 where a side surface extends from the bottom to the top of the base structure 4);
a vertical power semiconductor die (see FIG. 1, elements 5, 7, and 8 and [0077] “the component 5 is a MOSFET having a drain terminal 8 at one side and a source terminal 7 and a gate terminal 7 at the opposite side” which is a vertical power device) in a recess formed in the first main surface of the metallic body (see FIG. 1 where the component 5 is embedded within the base structure 4); and
an organic and/or glass electrical insulator (see FIG. 1, element 2, [0061] “electrically insulating layer structure 2” and [0062] “electrically insulating layer structure 2 can comprise at least one of the group consisting of resin, in particular reinforced or non-reinforced resin, for instance epoxy resin or Bismaleimide-Triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based build-up film, polytetrafluoroethylene, a ceramic, and a metal oxide” which includes organic materials (i.e. polyimide, polyamide, and epoxy) and/or glass) covering the second main surface of the metallic body (see FIG. 1 where the insulating layer structure 2 is disposed on the bottom of the base structure 4) such that the power device cell (element 1) is electrically insulated at least at a first side that includes the organic and/or glass electrical insulator (see FIG. 1 where the insulating layer structure 2 continues to the sides of the base structure 4),
wherein the organic and/or glass electrical insulator (element 2) is confined to the metallic body (see FIG. 1 where the insulating structure layer 2 is confined and attached to the base structure 4),
wherein a backside of the vertical power semiconductor die is configured to be at a different electric potential than a frontside of the vertical power semiconductor die (see FIG. 1 where the component 5 previously described to be a MOSFET having a source terminal 7 at the top and drain terminal 8 at the bottom of component 5, and would therefore need to have a different electrical potential at the top and bottom of the component 5 for the MOSFET to function properly for the voltage from the source terminal 7 to flow down to the drain terminal 8),
wherein the metallic body (element 4) is at the same electric potential as the backside of the vertical power semiconductor die (see FIG. 1 where the base structure 4 would have to the same electrical potential as the drain terminal 8 at the bottom for the voltage to flow into the metal base structure as a MOSEFT functions).
Regarding Claim 2, M1 discloses the power device cell of claim 1, wherein the organic and/or glass electrical insulator (element 2) is part of a foil (see FIG. 1 element 16a, [0072] “base copper layer 16a which can be a copper foil adhered or laminated on an electrically insulating layer structure 2”) to the second main surface of the metallic body (see FIG. 1 where the insulating layer structure 2 and copper layer 16a are disposed at the bottom of the metal base structure 4).
Regarding Claim 3, M1 discloses the power device cell of claim 1, wherein the organic and/or glass electrical insulator (element 2) is a resist, glue, (see [0078] “the electrically insulating layer structure 2 can be an adhesive”) that coats the second main surface of the metallic body (see FIG. 1 where the insulating layer structure 2 is disposed below the metal base structure 4).
Regarding Claim 4, M1 discloses the power device cell (element 5) of claim 1, wherein the organic and/or glass electrical insulator (element 2) comprises plastic (see [0062] “electrically insulating layer structure 2 can comprise at least one of the group consisting of…for instance epoxy resin, polyphenylene derivate, prepreg material, polyimide, polyamide” which are plastics or plastic derivatives).
Regarding Claim 5, M1 discloses the power device cell of claim 1, wherein the organic and/or glass electrical insulator (element 2) is a glass cloth (see FIG. 1 and [0062] “electrically insulating layer structure 2 can comprise at least one of the group consisting of…glass”).
Regarding Claim 13, M1 discloses the power device cell of claim 1, further comprising a metallic layer (element 16a) covering a side of the organic and/or glass electrical insulator (element 2) that faces away from the metallic body (see FIG. 1, where the copper layer 16a covers the bottom side of the insulating structure 2 and faces away from the metal base structure 4).
Regarding Claim 14, M1 a power electronics assembly (see [0090] “manufacturing method can be split into manufacturing a high current PCB”), comprising:
a printed circuit board (see FIG. 5 and FIG. 4, [0095] “In the embodiment of FIG. 5, the inner component carrier 100 is composed of the base structure 4, which additionally comprises the sintered layer 17 and the thick copper layer 18, the component 5, and optionally the core 9, the copper layer(s) 10, 11 and the copper layer(s) 15, 16 provided in the base concept depicted in FIGS. 2 to 4”, where the carrier 100 as shown in FIG. 4 is present within FIG. 5, and [0090] “a high current PCB, i.e. the inner component carrier 100”);
and a power device cell (see FIG. 5 and FIG. 4, elements 1 and 5, [0060] “component carrier 1”, [0064] “component 5” where the component is described as an electronic power device [0019] “at least one component is in particular selected from a group consisting of an electronic component”) embedded in the printed circuit board (see FIG. 5 and [0090] “embedded components 5 in an inner PCB lead frame 100” which as mentioned prior is composed in the PCB inner component carrier 100),
wherein power device cell (element 5), comprises:
a metallic body (see FIG. 5, element 4, [0064] “electrically conductive base structure 4 which can form a kind of lead frame”) having a first main surface (see FIG. 5 where the first main surface is at the top of the base structure 4), a second main surface opposite the first main surface (see FIG. 5 where the second main surface is at the bottom of the base structure 4), and a side face vertically extending between the first main surface and the second main surface (see FIG. 5 where a side surface extends from the bottom to the top of the base structure 4);
a vertical power semiconductor die (see FIG. 5, elements 5, 7, and 8 and [0077] “the component 5 is a MOSFET having a drain terminal 8 at one side and a source terminal 7 and a gate terminal 7 at the opposite side” which is a vertical power device) in a recess formed in the first main surface of the metallic body (see FIG. 5 where the component 5 is in the base structure 4); and
an organic and/or glass electrical insulator (see FIG. 5, element 2, [0061] “electrically insulating layer structure 2” and [0062] “electrically insulating layer structure 2 can comprise at least one of the group consisting of resin, in particular reinforced or non-reinforced resin, for instance epoxy resin or Bismaleimide-Triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based build-up film, polytetrafluoroethylene, a ceramic, and a metal oxide” which includes organic materials (i.e. polyimide, polyamide, and epoxy) and/or glass) covering the second main surface of the metallic body (see FIG. 5 where the insulating layer structure 2 is disposed on the bottom of the base structure 4) such that the power device cell (element 1) is electrically insulated at least at a first side that includes the organic and/or glass electrical insulator (see FIG. 5 where the insulating layer structure 2 continues to the sides of the base structure 4),
wherein the organic and/or glass electrical insulator (element 2) is confined to the metallic body (see FIG. 5 where the insulating structure layer 2 is confined and attached to the base structure 4),
wherein a backside of the vertical power semiconductor die is configured to be at a different electric potential than a frontside of the vertical power semiconductor die (see FIG. 5 where the component 5 previously described to be a MOSFET having a source terminal 7 at the top and drain terminal 8 at the bottom of the component 5, and would therefore need to have a different electrical potential at the top and bottom of the component 5 for the MOSFET to function properly for the voltage from the source terminal 7 to flow down to the drain 8),
wherein the metallic body is at the same electric potential as the backside of the vertical power semiconductor die (see FIG. 5 where the base structure 4 would have to the same electrical potential as the drain terminal 8 at the bottom for the voltage to flow into the metal base structure as a MOSEFT functions).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. as being unpatentable over Moitzi et al. (US 2021/0112666 A1), hereinafter as M1, in view of Chou et al. (TW 591700 B, see attached translation), hereinafter as C1.
Regarding Claim 7, M1 discloses the power device cell of claim 1, but does not explicitly disclose wherein the organic and/or glass electrical insulator has the same area as the second main surface of the metallic body.
C1 discloses wherein the organic and/or glass electrical insulator (see FIG. 1, element 104, and pg. 2 par. 2 “dielectric layer 104 It is necessary to use a dielectric material capable of having excellent adhesion with metals as a capacitor dielectric layer, such as chemical vapor deposition (CVD) Si02, SiN, or SiON” which are known organic electrical insulators) has the same area as the second main surface of the metallic body (see FIG. 1, elements 102 and 106, and pg. 1 par. 3 “a metal lower electrode plate 102, and then form a metal upper electrode plate 106” which can be seen having the same length and width as the dielectric layer 104, and therefore having the same area).
The insulating layer and metallic layer having equal area relative to each other in C1 is incorporated into the layers relative area of M1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C1 with M1 because the combination allows for equal capacitance within a device package area (C1 pg. 1 Abstract); and the combination is a simple known technique of varying the area to obtain predictable results – varying the area of package structure layers is a known technique for package management and optimization to obtain predictable results.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being anticipated over Moitzi et al. (US 2021/0112666 A1), hereinafter as M1, in view of Tomohiro (JP 2013149744 A, see attached translation), hereinafter as T1.
Regarding Claim 10, M1 discloses the power device cell of claim 1, but does not explicitly disclose wherein the organic and/or glass electrical insulator has a thickness in a range of 5mm to 0.01mm.
T1 discloses wherein the organic and/or glass electrical insulator (see FIG. 2, element 21, pg. 3 par. 4 “the insulating base material, for example, a glass epoxy substrate”) has a thickness in a range of 5mm to 0.01mm (see pg. 3 par. 4 “the insulating base material 21, for example, a glass epoxy substrate having a thickness of 0.2 mm can be used”).
The insulator thickness as taught by T1 is incorporated as the thickness for the insulating structure of M1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of T1 with M1 because the combination allows for managed optimization within a device package; and the combination is a simple known technique of varying structure thickness to obtain predictable results – varying the thickness of a package structure is a known technique for package management and optimization to obtain predictable results.
Regarding Claim 11, M1 and T1 disclose the power device cell of claim 10, where T1 further discloses wherein the thickness of the organic and/or glass electrical insulator (FIG. 2, element 21) is in a range of 2mm to 0.05mm (see pg. 3 par. 4 “the insulating base material 21, for example, a glass epoxy substrate having a thickness of 0.2 mm can be used”).
The insulator thickness as taught by T1 is incorporated as the thickness for the insulating structure of M1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of T1 with M1 because the combination allows for managed optimization within a device package; and the combination is a simple known technique of varying structure thickness to obtain predictable results – varying the thickness of a package structure is a known technique for package management and optimization to obtain predictable results.
Claim 12 is rejected under 35 U.S.C. as being unpatentable over by Moitzi et al. (US 2021/0112666 A1), hereinafter as M1, in view of Peterson et al. (US 20190252286 A1), hereinafter as P1.
Regarding Claim 12, M1 discloses the power device cell of claim 1, but does not explicitly disclose wherein the power device cell has a thickness tolerance of +/- 100 microns, including the organic and/or glass electrical insulator.
P1 discloses wherein the power device cell has a thickness tolerance of +/- 100 microns, including the organic and/or glass electrical insulator (see FIG. 7, see elements 126 and 104, [0048] “126 substrate”, [0021] “heat sources 104a-104i may be a heat generating device” in this case an electronic component as described prior, and [0018] “substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure” where this is the organic and/or glass insulator of this device package. Furthermore, see [0029] “die thickness tolerances and package assembly tolerances can cause as-built die heights to vary on the order of about ten (10) to about twenty (20) micrometers” which encompasses both the power cell of the device and the insulator within the range presented).
The thickness tolerance range as disclosed by P1 is incorporated as a thickness tolerance for M1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with M1 because the combination allows for optimization of fit and functionality within the device (P1 [0029]); and the combination is a simple known technique of varying thickness tolerance to obtain predictable results – varying the thickness tolerance of a package structure is a known technique for package management and optimization to obtain predictable results.
Claim 15 is rejected under 35 U.S.C. 103 as being anticipated by Moitzi et al. (US 2021/0112666 A1), hereinafter as M1, in view of Gong et al. (CN 102403236 A, see attached translation), hereinafter as G1.
Regarding Claim 15, M1 discloses the power device cell of claim 14, further comprising a metallic layer (element 3) covering a side of the organic and/or glass electrical insulator (element 2) that faces away from the metallic body (see FIGs. 1 and 5, where the conductive layer structure 3 covers the bottom side of the insulating structure 2 and faces away from the metal base structure 4) and
M1 does not disclose wherein the metallic layer of the power device cell is attached to a metallic layer of the printed circuit board.
G1 discloses wherein the metallic layer (see FIG. 2, element 113, pg. 5 par 6 “backside metal layer 113”) of the power device cell (see FIG. 2, element 100, pg. 5 par. 5 “semiconductor device 100”) is attached to a metallic layer of the printed circuit board (see pg. 6 par 7 “using surface mount technology (SMT) assembling the semiconductor device 100 on to a printed circuit board (PCB), the back metal layer is exposed 113 through welding materials such as solder paste welding on to heat welding plate of the PCB, so that the semiconductor device 100 soldered on the PCB” and pg. 7 par. 1 “generally, the backside metal layer…is directly welded on the PCB circuit board” showing the direct attachment of the metal layer 113 of the semiconductor 100 to a PCB).
The arrangement of metallic layers of the electronic components in relation to the PCB as disclosed by G1 is incorporated into the disclosure of M1. It would have been obvious to one with ordinary skill in the art at the time of filing to incorporate the teaching of G1 with M1 as there is motivation to properly regulate the conductivity and current flow of power cell device on a printed circuit board to yield predictable results – by having direct contact of the metal layers, the layers can be altered separately to properly regulate the flow of current through the device. For example, the two layers could be doped at different levels for a desired outcome. This management of current flow through separate metallic layers yield predictable results (see G1 pg. 6 par. 7).
Claim 16 is rejected under 35 U.S.C. 103 as being anticipated by Moitzi et al. (US 2021/0112666 A1), hereinafter as M1, in view of Gottwald (US 10964635 B2), hereinafter as G2.
Regarding Claim 16, M1 discloses the power electronics assembly of claim 14,
M1 discloses the organic and/or glass insulator (element 2) of the power cell device (element 5)
M1 does not disclose wherein a laminated structure of the printed circuit board covers the organic and/or glass electrical insulator of the power device cell, and wherein the laminated structure of the printed circuit board comprises one or more electrically conductive layers and one or more electrically insulating layers.
However, G2 discloses wherein a laminated structure of the printed circuit board (see FIG. 13 elements 42, 44, and 46, and col. 5 ln. 53 “a circuit board base frame 40 made of circuit board material 42…the copper lamination consist of a top copper layer 44 and a bottom copper layer 46” where the circuit board material 42 is seen between these two layers) covers the organic and/or glass electrical insulator (element 2 of M1) of the power device cell (element 5 of M1), and wherein the laminated structure of the printed circuit board comprises one or more electrically conductive layers and one or more electrically insulating layers (copper layers 44 and 46 are electrically conductive due to being made of copper and see col. 5 ln. 53 “a circuit board carrier material 42 (for example made of FR4)” which is a plastic electrical insulator. The laminated structure of G2 that covers the acting insulator ceramic carrier 14, col 3 ln. 64 “ceramic carrier 14” is being implemented into M1, since the insulator of G2 is not organic and/or a glass).
The laminated structure of the printed circuit board comprising electrically conductive layers as disclosed by G2 is integrated into the disclosure of M1. It would’ve been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of M1 and G2 because the combination allows for proper connection and insulation between the power cell device and the PCB; the combination is simple substitution of one element for another to obtain predictable results – simple substitution of a laminate board on the bottom of the device yields predictable results (see G2 col. 2 ln. 45-57)
Allowable Subject Matter
Claim 6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest art least the claim limitations of:
Claim 6, “the glass cloth is part of a layer stack that also includes an aluminum foil interposed between the glass cloth and the second main surface of the metallic body, an adhesive applied to a side of the glass cloth that faces away from the aluminum foil, and a liner applied to a side of the adhesive that faces away from the glass cloth” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter. At the time of filing, there are no claims depending on Claim 6.
Conclusion
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/B.S.C./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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