DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kalter et al. (US 5,899,703).
Regarding claim 1, Kalter discloses a manufacturing method of an electronic component (Abstract), comprising the steps of: providing an insulating layer (25) including a first region and a second region; providing a first metal layer (left one of 26, second from top, as viewed, shown within layer 24) disposed in the first region of the insulating layer; providing a second metal layer (top-left ones of 26, as viewed) disposed on the first metal layer; providing a metal line (13/41) in the second region of the insulating layer, wherein the metal line is electrically connected to the first metal layer (figs. 2-3 and 7; col. 2, lines 26-55; col. 3, lines 20-27); and removing the metal line to form an electronic component, wherein the electronic component includes the insulating layer; and a first metal bump (the two cited layers of 26, exposed by removal of the metal line, 13, and of a portion of the insulating layer, 25) disposed on the insulating layer and *including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer (figs. 2-3 and 7; col. 2-3, lines 51-67 and 1-12; col. 3, lines 20-28).
*NOTE: Though not necessarily indefinite, the following claim language is found to be broad and open to subjective interpretation. The claim discloses “a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer”. The manner in which this limitation is presented indicates that the “first metal bump” comprises the first and second metal layers, which appears to be consistent with the instant specification and drawing figures. The claims have been interpreted in this manner such that the “first metal bump” is not an additional limitation or structure at all, but instead is nothing more than a re-naming of the noted existing structures in the claim.
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Regarding claim 2, Kalter discloses the method of claim 1, wherein, after the step of providing a metal line in the second region of the insulating layer, the metal line disposed in the second region of the insulating layer is used as an auxiliary circuit by which an electrical test instrument is used to test the electronic component (col. 2, lines 51-64; col. 2, lines 20-28).
Regarding claim 3, Kalter discloses the method of claim 1, wherein the electronic component further includes a second metal bump (right ones of 26) disposed on the insulating layer, wherein before the step of removing the metal line, a first metal line segment (left one of 13; and/or one of 41) of the metal line is electrically connected to the first metal layer of the first metal bump, and a second metal line segment (right one of 13; and/or another of 41) of the metal line is electrically connected to the second metal bump (figs. 2-3).
Regarding claim 4, Kalter discloses the method of claim 1, further comprising a step of forming a third metal layer (left one of 26 in layer 23) disposed on the second metal layer before the step of providing the metal line (figs. 2-3).
Regarding claim 5, Kalter discloses the method of claim 1, further comprising a step of providing a *third metal bump (right ones of 26), wherein the third metal bump is electrically connected to the first metal layer (figs. 2-3).
*NOTE: the term “third metal bump” is not found to be indefinite for lack of antecedent basis, because, though there is no “second metal bump” in claim 1, there is a second metal bump in claim 3 and it is currently understood that the use of the descriptor “third” in the instant claim is intended simply to differentiate that the instant bump may be a different bump than that which is disclosed in claim 3. That being so, given that the “second” and “third” metal bumps do not appear in a single claim dependency chain, they are not currently required to be distinct elements/structures from one another.
Regarding claim 6, Kalter discloses the method of claim 1, further comprising a step of providing a chip (10/43) electrically connected to the first metal layer (figs. 1-2 and 7; col. 2, lines 25-35; col. 3, lines 21-28).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the concurrently mailed PTO-892, as all of those cited references are considered to be pertinent to the claimed invention. For example, Chevallier (US 6,323,048 B2) is held to seemingly disclose all of the limitations of at least claim 1. Chevallier discloses manufacturing method (figs. 5A-5B), comprising the steps of: providing an insulating layer (200, 204); providing a first metal layer (240) disposed in the first region of the insulating layer; providing a second metal layer (250) disposed on the first metal layer; providing a metal line (220/230) in the second region of the insulating layer, wherein the metal line is electrically connected to the first metal layer; and removing the metal line to form an electronic component, (Abstract; figs. 2-4 and 6A-6C; cols. 5-6, lines 46-67 and 1-24). The Chevallier reference is not currently applied as an anticipation rejection due to the completeness of the above applied art, and in order to avoid an overly long Office Action or duplicative rejections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeffrey T Carley whose telephone number is (571)270-5609. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sunil Singh can be reached at (571)272-3460. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEFFREY T CARLEY/Primary Examiner, Art Unit 3729
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