Prosecution Insights
Last updated: October 02, 2026
Application No. 18/466,944

IMAGING DEVICE, SOLID STATE IMAGE SENSOR, AND ELECTRONIC DEVICE

Final Rejection §103
Filed
Sep 14, 2023
Priority
May 29, 2017 — JP 2017-105714 +3 more
Examiner
YEUNG LOPEZ, FEIFEI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Group Corporation
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
884 granted / 1088 resolved
+13.3% vs TC avg
Minimal -3% lift
Without
With
+-2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
36 currently pending
Career history
1123
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.2%
+15.2% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
17.3%
-22.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1088 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 14 is objected to because of the following informalities: feature “the lens group is disposed to not be in contact with the integrated assembly” is in claim 1 Appropriate correction is required. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1,4,6,8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arayama et al (PG Pub 2016/0091643 A1), Tomicoka et al (PG Pub 2010/0176281 A1), Hamada et al (PG Pub 2017/0283587 A1), and Shibazaki et al (PG Pub 2012/0140100 A1). Regarding claim 1, Arayama teaches an electronic apparatus comprising: a lens group (fig. 1); an integrated assembly comprising: a pixel array (12, figs. 1 and 2); and an optical assembly comprising: one or more materials (13, fig. 2) mounted with the pixel array in the integrated assembly; and wherein a width of a substrate including the pixel array is the same as a width of the optical assembly (see 100 where pixel array is formed and 42, which is a part of the optical assembly, layer 13 is also a part of the optical assembly, fig. 1); wherein the lens group is disposed to not be in contact with the integrated assembly (fig. 1). Arayama does not teach the lens group to comprise a plurality of lenses. In the same field of endeavor, Tomioka teaches a lens group comprises a plurality of lenses (20-23, fig. 1), for the benefit of reflecting undesirable light from the sensor (paragraph [0008], fig. 1). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the lens group to comprise a plurality of lenses, for the benefit of reflecting undesirable light from the sensor. Arayama does not teach the material (layer 13, fig. 2) to comprise a transparent material. It would have been obvious to the skilled in the art before the effective filing date of the invention to make layer 13 a transparent material for the known benefit of allowing light to reach light sensors 12. Arayama does not teach a light shield arranged to block light at a periphery of the integrated assembly. In the same field of endeavor, Hamada teaches a light shield (11, fig. 4) arranged to block light at a periphery of the integrated assembly (IR filter 6), for the benefit of reducing noise (paragraphs [0004]-[0006]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to arrange a light shield to block light at a periphery of the integrated assembly (periphery of IR filter 42, fig. 1 of Arayama), for the benefit of reducing noise. Arayama in view of Hamada teaches “wherein a part of the light shield is disposed on at least one of the one or more transparent materials.” Arayama does not teach a signal processing circuit arranged to receive signals from sensors in the pixel array; a memory arranged to store image data; a monitor arranged to display image data; and a control circuit configured to control transfer of signal electric charges in the integrated assembly. In the same field of endeavor, Shibazaki teaches a signal processing circuit (202, fig. 1, paragraph [0060]) arranged to receive signals from sensors in the pixel array; a memory (207/203) arranged to store image data; a monitor (209) arranged to display image data; and a control circuit (201) configured to control transfer of signal electric charges in a integrated assembly (image sensor), for the benefits of processing light into images for display. Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a signal processing circuit arranged to receive signals from sensors in the pixel array; a memory arranged to store image data; a monitor arranged to display image data; and a control circuit configured to control transfer of signal electric charges in the integrated assembly, for the benefits of processing light into images for display. Regarding claim 4, Arayama teaches the electronic apparatus of claim 1 further comprising: a glass substrate (30, fig. 2) affixed to the pixel array with an adhesive layer (20, paragraph [0492]); an infrared filter (42) affixed to the glass substrate; a non-flat film (46, whose bottom is not flat) affixed to the infrared filter. Hamada teaches a light shield (11, fig. 4) configured to block light at a periphery of the pixel array (3), wherein the light shield is disposed on the glass substrate or on the infrared filter (6). Regarding claim 6, Arayama teaches the integrated assembly electronic apparatus of claim 4, wherein the glass substrate (30, fig. 2) is affixed to the pixel array with no cavity between the glass substrate and the pixel array (figs. 1 and 2). Regarding claim 8, Arayama teaches the electronic apparatus of claim 4, wherein a width of a substrate (100, fig. 1) including the pixel array is the same as a width of the glass substrate (30). Allowable Subject Matter Claims 2,3,5,9-11,13,14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach “the integrated assembly further comprising a non-flat film disposed on the infrared filter” (claim 2); “wherein the pixel array and the adhesive layer are in direct contact with each other” (claim 5); “wherein the light shield is disposed on the transparent substrate” (claim 9). Response to Arguments Applicant’s arguments with respect to claim(s) 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 14, 2023
Application Filed
Mar 12, 2026
Non-Final Rejection mailed — §103
Jun 11, 2026
Response Filed
Aug 20, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
79%
With Interview (-2.7%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1088 resolved cases by this examiner. Grant probability derived from career allowance rate.

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