Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In regard to the amendments the Examiner notes that the amendments have overcome the previous rejection 35 USC 102 (a)(1) rejection anticipated by Kamgaing et al. (US 2020/0219861 A1; hereinafter “Kamgaing”) (see for example Examiner Interview Summary Record mailed 06/24/2026). However, as shown below Kamgaing anticipates the limitations of the amended claim 1.
In regard to applicants amended claim 14, the new limitations raise new issues that require a 35 USC 112(b) rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation " a dielectric-conductor stack of layers in contact with the second surface of the bonding conductive layer, wherein the dielectric-conductor stack of layers comprises: a portion of the first layer of the bonding conductive layer… " in lines12-14. There is insufficient antecedent basis for the imitation regarding the first layer of the bonding conductive layer in the claim (emphasis added). While the limitations of the claim regard a first layer in line 6, the first layer appears to be regarding the dielectric material layer where the bonding conductive material layer is to be made of conductive material.
Further, it is unclear how the dielectric-conductor stack layers are in contact with the second surface of the bonding conductive layer and also contains the first layer of the bonding conductive layer.
Claims 15-17 are rejected due to depending on claim 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 8, 12-13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kamgaing et al. (US 2020/0219861 A1; hereinafter “Kamgaing”).
In regard to claim 1, Kamgaing teaches an integrated circuit device (an integrated system 200) (Fig. 2 and paragraph 31), comprising:
a ceramic based substrate (a package substrate 108 is an inorganic package substrate such as a ceramic substrate) (Fig. 2 and paragraph 26);
a stack of layers in contact with the ceramic-based substrate (the layers containing an interposer interconnect structure 122 and an interposer 204 including all conductive components associated with said layers are in either direct or electrical contact with the package substrate 108 as shown in annotated Fig. 2 below) (Fig. 2 and paragraphs 17 and 31), the stack of layers comprising:
a bonding conductive layer (a plurality of contact pads 168) comprising a first surface (bottom surface) in contact with the ceramic-based substrate and a second surface (top surface) opposite to the first surface (the top and bottom surface of the plurality of contact pads 168 is shown in Fig. 2) (Fig. 2 and paragraph 25);
a dielectric-conductor stack of layers (an interposer interconnect structure 122) in contact with the second surface of the bonding conductive layer (the an interposer interconnect structure 122 is shown in electrical contact of the contact pads 168) (Fig. 2 and paragraph 18), wherein the dielectric-conductor stack of layers comprises:
an insulation layer (dielectric layers 126) (Fig. 2 and paragraph 18); and
a conductive layer (metal layer 124) comprising conductive traces embedded in the insulation layer (the metal layers 124 are shown embedded in the dielectric layers 126 in Fig. 2) (Fig. 2 and paragraph 18);
an electronic interface layer (seal frame 236) in contact with the dielectric-conductor stack of layers (the seal frame 236 is shown in contact with the interposer interconnect structure 122 in Fig. 2) (Fig. 2 and paragraph 20); and
electronic elements (active die 102 and active die 202) in contact with the electronic interface layer and electrically connected to the conductive layer (the active die 102 and active die 202 are shown in contact with the seal frame 236 and electrically connected to the metal layers 124) (Fig. 2 and paragraph 32), wherein the conductive layer is configured to route electrical signals to the electronic elements (while the interconnect structure 122 may include transmission lines, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987). Therefore the claim is met.)
In regard to claim 5, Kamgaing teaches, wherein:
the conductive layer is a first conductive layer (the metal layer 124 on the bottom functions as the first conductive layer) (Fig. 2);
the dielectric-conductor stack of layers further comprises a second conductive layer comprising conductive traces embedded in the insulation layer (the metal layer 124 directly above the metal layer 124 on the bottom functions as second conductive layer) (Fig. 2);
a first conductive trace of the second conductive layer is parallel to a first conductive trace (metal interconnect of the bottom metal layer 124) of the first conductive layer (the metal interconnects in the bottom metal layer 124 are shown stacked with and running parallel with the metal layer 124 in Fig. 2) (Fig. 2 and paragraph 18); and
a second conductive trace of the second conductive layer is parallel to a second conductive trace (metal interconnects of the metal layer 124 above the metal layer 124 on the bottom) of the first conductive layer (the metal layer 124 directly above the metal layer 124 on the bottom functions as second conductive layer and the interconnects are shown running parallel with the metal layer 124 in Fig. 2) (Fig. 2 and paragraph 18).
In regard to claim 8, Kamgaing teaches, wherein: the conductive layer is a first conductive layer (the metal layer 124 on the bottom functions as the first conductive layer) (Fig. 2);
the dielectric-conductor stack of layers further comprises a second conductive layer comprising conductive traces embedded in the insulation layer (the metal layer 124 directly above the metal layer 124 on the bottom functions as second conductive layer and contains interconnects embedded in the dielectric layers 126) (Fig. 2 and paragraph 18);
first and second conductive traces of the first conductive layer are configured to transmit signals (each of the metal layers 124 may contain a plurality of metal interconnects used to route signals and power to various devices and components) (paragraph 18);
a shield conductive trace (an interconnect layer of the capacitor 138 in interconnect structure 122 in the bottom most metal layer 124) of the first conductive layer is disposed between the first and second conductive traces of the first conductive layer (interconnect layer of the capacitor 138 in interconnect structure 122 located in the bottom most metal layer 124 is shown between two other interconnect structures in Fig. 2) (Fig. 2 and paragraph 22); and
a shield conductive trace of the second conductive layer is over the shield conductive trace of the first conductive layer (an interconnect layer of the capacitor 138 in interconnect structure 122 located in the metal layer above bottom most metal layer 124 is shown over the interconnect layer of the capacitor 138 in interconnect structure 122 in the bottom most metal layer 124) (Fig. 2).
In regard to claim 12, Kamgaing teaches wherein the ceramic-based substrate is a high-temperature, co-fired ceramic substrate (package substrate 108 may be a high temperature co-fired ceramic substrate) (paragraph 26).
In regard to claim 13, Kamgaing teaches wherein the bonding conductive layer comprises a conductive plane between the insulation layer and the ceramic-based substrate (plurality of contact pads 168 create a conductive plane between the package substrate 108 and interposer interconnect structure 122 as shown in Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Kwon et al. (US 2016/0064328 A1; hereinafter “Kwon”) and Lin et al. (US 2017/0005073 A1; hereinafter “Lin”)
In regard to claim 2, Kamgaing doesn’t explicitly wherein: the insulation layer is a silicon dioxide layer; and the conductive layer is an aluminum layer having a thickness of about 5 microns to about 10 microns.
Kwon teaches an integrated circuit device (an electronic device 100) (Fig. 1 and paragraph 20), wherein an insulation layer (a dielectric 108) is a silicon dioxide layer (the dielectric 108 may be silicon dioxide) (Fig. 1 and paragraph 22).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Kwon to have the insulation layer be a silicon dioxide layer since silicon dioxide is a well-known dielectric oxide and it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Lin teaches an integrated circuit device (a semiconductor device as shown in Fig. 8), wherein a conductive layer (a first RDL 801) is an aluminum layer having a thickness of about 5 microns to about 10 microns (the first RDL 801 may comprise two conductive layers formed of metals such as aluminum, copper, tungsten, titanium, and combinations and may be between about 2 μm and about 30 μm, such as about 5 μm) (Fig. 8 and paragraph 38).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Lin to have the conductive layer be an aluminum layer having a thickness of about 5 microns to about 10 microns. since this allows for multiple connections to be made throughout the device as taught by Kamgaing (paragraph 67).
In regard to claim 3, Kamgaing teaches wherein:
the conductive layer is a first conductive layer (the metal layer 124 on the bottom functions as the first conductive layer) (Fig. 2);
the dielectric-conductor stack of layers further comprises a second conductive layer comprising conductive traces embedded in the insulation layer (the metal layer 124 directly above the metal layer 124 on the bottom functions as second conductive layer) (Fig. 2).
However, Kamgaing doesn’t explicitly teach the second conductive layer is an aluminum layer having a thickness of about 5 microns to about 10 microns.
Lin teaches an integrated circuit device (a semiconductor device as shown in Fig. 8), wherein a conductive layer (a first RDL 801) is an aluminum layer having a thickness of about 5 microns to about 10 microns (the first RDL 801 may comprise two conductive layers formed of metals such as aluminum, copper, tungsten, titanium, and combinations and may be between about 2 μm and about 30 μm, such as about 5 μm) (Fig. 8 and paragraph 38).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Lin to have the second conductive layer be an aluminum layer having a thickness of about 5 microns to about 10 microns. since this allows for multiple connections to be made throughout the device as taught by Kamgaing (paragraph 67).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Liu et al. (US 2023/0141681 A1).
In regard to claim 4, Kamgaing doesn’t explicitly teach wherein the electronic elements comprises an array of photodetector elements configured to receive illumination and to generate information signals according to an image associated with the received illumination, and wherein the conductive traces are configured to transmit the information signals.
Liu teaches an integrated circuit device (an image sensor 2100) (Fig. 22 and paragraph 43), wherein electronic elements comprises an array of photodetector elements (four photodiodes 2004a-2004d) configured to receive illumination and to generate information signals according to an image associated with the received illumination (Fig. 21, Fig. 22 and paragraph 41), and wherein conductive traces (a plurality of wires 2126) are configured to transmit the information signals (the light then interacts with the first photodetector 2004a to be transformed into an electrical signal, which is processed by circuitry of the photodetectors an image device interconnect structure 2124 which contains the polarity of wires 2126) (Fig. 22 and paragraphs 48 and 50).
It would’ve been obvious one of ordinary skill in the art to combine the teachings of Kamgaing with the teachings of Liu to have the electronic elements comprises an array of photodetector elements configured to receive illumination and to generate information signals according to an image associated with the received illumination, and have the conductive traces configured to transmit the information signals since this layout is well known to allow the device to act as a camera or image sensor as taught by Liu (paragraphs 2-3 and 43).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Wei et al. (US 2004/0222506 A1; hereinafter “Wei”)
In regard to claim 6, Kamgaing doesn’t explicitly teach wherein a separation between the first conductive trace of the first conductive layer and the first conductive trace of the second conductive layer is about 10 microns to about 15 microns.
Wei teaches an integrated circuit device (an integrated circuit die 102) (Fig. 6 and paragraph 33), wherein a separation between a first conductive trace of a first conductive layer and a first conductive trace of the second conductive layer is about 10 microns to about 15 microns (the vertical spacing between re-distribution layers RM1, RM2, and RM3 is preferably approximately 10 microns) (Fig. 6 and paragraph 34).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Wei to have a separation between the first conductive trace of the first conductive layer and the first conductive trace of the second conductive layer be about 10 microns to about 15 microns since this allows a the device to be provided with good electromagnetic shielding as taught by Wei (paragraphs 10-11 and 31).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Yeong et al. (US 2022/0359550 A1; hereinafter “Yeong”)
In regard to claim 10, Kamgaing doesn’t explicitly teach wherein one or more of the electronic elements comprises a tunable ferroelectric capacitor.
Yeong teaches an integrated circuit device (a semiconductor device 100) (Fig. 1 and paragraph 21), wherein one or more of electronic elements comprises a tunable ferroelectric capacitor (a ferroelectric tunable capacitor is fabricated at a same level in an RF circuit region of the chip) (Fig. 1 and paragraph 20)
It would’ve been obvious to combine the teachings of Kamgaing with the teachings of Yeong to have one or more of the electronic elements comprises a tunable ferroelectric capacitor since this enables the device to do high-frequency applications as taught by Yeong (paragraph 24).
In regard to claim 11, Kamgaing doesn’t explicitly teach wherein one or more of the electronic elements comprises an integrated ferrite configured to filter noise comprising a frequency component of about 5 GHz or greater.
Yeong teaches wherein one or more of the electronic elements comprises an integrated ferrite (ferroelectric structure 122A ) configured to filter noise comprising a frequency component of about 5 GHz or greater (Fig. 1 and paragraph 24). While Yeong does not explicitly teach the ferroelectric structure 122A is configured to filter noise comprising a frequency component of about 5 GHz or greater, the examiner notes intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable to performing the intended use, and then it meets the claim. Therefore, since the ferroelectric structure 122A is able to be used in an RF filter the claim limitation is met.
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Lee et al. (US 2024/0178206 A1; hereinafter “Lee”).
In regard to claim 21, Kamgaing teaches wherein:
the insulation layer comprises a plurality of insulation sublayers (a plurality of dielectric layers 126 are shown in Fig. 2),
an insulation sublayer of the plurality of insulation sublayers is above and in contact with the conductive layer (dielectric layers 126 are shown above and in contact with the metal layer 124 in Fig. 2).
Kamgaing doesn’t explicitly teach a ratio of a thickness of the conductive layer to a thickness of the insulation sublayer above the conductive layer is about 0.5:1 to about 2:1.
Lee teaches an integrated circuit device (an electronic device 10) (Fig. 1 and paragraph 28), wherein:
an insulation sublayer (one of a plurality of layers that comprise a dielectric structure 111) of the plurality of insulation sublayers is above and in contact with a conductive layer (a dielectric layer above embedded traces 1123) (Fig. 2A, paragraphs 30 and 32), and
a ratio of a thickness of the conductive layer to a thickness of the insulation sublayer above the conductive layer is about 0.5:1 to about 2:1 (the thickness of the layers of the dielectric structure 111 can range from approximately 3 μm to approximately 100 μm, and the thicknesses of embedded traces 1123 can range from approximately 3 μm to approximately 50 μm. Therefore the ratio range is met).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Lee to have a ratio of a thickness of the conductive layer to a thickness of the insulation sublayer above the conductive layer is about 0.5:1 to about 2:1 since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
.
In regard to claim 22, Kamgaing teaches wherein:
the insulation layer comprises a plurality of insulation sublayers (a plurality of dielectric layers 126 are shown in Fig. 2),
an insulation sublayer of the plurality of insulation sublayers is above and in contact with the conductive layer (dielectric layers 126 are shown below and in contact with the metal layer 124 in Fig. 2).
Kamgaing doesn’t explicitly teach a ratio of a thickness of the conductive layer to a thickness of the insulation sublayer above the conductive layer is about 1:1 to about 3:1.
Lee teaches an integrated circuit device (an electronic device 10) (Fig. 1 and paragraph 28), wherein:
an insulation sublayer (one of a plurality of layers that comprise a dielectric structure 111) of the plurality of insulation sublayers is above and in contact with a conductive layer (a dielectric layer above embedded traces 1123) (Fig. 2A, paragraphs 30 and 32), and
a ratio of a thickness of the conductive layer to a thickness of the insulation sublayer above the conductive layer is about 1:1 to about 3:1 (the thickness of the layers of the dielectric structure 111 can range from approximately 3 μm to approximately 100 μm, and the thicknesses of embedded traces 1123 can range from approximately 3 μm to approximately 50 μm. Therefore the ratio range is met).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Lee to have a ratio of a thickness of the conductive layer to a thickness of the insulation sublayer above the conductive layer is about 1:1 to about 3:1 since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sahin et al. (US 2022/0268994 A1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights