DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Applicant’s election without traverse of Group I, represented by claims 1-13, as well as amended claims 14, 18, and 19 and their dependent claims 15-17 and 20 in the reply filed on 03/26/2026 is acknowledged.
The Examiner agrees with applicant that the amended claims of Group II do negate the previous restriction, as the amended combination does require the particulars of the sub-combination. However, the amended claim 18 as well as the dependent claims 19 and 20 still do not overcome the previous restriction requirement, as the device the device of inventions I/II can be formed through a materially different method, the device does not require the deposition of silicon dioxide layers. Therefore, the restriction is maintained as well as final, and claims 18-20 are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the waveguide stack" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 is rejected due to depending on claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 7-9, 12-13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kamgaing et al. (US 2020/0219861 A1; hereinafter “Kamgaing”).
In regard to claim 1, Kamgaing teaches an integrated circuit device (an integrated system 200) (Fig. 2 and paragraph 31), comprising:
a ceramic-based substrate (a package substrate 108 is an inorganic package substrate such as a ceramic substrate) (Fig. 2 and paragraph 26);
a stack of layers disposed on the ceramic-based substrate (the layers containing active die 202, active die 102, an interposer interconnect structure 122 and an interposer 204 including all conductive components associated with said layers) (Fig. 2 and paragraphs 17 and 31), the stack of layers comprising:
an insulation layer (dielectric layers 126) (Fig. 2 and paragraph 18); and
a conductive layer (a layer annotated as first in Fig. 2 below) comprising conductive traces (the layer annotated as first that contains contact pads 152 on backside 125 of substrate 120) (Fig. 2 and paragraph 23); and
electronic elements (active dies 102 and 202) electrically connected to the conductive layer (the active dies 102 and 202 are electrically connected to the contact pads 152 on backside 125 of substrate 120 through the lower most metal layer 124) (Fig. 2 and paragraph 23), wherein the conductive layer is configured to route electrical signals to the electronic elements (while the contact pads 125 route signals to the active dies, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987). Therefore, the claim is met by the contact pads being electrically connected to the active dies).
PNG
media_image1.png
544
834
media_image1.png
Greyscale
In regard to claim 5, Kamgaing teaches wherein:
the conductive layer is a first conductive layer (the layer annotated as first contains contact pads 152 on backside 125 of substrate 120) (Fig. 2 and paragraph 23);
the stack of layers further comprises a second conductive layer comprising conductive traces disposed in the insulation layer (the lower most metal layer 124 and its associated traces annotated as second in Fig. 2 above) (Fig. 2 and paragraph 45-47);
a first conductive trace of the second conductive layer is stacked with and runs parallel to a first conductive trace of the first conductive layer (the trace to the far left in the layer annotated as first containing contact pads 152 and the trace to the far left in the lower most metal layer 124 annotated as second are shown stacked and parallel to one another in Fig. 5A); and
a second conductive trace (a trace in the layer annotated as first next to the first trace under a capacitor 138) of the second conductive layer is stacked with and runs parallel to a second conductive trace (a trace in the lower most metal layer 124 next to the first trace under the capacitor 138) of the first conductive layer (the traces under the capacitor 138 are shown stacked and parallel to one another in annotated Fig. 2 above) (Fig. 2 and paragraph 22).
In regard to claim 7, Kamgaing teaches wherein:
the stack of layers further comprises a third conductive layer comprising conductive traces disposed in the insulation layer (the metal layer 124 and its traces annotated as third in annotated Fig. 2);
a first conductive trace (a trace to the far left in the metal layer 124 annotated as third in annotated Fig. 2) of the third conductive layer is stacked with the first conductive trace of the first conductive layer and the first conductive trace of the second conductive layer (the traces to the far left in the layers annotated as first, second and third are shown stacked and running parallel to one another in annotated Fig. 2 above); and a second conductive trace of the third conductive layer (top electrode of capacitor 138) is stacked with the second conductive trace of the first conductive layer and the second conductive trace of the second conductive layer (the traces in the layers annotated as first, second and third associated connected to the capacitor 138 next to the first traces are shown stacked and running parallel to one another in annotated Fig. 2 above).
In regard to claim 8, Kamgaing teaches wherein:
the conductive layer is a first conductive layer (the layer annotated as first contains contact pads 152 on backside 125 of substrate 120) (Fig. 2 and paragraph 23);
the stack of layers further comprises a second conductive layer comprising conductive traces disposed in the insulation layer (the lower most metal layer 124 and its associated traces annotated as second in Fig. 2 above);
first and second conductive traces of the first conductive layer (the layer annotated as first contact pads 152 that are not under capacitor 138) are configured to transmit signals (while the contact pads 152 transmit signals, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987));
a shield conductive trace (the contact pad 152 of the layer annotated as first under a capacitor 138) of the first conductive layer is disposed between the first and second conductive traces of the first conductive layer (the positioning of the contact pads 152 is shown in annotated Fig. 2 above); and
a shield conductive trace of the second conductive layer (a trace the layer annotated as first in a capacitor 138) is stacked with the shield conductive trace of the first conductive layer (the traces of the layer annotated as first and the metal layer 124 annotated as second are shown stacked in annotated Fig. 2 above).
In regard to claim 9, Kamgaing teaches wherein:
a third conductive layer (the metal layer 124 and its traces annotated as third in annotated Fig. 2);
and a shield conductive trace (a top electrode of capacitor 138) of the third conductive layer is stacked with the shield conductive trace of the first conductive layer and the shield conductive trace of the second conductive layer (the elements mapped as the shield conductive trace of the first, second, and third layer are shown stacked in annotated Fig. 2).
In regard to claim 12, Kamgaing teaches wherein the ceramic-based substrate is a high-temperature, co-fired ceramic substrate (package substrate 108 may be a high temperature co-fired ceramic substrate) (paragraph 26).
In regard to claim 13, wherein the stack of layers further comprises a bottom conductive plane (the plane containing contacts 162) disposed between the insulation layer and the ceramic-based substrate (as shown in Fig. 2 plane containing the contacts 162 is between the dielectric layers 126 and the package substrate 108 in Fig. 2) (Fig. 2 and paragraph 24).
Claims 14 and 16 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Shao et al. (US 2025/0044532 A1; hereinafter “Shao”).
In regard to claim 14, Shao teaches a waveguide device (a photonic package 200) (Fig. 10 and paragraph 33), comprising:
a ceramic-based substrate (substrate 214 of the interconnect substrate 210 may comprise a ceramic substrate) (Fig. 10 and paragraph 34); and
a stack of layers disposed on the ceramic-based substrate (the layers formed above the substrate 214 as shown in Fig. 10, and Fig. 11), the stack of layers comprising:
a first layer comprising a first dielectric material (a dielectric layer 108) (Fig. 10 and paragraph 22);
a second layer (waveguides 104) disposed in the first layer and comprising a second dielectric material different from the first dielectric material and having a refractive index greater than a refractive index of the first dielectric material (the refractive index of the material of the waveguides 104 is higher than the refractive index of the material of the dielectric layer 108) (paragraph 22); and
a conductive layer comprising conductive traces (redistribution structure 120) (Fig. 10 and paragraph 25); and
electronic elements electrically (electronic dies 122) connected to the conductive layer, wherein the conductive layer is configured to route electrical signals to the electronic elements (while the redistribution structure 120 may connect the vias 112, the contacts 113, and/or overlying devices such as electronic dies 122 to send signals (paragraph 25), it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987)).
In regard to claim 16, Shao teaches the waveguide device further comprising a coupling interface configured to propagate light in and/or out of the waveguide stack (waveguide structure 300 is a structure that provides optical coupling between waveguides (e.g., waveguides 104 of an optical engine 100) and an external optical fiber) (Fig. 19 and paragraph 40).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Kwon et al. (US 2016/0064328 A1; hereinafter “Kwon”) and Lin et al. (US 2017/0005073 A1; hereinafter “Lin”)
In regard to claim 2, Kamgaing doesn’t explicitly wherein: the insulation layer is a silicon dioxide layer; and the conductive layer is an aluminum layer having a thickness of about 5 microns to about 10 microns.
Kwon teaches an integrated circuit device (an electronic device 100) (Fig. 1 and paragraph 20), wherein an insulation layer (a dielectric 108) is a silicon dioxide layer (the dielectric 108 may be silicon dioxide) (Fig. 1 and paragraph 22).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Kwon to have the insulation layer be a silicon dioxide layer since silicon dioxide is a well-known dielectric oxide and it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Lin teaches an integrated circuit device (a semiconductor device as shown in Fig. 8), wherein a conductive layer (a first RDL 801) is an aluminum layer having a thickness of about 5 microns to about 10 microns (the first RDL 801 may comprise two conductive layers formed of metals such as aluminum, copper, tungsten, titanium, and combinations and may be between about 2 μm and about 30 μm, such as about 5 μm) (Fig. 8 and paragraph 38).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Lin to have since this allows for multiple connections to be made throughout the device as taught by Kamgaing (paragraph 67).
In regard to claim 3, Kamgaing teaches wherein: the conductive layer is a first conductive layer (the layer annotated as first contains contact pads 152 on backside 125 of substrate 120) (Fig. 2 and paragraph 23);
the stack of layers further comprises a second conductive layer (the lower most metal layer 124 annotated as second in Fig. 2 above) comprising conductive traces (traces of the metal layer are shown in Fig. 2) disposed in the insulation layer (the traces of metal layers 124 are shown in the dielectric layer in Fig. 2) (annotated Fig. 2 and paragraph 23).
However, Kamgaing doesn’t explicitly teach the second conductive layer is an aluminum layer having a thickness of about 5 microns to about 10 microns.
Lin teaches an integrated circuit device (a semiconductor device as shown in Fig. 8), wherein a conductive layer (a first RDL 801) is an aluminum layer having a thickness of about 5 microns to about 10 microns (the first RDL 801 may comprise two conductive layers formed of metals such as aluminum, copper, tungsten, titanium, and combinations and may be between about 2 μm and about 30 μm, such as about 5 μm) (Fig. 8 and paragraph 38).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Liu et al. (US 2023/0141681 A1).
In regard to claim 4, Kamgaing doesn’t explicitly teach wherein the electronic elements comprises an array of photodetector elements configured to receive illumination and to generate information signals according to an image associated with the received illumination, and wherein the conductive traces are configured to transmit the information signals.
Liu teaches an integrated circuit device (an image sensor 2100) (Fig. 22 and paragraph 43), wherein electronic elements comprises an array of photodetector elements (four photodiodes 2004a-2004d) configured to receive illumination and to generate information signals according to an image associated with the received illumination (Fig. 21, Fig. 22 and paragraph 41), and wherein conductive traces (a plurality of wires 2126) are configured to transmit the information signals (the light then interacts with the first photodetector 2004a to be transformed into an electrical signal, which is processed by circuitry of the photodetectors an image device interconnect structure 2124 which contains the polarity of wires 2126) (Fig. 22 and paragraphs 48 and 50).
It would’ve been obvious one of ordinary skill in the art to combine the teachings of Kamgaing with the teachings of Liu to have the electronic elements comprises an array of photodetector elements configured to receive illumination and to generate information signals according to an image associated with the received illumination, and have the conductive traces configured to transmit the information signals since this layout is well known to allow the device to act as a camera or image sensor as taught by Liu (paragraphs 2-3 and 43).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Wei et al. (US 2004/0222506 A1; hereinafter “Wei”)
In regard to claim 6, Kamgaing doesn’t explicitly teach wherein a separation between the first conductive trace of the first conductive layer and the first conductive trace of the second conductive layer is about 10 microns to about 15 microns.
Wei teaches an integrated circuit device (an integrated circuit die 102) (Fig. 6 and paragraph 33), wherein a separation between a first conductive trace of a first conductive layer and a first conductive trace of the second conductive layer is about 10 microns to about 15 microns (the vertical spacing between re-distribution layers RM1, RM2, and RM3 is preferably approximately 10 microns) (Fig. 6 and paragraph 34).
It would’ve been obvious to one skilled in the art to combine the teachings of Kamgaing with the teachings of Wei to have a separation between the first conductive trace of the first conductive layer and the first conductive trace of the second conductive layer be about 10 microns to about 15 microns since this allows a the device to be provided with good electromagnetic shielding as taught by Wei (paragraphs 10-11 and 31).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing as applied to claim 1 above, in view of Yeong et al. (US 2022/0359550 A1; hereinafter “Yeong”)
In regard to claim 10, Kamgaing doesn’t explicitly teach wherein one or more of the electronic elements comprises a tunable ferroelectric capacitor.
Yeong teaches an integrated circuit device (a semiconductor device 100) (Fig. 1 and paragraph 21), wherein one or more of electronic elements comprises a tunable ferroelectric capacitor (a ferroelectric tunable capacitor is fabricated at a same level in an RF circuit region of the chip) (Fig. 1 and paragraph 20)
It would’ve been obvious to combine the teachings of Kamgaing with the teachings of Yeong to have one or more of the electronic elements comprises a tunable ferroelectric capacitor since this enables the device to do high-frequency applications as taught by Yeong (paragraph 24).
In regard to claim 11, Kamgaing doesn’t explicitly teach wherein one or more of the electronic elements comprises an integrated ferrite configured to filter noise comprising a frequency component of about 5 GHz or greater.
Yeong teaches wherein one or more of the electronic elements comprises an integrated ferrite (ferroelectric structure 122A ) configured to filter noise comprising a frequency component of about 5 GHz or greater (Fig. 1 and paragraph 24). While Yeong does not explicitly teach the ferroelectric structure 122A is configured to filter noise comprising a frequency component of about 5 GHz or greater, the examiner notes intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable to performing the intended use, and then it meets the claim. Therefore, since the ferroelectric structure 122A is able to be used in an RF filter the claim limitation is met.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Shao as applied to claim 14 above, in view of Padney et al. (US 2023/0273369 A1; hereinafter “Padney”).
In regard to claim 15, Shao doesn’t explicitly teach wherein the first dielectric material comprises silicon dioxide and the second dielectric material comprises silicon nitride.
Padney teaches a wave guide device (a photonics structure) (Fig. 7 and paragraph 9), wherein a first dielectric material comprises silicon dioxide and a second dielectric material comprises silicon nitride (a dielectric layer 24 may be comprised of a dielectric material such as silicon dioxide and waveguide core 22 may be comprised of a dielectric material such as silicon nitride) (Fig. 7 and paragraphs 12 and 14).
It would’ve been obvious to one skilled in the art to combine the teachings of Shao and Padney to have the first dielectric material comprise silicon dioxide and the second dielectric material comprise silicon nitride since these are common materials for a waveguide device and it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Shao as applied to claim 16 above, in view of Sahin et al. (US 2022/0268994 A1; hereinafter “Sahin”).
In regard to claim 17, Shao doesn’t explicitly teach wherein a shape of the coupling interface is a v- groove configured to connect with an optical fiber.
Sahin teaches a waveguide device (a photonics integrated circuit (PIC) 100) (Fig. 3 and paragraph 27), wherein a shape of the coupling interface is a v- groove configured to connect with an optical fiber (FIG. 5 shows optically coupling fiber optic cable 156 (FIG. 4) in V-groove 146 to Si waveguide edge coupler 150) (Fig. 5 and paragraph 45).
It would’ve been obvious to one skilled in the art to combine the teachings of Shao with the teachings of Sahin to have a shape of the coupling interface be a v- groove configured to connect with an optical fiber since this shape is common as taught by Sahin (paragraph 34), and it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights