DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 04/03/2026, in which claims 1, 6, 12 were amended, claims 11, 17-20 were withdrawn, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-7, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Fountain, Jr. et al. (US Pub. 20210242152) and Lee et al. (US Pub. 20220013502).
Regarding claim 1, Fountain, Jr. et al. discloses in Fig. 2, Fig. 3B, paragraph [0030]-[0038], [0040] a bonding semiconductor device [1] comprising:
a first chip [10] including a first bonding pad; and
a second chip [12] including a second bonding pad,
wherein the bonding semiconductor device [1] includes a chip region and a partition region [region including voids 32 and 33],
the chip region includes a bonding pad [22] comprising the first bonding pad of the first chip bonded to the second bonding pad of the second chip, and
the partition region [region including voids 32 and 33] includes a separation pattern portion [29 and 28] in which a first base layer [29] of a first pattern portion of the first chip [10] and a second base layer [29] of a second pattern portion of the second chip [12] are entirely separated from each other and define an inner space [28].
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Fountain, Jr. et al. discloses the partition region [region including voids 32 and 33] includes regions formed on both side of the chip region. Fountain, Jr. et al. discloses the partition region including dummy/inactive pads.
Fountain, Jr. et al. fails to explicitly disclose
the partition region surrounding the chip region.
Lee et al. discloses in Fig. 1, Fig. 2, paragraph [0028]-[0044]
the partition region [dummy pad region DPR] surrounding the chip region [MPR1].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Fountain, Jr. et al. to include the partition region surrounding the chip region. The ordinary artisan would have been motivated to modify Fountain, Jr. et al. in the above manner for the purpose of providing suitable layout of the partition region to prevent local erosion of an insulating layer from occurring [paragraph [0004], [0028], [0043] of Lee et al.].
Alternatively
Regarding claim 1, Lee et al. discloses in Figs. 1-4, paragraph [0025]-[0059] a bonding semiconductor device [100] comprising:
a first chip [10C] including a first bonding pad; and
a second chip [20C] including a second bonding pad,
wherein the bonding semiconductor device [100] includes a chip region [MPR1] and a partition region [DPR], the partition region [dummy pad region DPR] surrounding the chip region [MPR1].
the chip region [MPR1] includes a bonding pad [16 and 26] comprising the first bonding pad [16] of the first chip [10C] bonded to the second bonding pad [26] of the second chip [20C].
Lee et al. fails to disclose
the partition region includes a separation pattern portion in which a first base layer of a first pattern portion of the first chip and a second base layer of a second pattern portion of the second chip are entirely separated from each other and define an inner space.
However, Lee et al. discloses the partition region [DPR] includes a dummy pattern portion [DP] that is not connected to transfer any signals to or from any integrated circuits.
Fountain, Jr. et al. discloses in Fig. 3B paragraph [0030]-[0038], [0040]
the partition region [region including voids 32 and 33] includes a separation pattern portion [29 and 28] in which a first base layer [29] of a first pattern portion of the first chip [10] and a second base layer [29] of a second pattern portion of the second chip [12] are entirely separated from each other and define an inner space [28].
Fountain, Jr. et al. further discloses in paragraph [0034] the separation pattern portion [29 and 28] is a dummy/inactive pad that is not connected to transfer any signals to or from any integrated circuits.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fountain, Jr. et al. into the method of Lee et al. to include the partition region includes a separation pattern portion in which a first base layer of a first pattern portion of the first chip and a second base layer of a second pattern portion of the second chip are entirely separated from each other and define an inner space. The ordinary artisan would have been motivated to modify Lee et al. in the above manner for the purpose of preventing interconnections for these dummy conductive contact pads between the first and second chip and disable functionalities of the bonded pad structure at dummy pad region [paragraph [0031], [0034] of Fountain, Jr. et al.].
Regarding claims 2, 6-7, Fountain, Jr. et al. discloses in Fig. 2, Fig. 3B, paragraph [0025], [0030]-[0038], [0040], paragraph [0044]
wherein the first chip [10] includes a first insulation layer [16],
the second chip [12] includes a second insulation layer [16] bonded to the first insulation layer [16], and a bonding surface [18] between the first insulation layer [16] and the second insulation layer [16] and the inner space [28] between the first base layer [29] and the second base layer [29] are between the first chip [10] and the second chip [12] in the partition region;
wherein the first chip [10] further comprises a first insulation layer [16] defining a first trench portion and a second trench, wherein the first bonding pad [22] is in the first trench, and the first pattern portion [29] is in the second trench such that the first base layer [29] does not completely cover a side surface of the second trench portion;
wherein the first pattern portion and the second pattern portion form a disconnection structure such that the first pattern portion and the second pattern portion are not connected with each other.
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Regarding claim 10, Fountain, Jr. et al. discloses in paragraph [0046]
wherein the separation pattern portion is included in at least one of a key pattern or a dummy pattern [pads 22 which do not connect to any active circuitry].
Lee et al. discloses the partition region [DPR] includes a dummy pattern portion [DP].
In addition, “a key pattern or a dummy pattern” directs to intended used and manner of operation of the separation pattern portion. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). MPEP 2114 (II). In addition, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In this case, Fountain, Jr. et al. disclosed all structural limitation of the separation pattern portion as claimed. Thus, the separation pattern portion disclosed by Fountain, Jr. et al. would be able to perform the intended function as a key pattern or a dummy pattern.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Fountain, Jr. et al. (US Pub. 20210242152) and Lee et al. (US Pub. 20220013502) as applied to claim 1 above and further in view of Huang (US Pub. 20220077091).
Regarding claim 3, Fountain, Jr. et al. and Lee et al. fails to disclose
wherein, in cross-section, a width of the separation pattern portion is greater than a width of the bonding pad.
One of ordinary skill in the art would have recognized the finite number of predictable solutions for a width of the separation pattern portion with respect to a width of the bonding pad: a width of the separation pattern portion is greater than, less than or equal to a width of the bonding pad. Absent unexpected results, it would have been obvious to try a width of the separation pattern portion is greater than a width of the bonding pad.
For further support, Huang discloses in Fig. 2I
wherein, in cross-section, a width of the separation pattern portion is greater than or less than a width of the bonding pad.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Huang into the method of Fountain, Jr. et al. and Lee et al. to include wherein, in cross-section, a width of the separation pattern portion is greater than or less than a width of the bonding pad. The ordinary artisan would have been motivated to modify Fountain, Jr. et al. and Lee et al. in the above manner for the purpose of providing suitable width of the separation pattern portion.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Fountain, Jr. et al. (US Pub. 20210242152) and Lee et al. (US Pub. 20220013502) as applied to claim 1 above and further in view of Haba et al. (US Pub. 20190115323).
Regarding claims 4-5, Fountain, Jr. et al. and Lee et al. fails to disclose
wherein, in cross- section, a thickness of the inner space is smaller than a sum of a thickness of the first base layer and a thickness of the second base layer;
wherein, in cross- section, a width of the separation pattern portion is greater than a thickness of the inner space.
Haba et al. discloses in Fig. 7, paragraph [0052]
wherein, in cross- section, a thickness of the inner space [space that has the dielectric medium 618] is smaller than a sum of a thickness of the first base layer [614] and a thickness of the second base layer [616];
wherein, in cross- section, a width of the separation pattern portion [702] is greater than a thickness of the inner space [space that has the dielectric medium 618].
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Haba et al. further suggests in Fig. 6 and Fig. 8 and paragraph [0058] that a thickness of the inner space can be adjusted to obtain desired capacitance of the separation pattern portion.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Haba et al. into the method of Fountain, Jr. et al. and Lee et al. to include wherein, in cross- section, a thickness of the inner space is smaller than a sum of a thickness of the first base layer and a thickness of the second base layer; wherein, in cross- section, a width of the separation pattern portion is greater than a thickness of the inner space. The ordinary artisan would have been motivated to modify Fountain, Jr. et al. and Lee et al. in the above manner for the purpose of providing suitable thickness of the inner space to obtain desired capacitance of the separation pattern portion [paragraph [0058] of Haba et al.].
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fountain, Jr. et al. (US Pub. 20210242152) and Lee et al. (US Pub. 20220013502) as applied to claim 1 above and further in view of Aoki et al. (US Pub. 20120068355).
Regarding claims 8-9, Fountain, Jr. et al. and Lee et al. fails to disclose in Fig. 3B
wherein the first base layer is on a first barrier layer having a thinner thickness than the first base layer,
the second base layer is on a second barrier layer having a thinner thickness than the second base layer, and
the first barrier layer and the second barrier layer are directly connected to each other at a bonding surface between the first chip and the second chip;
wherein a thickness of the inner space is larger than a thickness of at least one of the first barrier layer or second barrier layer.
Aoki et al. discloses in Fig. 10, paragraph [0055]
wherein the first base layer [22 bottom] is on a first barrier layer [15 bottom] having a thinner thickness than the first base layer [22 bottom],
the second base layer [22 top] is on a second barrier layer [15 top] having a thinner thickness than the second base layer [22 top], and
the first barrier layer [15 bottom] and the second barrier layer [15 top] are directly connected to each other at a bonding surface between the first chip and the second chip;
wherein a thickness of the inner space [23] is larger than a thickness of at least one of the first barrier layer or second barrier layer [15].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Aoki et al. into the method of Fountain, Jr. et al. and Lee et al. to include wherein the first base layer is on a first barrier layer having a thinner thickness than the first base layer and the second base layer is on a second barrier layer having a thinner thickness than the second base layer, the first barrier layer and the second barrier layer are directly connected to each other at a bonding surface between the first chip and the second chip; wherein a thickness of the inner space is larger than a thickness of at least one of the first barrier layer or second barrier layer. The ordinary artisan would have been motivated to modify Fountain, Jr. et al. and Lee et al. in the above manner for the purpose of preventing the conductive material in the base layer from diffusing into the insulation layer [paragraph [0055] of Aoki et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. (US Pub. 20200075533) in view of Lee et al. (US Pub. 20220013502) and Aoki et al. (US Pub. 20120068355)
Regarding claim 12, Gao et al. discloses in Fig. 11, paragraph [0042], [0072]-[0073] a chip for a bonding semiconductor device including a chip region and an external region, the chip comprising:
an insulation layer and defining a first trench portion and a second trench portion, the first trench portion in the chip region and having a first size and the second trench portion in the external region and having a second size larger than the first size;
a bonding pad [1106 or 1104] in the first trench portion; and
a pattern portion [1108 or 1112] in the second trench portion, the pattern portion [1108 or 1112] including a base layer,
wherein an uppermost surface of the base layer is lower than an upper surface of the insulation layer.
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Gao et al. fails to disclose the chip comprising:
a substrate;
the insulation layer on the substrate.
Aoki et al. discloses in Fig. 9, Fig. 10 the chip comprising:
a substrate [10];
the insulation layer [11] on the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Aoki et al. into the method of Gao et al. to include the chip comprising: a substrate; the insulation layer on the substrate. The ordinary artisan would have been motivated to modify Gao et al. in the above manner for the purpose of providing a semiconductor device [paragraph [0003]-[0006], [0020]-[0021]].
Gao et al. fails to explicitly disclose
the external region surrounding the chip region.
Lee et al. discloses in Fig. 1, Fig. 2, paragraph [0028]-[0044]
the external region [dummy pad region DPR] surrounding the chip region [MPR1].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Gao et al. to include the external region surrounding the chip region. The ordinary artisan would have been motivated to modify Gao et al. in the above manner for the purpose of providing suitable layout of the external region to prevent local erosion of an insulating layer from occurring [paragraph [0004], [0028], [0043] of Lee et al.].
Regarding claims 13-15, Gao et al. discloses in Fig. 11
wherein the uppermost surface of the base layer is lower than an upper surface of the bonding pad;
wherein an upper surface of the bonding pad [1104] is lower than or at a same plane as the upper surface of the insulation layer;
wherein the pattern portion [1112] does not contact an upper side surface of the second trench portion such that the pattern portion [1112] is spaced apart from the upper surface of the insulation layer.
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Regarding claim 16, Gao et al. fails to disclose
wherein the pattern portion includes a barrier layer between the base layer and the insulation layer, the barrier layer having a thickness thinner than that of the base layer, and the barrier layer is on a bottom surface and side surfaces of the second trench portion and extends up to the upper surface of the insulation layer.
Aoki et al. discloses in Fig. 9, paragraph [0055]
wherein the pattern portion includes a barrier layer [15] between the base layer [22] and the insulation layer [11], the barrier layer [15] having a thickness thinner than that of the base layer [22], and the barrier layer [15] is on a bottom surface and side surfaces of the second trench portion and extends up to the upper surface of the insulation layer [11].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Aoki et al. into the method of Gao et al. to include wherein the pattern portion includes a barrier layer between the base layer and the insulation layer, the barrier layer having a thickness thinner than that of the base layer, and the barrier layer is on a bottom surface and side surfaces of the second trench portion and extends up to the upper surface of the insulation layer. The ordinary artisan would have been motivated to modify Gao et al. in the above manner for the purpose of preventing the conductive material in the base layer from diffusing into the insulation layer [paragraph [0055] of Aoki et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to claims 1-10, 12-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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