DETAILED ACTION
This action is responsive to the communication filed 29 June 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species I embodiment in the reply filed on 8 January 2026 is acknowledged.
Accordingly, claims 9-15, which are directed to a nonelected species, are withdrawn from further consideration.
Response to Arguments
Applicant's arguments filed 29 June 2026 have been fully considered but they are not persuasive.
Applicant states:
Regarding the above-claimed features, the Office Action relies on the doctrine of inherency (MPEP § 2112.01(I)). Specifically, the Examiner urges that Noh in view of Park discloses a structure identical to the claimed thin film transistor, and thus necessarily possesses the properties of forming first and second parasitic capacitances that are different from each other.
Applicant respectfully disagrees. The structure of Noh is not identical or substantially identical to the claimed invention, and the claimed "different parasitic capacitances" are not inherently formed in the structure of Noh.
Applicant Arguments/Remarks Made in an Amendment (filed 29 June 2026) at 3. The Examiner respectfully notes that the Non-Final Rejection mailed 2 April 2026 clearly establishes that U.S. Patent Publication No. 2021/0005638 (published Jan. 7, 2021) (hereinafter “Noh”) in view of U.S. Patent Publication No. 2022/0013549 (filed July 2, 2021) (hereinafter “Park”) discloses each and every claimed feature of independent claim 1 and sets forth those portions of the MPEP and relevant case law upon which the prima facie case of obviousness is made. Because Applicant did not amend claim 1 in the response filed 29 June 2026, an identical rejection of independent claim 1 appears in the rejection of claim 1, below.
Applicant further states:
The second gate electrode (330) does not vertically overlap the lower flat portions (i.e., the remaining portions adjacent to the source/drain electrodes 350 and 360) of the second semiconductor pattern (310). Because there is no vertical overlap between the gate electrode (330) and the remaining lower portions of the semiconductor pattern (310), a vertical distance—and consequently, a parasitic capacitance—between these non-overlapping components cannot be structurally defined or formed.
…
In contrast, the claimed invention provides a structure where the vertical distances from the gate electrode to the first portion and the second portion of the oxide semiconductor pattern are intentionally different from each other. This physical difference in distance is what creates the "first parasitic capacitance and the second parasitic capacitance [that] are different from each other." This intentional design secures a unique effect of improving low-gradation expression (e.g., s-factor adjustment) by driving parallel sub-transistors with different threshold voltages.
Applicant Arguments/Remarks Made in an Amendment (filed 29 June 2026) at 4. At the outset, the Examiner respectfully notes that Applicant’s arguments are directed to the rejection of independent claim 1. See id. at 3-5. Concerning parasitic capacitance, independent claim 1 uses broad and encompassing language and recites, in relevant part:
wherein the first oxide semiconductor pattern comprises a first portion configured to form a first parasitic capacitance, together with the first gate electrode, and a second portion configured to form a second parasitic capacitance, together with the first gate electrode, and wherein the first parasitic capacitance and the second parasitic capacitance are different from each other.
Notably missing from independent claim 1 is any specific language claiming a protrusion/protruding portion, wherein the gate electrode vertically overlaps the semiconductor pattern, wherein the vertical distances from the gate electrode to the first portion and the second portion of the oxide semiconductor pattern are intentionally different, or wherein the parasitic capacitance is configured to be formed therefrom. Applicant’s arguments regarding claim 1 are almost entirely based on features that Applicant fails to claim. Accordingly, responsive to Applicant's argument that the references fail to show certain features of the invention, the Examiner respectfully notes that the features upon which Applicant relies (e.g., a protrusion/protruding portion, wherein the gate electrode vertically overlaps the semiconductor pattern, wherein the vertical distances from the gate electrode to the first portion and the second portion of the oxide semiconductor pattern are intentionally different, or wherein the parasitic capacitance is configured to be formed therefrom) are not recited in the rejected claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant further states:
First, referring to FIG. 14 of Noh, the Office Action points to the corrugated shape of the second semiconductor pattern (310) as having a protrusion.
…
Second, even if one were to look at other cross-sections of Noh, such as FIG. 13 where the second gate electrode (330) vertically overlaps the side portions of the second semiconductor pattern (310), Noh strictly employs a conformal coating structure. Specifically, the gate insulating film (114) and the gate electrode (330) are conformally deposited along the stepped profile of the underlying semiconductor pattern (310). Because the conformally deposited gate insulating film (114) has a uniform thickness, the vertical distance (i.e., normal distance) between the semiconductor pattern (310) and the gate electrode (330) remains constant across all overlapping regions.
Applicant Arguments/Remarks Made in an Amendment (filed 29 June 2026) at 4. The Examiner respectfully asserts that even assuming, arguendo, that independent claim 1 was drawn to the configuration urged by Applicant (which it is not, discussed above), Noh clearly discloses in FIG. 13, annotated below, wherein parasitic capacitances are different between different portions of the semiconductor layer and the first gate electrode.
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Annotated FIG. 13
Accordingly, none of Applicant’s arguments are persuasive.
Claim Rejections - 35 USC § 112
The rejection of claim 8 under § 112(b) is withdrawn, responsive to Applicant’s amendment of the claim.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-8 and 16-19 is/are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Publication No. 2021/0005638 (published Jan. 7, 2021) (hereinafter “Noh”) in view of U.S. Patent Publication No. 2022/0013549 (filed July 2, 2021) (hereinafter “Park”).
Regarding independent claim 1, Noh discloses: A thin film transistor array substrate comprising:
a substrate (FIG. 14, substrate 100, [0027]) comprising an active area (FIGS. 1/14, depicting, e.g., the area in which the pixel PA is disposed, [0027]) and a non-active area disposed around the active area (FIGS. 1/14, depicting, e.g., the area disposed around the area in which the pixel PA is disposed, [0027]);
a first thin film transistor disposed on the substrate (FIG. 14, thin film transistor 300, [0030]);
wherein the first thin film transistor comprises a first oxide semiconductor pattern disposed on the substrate (FIG. 14, semiconductor pattern 310, which may be an oxide semiconductor, disposed on the substrate 100, [0031]),
a first gate electrode (FIG. 14, second gate electrode 330, [0030]),
a first gate insulating layer interposed between the first oxide semiconductor pattern and the first gate electrode (FIG. 14, depicting, e.g., a gate insulating film 114, disposed between the semiconductor pattern 310 and the second gate electrode 330, [0030]),
a first source electrode (FIG. 14, source electrode 350, [0030]), and
a first drain electrode (FIG. 14, drain electrode 360, [0030]);
wherein the first oxide semiconductor pattern comprises a first portion and a second portion (FIGS. 1/13/14, e.g., a left portion and a right portion of the semiconductor pattern 310 which may be a first portion and a second portion).
Noh does not specifically disclose a first light shielding pattern disposed between the substrate and the first thin film transistor, wherein the first light shielding pattern is electrically connected to one of the first source electrode and the first drain electrode and is disposed under the first oxide semiconductor pattern.
In the same field of endeavor, Park discloses a thin-film transistor including a first light shielding pattern (FIG. 4, light blocking layer BML, [0065]) disposed between the substrate and the first thin film transistor (FIG. 4, depicting wherein the light blocking layer is disposed between the substrate SUB and the transistor T1), wherein the first light shielding pattern is electrically connected to one of the first source electrode and the first drain electrode (FIG. 4, depicting wherein the source electrode S1 is electrically connected to the light blocking layer BML). Regarding the light blocking layer BML, in [0066], Park states: “The light blocking layer BML may prevent or reduce instances of light, which is incident from the substrate SUB, entering a first channel region CP1 of the first active layer ACT1. Therefore, it may be possible to prevent or reduce instances of a leakage current due to light flowing in the first channel region CP1 of the first active layer ACT1.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Noh by adding the light blocking layer of Park in order to prevent light from entering, and thereby preventing leakage current. See Park [0066].
Moreover, the addition of the light blocking layer of Park would result in a configuration wherein the first light shielding pattern is disposed under the first oxide semiconductor pattern (Noh FIG. 14; Park FIG. 4; depicting wherein the light blocking layer BML would be disposed under the semiconductor pattern 310 of Noh just as the light blocking layer BML is disposed under the active layer ACT1 of Park).
Applicant further claims “wherein the first oxide semiconductor pattern comprises a first portion configured to form a first parasitic capacitance, together with the first gate electrode, and a second portion configured to form a second parasitic capacitance, together with the first gate electrode, and wherein the first parasitic capacitance and the second parasitic capacitance are different from each other.”
When the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. MPEP § 2112.01(I). “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established.” Id. (citing In re Best, 562 F.2d 1252, 1255, 195 U.S.P.Q. 430, 433 (C.C.P.A. 1977)). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” Id. (quoting In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990)). “Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product.” Id. (citing In re Best, 562 F.2d at 1255).
In the instant case, Noh in view of Park discloses a thin film transistor substrate structure that is identical to the thin film transistor substrate structure claimed in Applicant’s claim 1, and thus necessarily possesses the properties of the thin film transistor substrate structure claimed in Applicant’s claim 1, including wherein the first oxide semiconductor pattern comprises a first portion configured to form a first parasitic capacitance, together with the first gate electrode, and a second portion configured to form a second parasitic capacitance, together with the first gate electrode, and wherein the first parasitic capacitance and the second parasitic capacitance are different from each other. Compare, e.g., FIG. 14 and [0027]-[0031] of Noh and FIG. 4 and [0065]-[0066] of Park with FIGS. 5A-E and [0042]-[0212] of the instant application.
Accordingly, Noh in view of Park discloses a display device that necessarily possesses the properties of the display device structure disclosed in Applicant’s claim 1, and thus renders obvious claim 1.
Regarding claim 2, Noh in view of Park further discloses wherein the first portion of the first oxide semiconductor pattern comprises a protrusion protruding toward the first gate electrode (FIG. 14, depicting wherein the first portion of the second semiconductor pattern 310 includes a protrusion protruding toward the second gate electrode 330).
Regarding claim 3, Noh in view of Park further discloses wherein the first oxide semiconductor pattern (FIG. 14, second semiconductor pattern 310) comprises: a first source region connected to the first source electrode (FIG. 14, depicting the portion of the second semiconductor pattern 310 under the source electrode 350), a first drain region connected to the first drain electrode (FIG. 14, depicting the portion of the second semiconductor pattern 310 under the drain electrode 360), and a first channel region disposed between the first source region and the first drain region (FIG. 14, depicting a channel region between the portions of the second semiconductor pattern 310 under the source and drain electrodes 350/360, [0032]), wherein a length of the first protrusion is equal to or greater than a length of the first channel region (FIG. 14, depicting wherein a length of the protrusion is greater than a length of the channel region).
Regarding claim 4, Noh in view of Park further discloses wherein the first protrusion of the first oxide semiconductor pattern corresponds to the first channel region (FIG. 14, depicting wherein the protrusion corresponds to the channel region between the portions of the second semiconductor pattern 310 under the source and drain electrodes 350/360).
Regarding claim 5, Noh in view of Park further discloses wherein the first protrusion is disposed in a number of at least one in a width direction of the first channel region (FIG. 14, depicting one protrusion).
Regarding claim 6, Applicant further claims “wherein the first parasitic capacitance is greater than the second parasitic capacitance.”
When the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. MPEP § 2112.01(I). “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established.” Id. (citing In re Best, 562 F.2d 1252, 1255, 195 U.S.P.Q. 430, 433 (C.C.P.A. 1977)). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” Id. (quoting In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990)). “Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product.” Id. (citing In re Best, 562 F.2d at 1255).
In the instant case, Noh in view of Park discloses a thin film transistor substrate structure that is identical to the thin film transistor substrate structure claimed in Applicant’s claim 6, and thus necessarily possesses the properties of the thin film transistor substrate structure claimed in Applicant’s claim 6, including wherein the first parasitic capacitance is greater than the second parasitic capacitance. Compare, e.g., FIG. 14 and [0027]-[0031] of Noh and FIG. 4 and [0065]-[0066] of Park with FIGS. 5A-E and [0042]-[0212] of the instant application.
Accordingly, Noh in view of Park discloses a display device that necessarily possesses the properties of the display device structure disclosed in Applicant’s claim 6, and thus renders obvious claim 6.
Regarding claim 7, Noh in view of Park further discloses a buffer layer between the first oxide semiconductor pattern and the first light shielding pattern (FIG. 14, buffer insulating film 114, [0080]), wherein the buffer layer comprises a second protrusion protruding toward the first gate electrode (FIG. 14, depicting wherein the buffer insulating film 114 includes a protrusion protruding toward the second gate electrode 330), and wherein the first protrusion of the first oxide semiconductor pattern is deposited along a curvature of an upper surface of the buffer layer (FIG. 14, depicting wherein the protrusion of the semiconductor pattern 310 is deposited along a curvature of the upper surface of the buffer insulating film 114).
Regarding claim 8, Noh in view of Park further discloses wherein when a vertical distance from the first protrusion to the first gate electrode is a first vertical distance (D1), and a vertical distance from the first oxide semiconductor pattern, except for the first protrusion, to the first gate electrode is a second vertical distance (D2), the second vertical distance (D2) is greater than the first vertical distance (D1) (FIG. 14, depicting wherein the portion of the semiconductor pattern 310 forming the protrusion is a first vertical distance from the gate electrode 330, wherein the portion of the semiconductor pattern 310 not forming the protrusion is a second vertical distance from the gate electrode 330, and further wherein the second vertical distance is greater than the first vertical distance).
Regarding claim 16, Noh in view of Park further discloses wherein the first thin film transistor is a driving thin film transistor configured to drive a pixel disposed in the active area (FIG. 14; [0030]: “Each of the driving circuits may include at least two thin- film transistors 200 and 300. For example, each of the driving circuits may include a first thin-film transistor 200, a second thin-film transistor 300, and a storage capacitor 400. The first thin-film transistor 200 may turn on or off the second thin-film transistor 300 according to a gate signal. The storage capacitor 400 may maintain the signal applied to the second thin-film transistor 300 from the first thin-film transistor 200 for a predetermined period of time. The second thin-film transistor 300 may generate a driving current corresponding to the signal of the first thin-film transistor 200.”).
Regarding claim 17, Applicant further claims “wherein a parasitic capacitance formed between the first light shielding pattern and the first oxide semiconductor pattern is greater than a parasitic capacitance formed between the first gate electrode and the first oxide semiconductor pattern.”
When the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. MPEP § 2112.01(I). “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established.” Id. (citing In re Best, 562 F.2d 1252, 1255, 195 U.S.P.Q. 430, 433 (C.C.P.A. 1977)). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” Id. (quoting In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990)). “Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product.” Id. (citing In re Best, 562 F.2d at 1255).
In the instant case, Noh in view of Park discloses a thin film transistor substrate structure that is identical to the thin film transistor substrate structure claimed in Applicant’s claim 17, and thus necessarily possesses the properties of the thin film transistor substrate structure claimed in Applicant’s claim 17, including wherein a parasitic capacitance formed between the first light shielding pattern and the first oxide semiconductor pattern is greater than a parasitic capacitance formed between the first gate electrode and the first oxide semiconductor pattern. Compare, e.g., FIG. 14 and [0027]-[0031] of Noh and FIG. 4 and [0065]-[0066] of Park with FIGS. 5A-E and [0042]-[0212] of the instant application.
Accordingly, Noh in view of Park discloses a display device that necessarily possesses the properties of the display device structure disclosed in Applicant’s claim 17, and thus renders obvious claim 17.
Regarding claim 18, Noh in view of Park further discloses wherein the first thin film transistor comprises a first sub-first thin film transistor (FIGS. 1/13/14, depicting, e.g., a “first sub-first thin film transistor” corresponding to a left portion of the semiconductor pattern 310) and a second sub-first thin film transistor (FIGS. 1/13/14, depicting, e.g., a “first sub-first thin film transistor” corresponding to a right portion of the semiconductor pattern 310); the first sub-first thin film transistor comprises the first portion of the first oxide semiconductor pattern, the first gate electrode, the first source electrode, and the first drain electrode (FIGS. 1/13/14, a “first sub-first thin film transistor” corresponding to a left portion of the semiconductor pattern 310 comprises the left portion of the semiconductor pattern 310, the gate electrode 330, the source electrode 350, and the drain electrode 360); the second sub-first thin film transistor comprises the second portion of the first oxide semiconductor pattern, the first gate electrode, the first source electrode, and the first drain electrode (FIGS. 1/13/14, a “second sub-first thin film transistor” corresponding to a right portion of the semiconductor pattern 310 comprises the right portion of the semiconductor pattern 310, the gate electrode 330, the source electrode 350, and the drain electrode 360).
Applicant further claims “wherein a threshold voltage of the first sub-first thin film transistor is different from a threshold voltage of the second sub-first thin film transistor.”
When the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. MPEP § 2112.01(I). “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established.” Id. (citing In re Best, 562 F.2d 1252, 1255, 195 U.S.P.Q. 430, 433 (C.C.P.A. 1977)). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” Id. (quoting In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990)). “Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product.” Id. (citing In re Best, 562 F.2d at 1255).
In the instant case, Noh in view of Park discloses a thin film transistor substrate structure that is identical to the thin film transistor substrate structure claimed in Applicant’s claim 18, and thus necessarily possesses the properties of the thin film transistor substrate structure claimed in Applicant’s claim 18, including wherein a threshold voltage of the first sub-first thin film transistor is different from a threshold voltage of the second sub-first thin film transistor. Compare, e.g., FIG. 14 and [0027]-[0031] of Noh and FIG. 4 and [0065]-[0066] of Park with FIGS. 5A-E and [0042]-[0212] of the instant application.
Accordingly, Noh in view of Park discloses a display device that necessarily possesses the properties of the display device structure disclosed in Applicant’s claim 18, and thus renders obvious claim 18.
Regarding claim 19: Noh in view of Park further discloses a display device comprising: the thin film transistor array substrate according to claim 1 (FIGS. 1/14, depicting a display apparatus including the thin film transistor 300, [0016]); and a light emitting device part disposed on the substrate (FIG. 14, light emitting device 500, [0057]), the light emitting device part comprising a first electrode connected to the first drain electrode (FIG. 14, first electrode 510, [0059]: “The first electrode 510 may be electrically connected to the driving circuit of the corresponding pixel PA. For example, the lower protective film 120 and the over-coat layer 130 may include pixel contact holes partially exposing the second drain electrode 360 of the second thin-film transistor 300 in each pixel PA. The first electrode 510 may include a region that is in contact with the portion of the second drain electrode 360 of the second thin-film transistor 300 that is exposed by the corresponding pixel contact hole.”), a second electrode corresponding to the first electrode (FIG. 14, second electrode 530, [0060]), and a light emitting layer disposed between the first electrode and the second electrode (FIG. 14, light emitting layer 520 disposed between the first electrode 510 and the second electrode 530, [0060]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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