DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 13 and 20 have been amended. Claim 14 remains cancelled. No new claims have been added. Claims 1-13 and 15-20 remain pending and are ready for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8, 10, 13, 15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hyun et al. (US Publication No. 2018/0101441 -- "Hyun") in view of Wysocki et al. (US Publication No. 2019/0050161 – “Wysocki”) in further view of Fujita et al. (US Publication No. 2019/0212947 – “Fujita”).
Regarding claim 1, Hyun teaches A storage system comprising: a random access memory; a plurality of storage devices; and processing circuitry configured to control the random access memory and the plurality of storage devices, (Hyun Fig. 14; Hyun paragraph [0042], In the present exemplary embodiment, the plurality of nonvolatile memories 1310 may be referred to as a plurality of first memories. Further, the buffer memory 1350 located outside the controller 1330 may be referred to as a second memory, and the cache memory 1331 located inside the controller 1330 may be referred to as a third memory. Plurality of storage devices with cache and controller as processing circuitry, see Hyun paragraph [0165]) wherein each of the plurality of storage devices includes a nonvolatile memory device (Hyun Fig. 1; Hyun paragraph [0042], In the present exemplary embodiment, the plurality of nonvolatile memories 1310 may be referred to as a plurality of first memories. Also see Hyun paragraphs [0032-0033], The storage device 1300 may include a plurality of nonvolatile memories 1310, a controller 1330, and a buffer memory 1350. The plurality of nonvolatile memories 1310 may include nonvolatile memories 1311, 1312, 1313, and 1314. Each of the nonvolatile memories 1311, 1312, 1313, and 1314 may store write data transmitted by the host 1100, or may output read data requested by the host 1100. The storage device includes a nonvolatile memory device) Wherein each of the nonvolatile memory devices include a first storage area and a second storage area separate from the first storage area, (Hyun paragraph [0033], The plurality of nonvolatile memories 1310 may include nonvolatile memories 1311, 1312, 1313, and 1314. Each of the nonvolatile memories 1311, 1312, 1313, and 1314 may store write data transmitted by the host 1100, or may output read data requested by the host 1100. To this end, each of the nonvolatile memories 1311, 1312, 1313, and 1314 may include memory area(s) for storing data. Each of the plurality of nonvolatile memories is stated as including memory area(s) for storing data, indicating distinct/separate storage areas) wherein the processing circuitry is configured to assign a zone to the first storage areas of the plurality of storage devices, assign a plurality of Redundant Array of Inexpensive Disks (RAID) stripes to the zone assigned in the first storage areas of the plurality of storage devices, (Hyun paragraph [0005], With RAID, data is managed in units of stripes. One stripe is divided into a plurality of data chunks, and the divided data chunks are distributively stored in a plurality of separate storage areas. Further, a parity is generated based on the divided data chunks, and the generated parity is stored in one of the storage areas. When some of the data chunks are lost or damaged, the parity is used to recover or restore the lost or damaged data chunk(s). RAID stripe data areas are applied to the storage areas, and may each be distributed to distinct storage areas) write sequential data, in the first storage area, with respect to each of the plurality of RAID stripes, the sequential data based on sequential logical addresses, (Hyun paragraph [0054], The data chunks D01, D02, and D03 may be sequentially processed. Hereinafter, “sequentially” may refer to the following order: the data chunk D01, the data chunk D02, and the data chunk D03. For example, the data chunks D01, D02, and D03 may be sequentially buffered in the buffer memory 1350, which can all be written to the first storage area, see Hyun paragraph [0049], The divided data chunks and the parity may be distributively stored in a plurality of separate storage areas. For example, the nonvolatile memories 1311, 1312, 1313, and 1314 may distributively store the data chunks D01, D02, and D03 and the parity P03, respectively, under the control of the controller 1330. However, the inventive concept is not limited to this example. As another example, the data chunks D01, D02, and D03 and the parity P03 may be distributed to and stored in nonvolatile memories which are connected to different channels, or may be distributed to different memory areas in one nonvolatile memory) write a parity, in the first storage area, corresponding to the write of the sequential data with respect to each of the plurality of RAID stripes after the write of the sequential data is completed, (Hyun paragraph [0054], The data chunks D01, D02, and D03 may be sequentially processed. Hereinafter, “sequentially” may refer to the following order: the data chunk D01, the data chunk D02, and the data chunk D03. For example, the data chunks D01, D02, and D03 may be sequentially buffered in the buffer memory 1350. For example, the data chunks D01, D02, and D03 may be sequentially referenced to generate the parity P03. The data is written sequentially, followed by the corresponding parity bit, as seen above, can be written to the same storage area) and wherein the processing circuitry is further configured to write an intermediate parity, corresponding to the parity, in the second storage area of at least one storage device, among the plurality of storage devices while performing the write of the sequential data (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b. Herein, the final parity may be a parity (e.g., the parity P03) which is distributively stored in the nonvolatile memories 1310 together with the data chunks (e.g., D01 to D03), and the intermediate parity may be an intermediate result obtained while the final parity is calculated. Intermediate parity may be generated before final parity for write operation).
Hyun does not teach write an intermediate parity, corresponding to the parity, in the second storage area of at least one storage device; and wherein a write speed of the second storage area is faster than a write speed of the first storage area.
However, Wysocki teaches write an intermediate parity, corresponding to the parity, in the second storage area of at least one storage device (Wysocki paragraph [0040], In various embodiments, a RAID data layout may combine a plurality of physical storage devices into a logical drive for purposes of reliability, capacity, and/or performance. A level 5 RAID system may provide a high level of redundancy by striping both data and parity information across at least three storage devices. Data striping may be combined with distributed parity to provide a recovery path in case of failure. In some embodiments, strips of a storage device may be used to store data. A strip may be a range of logical block addresses (LBAs) written to a single storage device in a parity RAID system. A RAID controller may divide incoming host writes into strips of writes across member storage devices in a RAID volume. A stripe is a set of corresponding strips on each member storage device in the RAID volume. In an N-drive RAID 5 system, for example, each stripe contains N−1 data strips and one parity strip. A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity. The parity information, including intermediate/partial parity bits, can be written to a plurality of storage zones in storage devices, corresponding to RAID stripes).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun with those of Wysocki. Wysocki teaches storing the parity and temporary parity in the RAID storage device, which can provide additional security for the parity bits in the event of a failure or error (Wysocki paragraph [0040], A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity).
Hyun in view of Wysocki does not teach wherein a write speed of the second storage area is faster than a write speed of the first storage area.
However, Fujita teaches wherein a write speed of the second storage area is faster than a write speed of the first storage area (Fujita paragraph [0020], The second storage section 8 may be a high-speed nonvolatile memory (hNVM) 11 such as an MRAM. It is desirable that the second storage section 8 can write at least at the speed equal to or higher than that of the DRAM 10. More desirably, the second storage section 8 has a write latency of 100 ns or less. Since the second storage section 8 need only have a write latency of 100 ns or less, the second storage section 8 does not necessarily have to be configured with an MRAM, and may be configured with another nonvolatile memory. The second storage section 8 has a smaller storage capacity than that of the first storage section 7. The second storage section 8 has higher cost per unit bit than that of the first storage section 7).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki with those of Fujita. Fujita teaches a plurality of storage areas, wherein one storage area may be designed to perform at a faster write speed, which can optimize write commands to ensure that the memory system is performing at an ideal frequency by targeting higher frequency storage areas with improved write speed (i.e., see Fujita paragraph [0020], Since the second storage section 8 need only have a write latency of 100 ns or less, the second storage section 8 does not necessarily have to be configured with an MRAM, and may be configured with another nonvolatile memory. The second storage section 8 has a smaller storage capacity than that of the first storage section 7. The second storage section 8 has higher cost per unit bit than that of the first storage section 7. However, in the embodiment, by significantly reducing the storage capacity of the second storage section 8 compared with the first storage section 7, an excessive rise in part cost is prevented, and the need for a backup power supply is eliminated. Thus, reduction in total cost can be realized).
Regarding claim 2, Hyun in view of Wysocki in further view of Fujita teaches The storage system of claim 1, wherein each of the plurality of RAID stripes includes a plurality of zone areas where the sequential data is written, (Hyun paragraph [0134], In the example of FIGS. 11 to 12C, the RAID manager 1333a may receive the plurality of data D1, D2, and D3. The RAID manager 1333a may divide the data D1 into data chunks D11, D12, and D13, may divide the data D2 into data chunks D21, D22, and D23, and may divide the data D3 into data chunks D31, D32, and D33, on the basis of RAID parameter(s). In the example of FIGS. 11 to 12C, the data chunks D11, D12, D13, D21, D22, D23, D31, D32, and D33 may be sequentially processed in the order of the data chunk D11, the data chunk D21, the data chunk D31, the data chunk D12, the data chunk D22, the data chunk D32, the data chunk D13, the data chunk D23, and the data chunk D33. Data may be sequentially written to the RAID stripes, see Hyun paragraph [0054], The data chunks D01, D02, and D03 may be sequentially processed. Hereinafter, “sequentially” may refer to the following order: the data chunk D01, the data chunk D02, and the data chunk D03) and a RAID area where the parity is written, (RAID stripes can store final parity, see Hyun paragraph [0063], At time t10, the cache memory 1331 may output the final parity P03 to the nonvolatile memories 1310, in response to a request of the RAID engine 1333. Thus, the nonvolatile memories 1310 may distributively store the data chunks D01, D02, and D03 and the final parity P03) wherein the plurality of zone areas and the RAID area respectively correspond to the plurality of storage devices (Hyun paragraph [0066], For example, when the host 1100 requests to store large amounts of data or when a plurality of stripes is generated concurrently inside the storage device 1300b, a plurality of data D1, D2, and D3 may be handled. As another example, when a storage service based on namespace or logical unit number (LUN) is implemented, a plurality of data D1, D2, and D3 may be handled).
Regarding claim 3, Hyun in view of Wysocki in further view of Fujita teaches The storage system of claim 2, wherein the processing circuitry is configured to write first data in a first zone area from among zone areas of a first RAID stripe, the first zone area corresponding to a first storage device, (Hyun paragraph [0005], With RAID, data is managed in units of stripes. One stripe is divided into a plurality of data chunks, and the divided data chunks are distributively stored in a plurality of separate storage areas. Further, a parity is generated based on the divided data chunks, and the generated parity is stored in one of the storage areas. When some of the data chunks are lost or damaged, the parity is used to recover or restore the lost or damaged data chunk(s)) generate a first intermediate parity based on the first data, (Hyun paragraph [0009], The controller may generate a first intermediate parity using the first data chunk) and write the first intermediate parity in the random access memory (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b. Herein, the final parity may be a parity (e.g., the parity P03) which is distributively stored in the nonvolatile memories 1310 together with the data chunks (e.g., D01 to D03), and the intermediate parity may be an intermediate result obtained while the final parity is calculated. Intermediate parity may be generated before final parity for write operation) and in the second storage area of the at least one storage device (Wysocki paragraph [0040], In various embodiments, a RAID data layout may combine a plurality of physical storage devices into a logical drive for purposes of reliability, capacity, and/or performance. A level 5 RAID system may provide a high level of redundancy by striping both data and parity information across at least three storage devices. Data striping may be combined with distributed parity to provide a recovery path in case of failure. In some embodiments, strips of a storage device may be used to store data. A strip may be a range of logical block addresses (LBAs) written to a single storage device in a parity RAID system. A RAID controller may divide incoming host writes into strips of writes across member storage devices in a RAID volume. A stripe is a set of corresponding strips on each member storage device in the RAID volume. In an N-drive RAID 5 system, for example, each stripe contains N−1 data strips and one parity strip. A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity. The parity information, including intermediate/partial parity bits, can be written to a plurality of storage zones in storage devices, corresponding to RAID stripes).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun with those of Wysocki. Wysocki teaches storing the parity and temporary parity in the RAID storage device, which can provide additional security for the parity bits in the event of a failure or error (Wysocki paragraph [0040], A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity).
Regarding claim 4, Hyun in view of Wysocki in further view of Fujita teaches The storage system of claim 3, wherein the processing circuitry is configured to write second data in a second zone area from among the zone areas of the first RAID stripe, the second zone area corresponding to a second storage device, (Hyun paragraph [0005], With RAID, data is managed in units of stripes. One stripe is divided into a plurality of data chunks, and the divided data chunks are distributively stored in a plurality of separate storage areas. Further, a parity is generated based on the divided data chunks, and the generated parity is stored in one of the storage areas. When some of the data chunks are lost or damaged, the parity is used to recover or restore the lost or damaged data chunk(s)) read the first intermediate parity from the random access memory, (Hyun paragraph [0079], To this end, in response to a determination and a request of the RAID engine 1333, the intermediate parity P31 from the parity area 1331a may be stored in the parity area 1350b, and the intermediate parity P21 may be loaded into the empty parity area 1331a from the parity area 1350b. Next intermediate parity P22, associated with the data D2, may be generated by the parity operation, and may be stored (or updated) in the parity area 1331a. First intermediate parity may be stored and read from cache) generate a second intermediate parity based on the first intermediate parity and the second data (Hyun paragraph [0078], The parity operator 1333b may perform the parity operation on the data chunk D12 and the intermediate parity P11 to generate next intermediate parity P12 associated with the data D1. Second intermediate parity data can be generated based on second data and first intermediate parity data) and write the second intermediate parity in the second storage area of the at least one storage device (Wysocki paragraph [0040], In various embodiments, a RAID data layout may combine a plurality of physical storage devices into a logical drive for purposes of reliability, capacity, and/or performance. A level 5 RAID system may provide a high level of redundancy by striping both data and parity information across at least three storage devices. Data striping may be combined with distributed parity to provide a recovery path in case of failure. In some embodiments, strips of a storage device may be used to store data. A strip may be a range of logical block addresses (LBAs) written to a single storage device in a parity RAID system. A RAID controller may divide incoming host writes into strips of writes across member storage devices in a RAID volume. A stripe is a set of corresponding strips on each member storage device in the RAID volume. In an N-drive RAID 5 system, for example, each stripe contains N−1 data strips and one parity strip. A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity. The parity information, including intermediate/partial parity bits, can be written to a plurality of storage zones in storage devices, corresponding to RAID stripes).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun with those of Wysocki. Wysocki teaches storing the parity and temporary parity in the RAID storage device, which can provide additional security for the parity bits in the event of a failure or error (Wysocki paragraph [0040], A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity).
Regarding claim 5, Hyun in view of Wysocki in further view of Fujita teaches The storage system of claim 4, wherein the first intermediate parity is invalidated after the second intermediate parity is written (Hyun paragraph [0105], The parity operator 1333c may receive the intermediate parity D11′ along a route C, and may generate intermediate parity P11 based on the intermediate parity D11′. Each of the intermediate parities D11′ and P11 may be substantially the same as the data chunk D11. The initial intermediate parity data may be overwritten with more recent intermediate parity data targeting the same block address).
Regarding claim 6, Hyun in view of Wysocki in further view of Fujita teaches The storage system of claim 4, wherein the first intermediate parity and the second intermediate parity are written in the second storage area of the at least one storage device based on the same logical address (Hyun paragraph [0105], The parity operator 1333c may receive the intermediate parity D11′ along a route C, and may generate intermediate parity P11 based on the intermediate parity D11′. Each of the intermediate parities D11′ and P11 may be substantially the same as the data chunk D11. The initial intermediate parity data may be overwritten with more recent intermediate parity data targeting the same block address)
Regarding claim 7, Hyun in view of Wysocki in further view of Fujita teaches The storage system of claim 4, wherein the first intermediate parity and the second intermediate parity are written in the second storage area of the at least one storage device (Wysocki paragraph [0040], In various embodiments, a RAID data layout may combine a plurality of physical storage devices into a logical drive for purposes of reliability, capacity, and/or performance. A level 5 RAID system may provide a high level of redundancy by striping both data and parity information across at least three storage devices. Data striping may be combined with distributed parity to provide a recovery path in case of failure. In some embodiments, strips of a storage device may be used to store data. A strip may be a range of logical block addresses (LBAs) written to a single storage device in a parity RAID system. A RAID controller may divide incoming host writes into strips of writes across member storage devices in a RAID volume. A stripe is a set of corresponding strips on each member storage device in the RAID volume. In an N-drive RAID 5 system, for example, each stripe contains N−1 data strips and one parity strip. A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity. The parity information, including intermediate/partial parity bits, can be written to a plurality of storage zones in storage devices, corresponding to RAID stripes) based on different logical addresses (Hyun paragraph [0061], At time t5, the parity operator 1333b may receive the data chunk D02 along the route A, and may receive the intermediate parity P01 along the route B. The parity operator 1333b may perform the parity operation (e.g., an exclusive OR (XOR) operation) on the data chunk D02 and the intermediate parity P01 to generate a next intermediate parity P02. At time t6, the intermediate parity P02 may be stored (or updated) in the parity area 1331a, and the data chunk D02 may be output to the nonvolatile memories 1310. The first and second intermediate parity bits may also be based on different data chunks (addresses)).
Regarding claim 8, Hyun in view of Wysocki in further view of Fujita teaches The storage system of claim 3, wherein the processing circuitry is configured to write second data in a second zone area from among the zone areas of the first RAID stripe, the second zone area corresponding to a second storage device; (Hyun paragraph [0049], The divided data chunks and the parity may be distributively stored in a plurality of separate storage areas. For example, the nonvolatile memories 1311, 1312, 1313, and 1314 may distributively store the data chunks D01, D02, and D03 and the parity P03, respectively, under the control of the controller 1330. However, the inventive concept is not limited to this example. As another example, the data chunks D01, D02, and D03 and the parity P03 may be distributed to and stored in nonvolatile memories which are connected to different channels, or may be distributed to different memory areas in one nonvolatile memory. Write of second data can be to a different storage device) read the first intermediate parity from the random access memory, (Hyun paragraph [0079], To this end, in response to a determination and a request of the RAID engine 1333, the intermediate parity P31 from the parity area 1331a may be stored in the parity area 1350b, and the intermediate parity P21 may be loaded into the empty parity area 1331a from the parity area 1350b. Next intermediate parity P22, associated with the data D2, may be generated by the parity operation, and may be stored (or updated) in the parity area 1331a. First intermediate parity may be stored and read from cache) generate the parity based on the first intermediate parity and the second data, (Hyun paragraph [0059], The parity operator 1333b may receive a data chunk, which is buffered in the data area 1350a, along a route A. The parity operator 1333b may receive the intermediate parity, which is stored in the cache memory 1331, along a route B. The parity operator 1333b may perform a parity operation on the received data chunk and the received intermediate parity, and thus, may generate the final parity or a next intermediate parity) and write the parity in the RAID area of the first RAID stripe corresponding to the third storage device (Hyun paragraph [0063], At time t10, the cache memory 1331 may output the final parity P03 to the nonvolatile memories 1310, in response to a request of the RAID engine 1333. Thus, the nonvolatile memories 1310 may distributively store the data chunks D01, D02, and D03 and the final parity P03. Final parity may be written in the storage device).
Regarding claim 10, Hyun in view of Wysocki in further view of Fujita teaches The storage system of claim 8, wherein, after a power is turned on, the processing circuitry is configured to determine whether the parity is written in the RAID area of the first RAID stripe (Hyun paragraph [0050], Since a case where the nonvolatile memories 1311, 1312, 1313, and 1314 simultaneously cause problems rarely occurs, it is unlikely that the data chunks D01, D02, and D03 and the parity P03 are lost or damaged together. In addition, even if a specific nonvolatile memory causes a problem and some data chunks are lost or damaged, the lost or damaged data chunk(s) may be restored or recovered based on the parity P03. The system may check for the final parity in the storage if memory is lost (i.e., due to power failure)) and whether the first intermediate parity is written and read the first intermediate parity from the second storage area of the at least one storage device (see Wysocki above) in response to a determination that the parity is not written in the RAID area of the first RAID stripe (Hyun paragraph [0062], At time t7, the data chunk D03 may be buffered in the data area 1350a. At time t8, the parity operator 1333b may receive the data chunk D03 along the route A, and may receive the intermediate parity P02 along the route B. The parity operator 1333b may perform the parity operation on the data chunk D03 and the intermediate parity P02 to generate the parity P03. At time t9, the parity P03 may be stored (or updated) in the parity area 1331a, and the data chunk D03 may be output to the nonvolatile memories 1310. The intermediate parity may be accessed if it is determined to be written, and used to produce the final parity that is then stored in the storage device) and that the first intermediate parity is written in the second storage area of the at least one storage device, (Wysocki paragraph [0040], In various embodiments, a RAID data layout may combine a plurality of physical storage devices into a logical drive for purposes of reliability, capacity, and/or performance. A level 5 RAID system may provide a high level of redundancy by striping both data and parity information across at least three storage devices. Data striping may be combined with distributed parity to provide a recovery path in case of failure. In some embodiments, strips of a storage device may be used to store data. A strip may be a range of logical block addresses (LBAs) written to a single storage device in a parity RAID system. A RAID controller may divide incoming host writes into strips of writes across member storage devices in a RAID volume. A stripe is a set of corresponding strips on each member storage device in the RAID volume. In an N-drive RAID 5 system, for example, each stripe contains N−1 data strips and one parity strip. A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity. The parity information, including intermediate/partial parity bits, can be written to a plurality of storage zones in storage devices, corresponding to RAID stripes) and store the first intermediate parity in the random access memory (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun with those of Wysocki. Wysocki teaches storing the parity and temporary parity in the RAID storage device, which can provide additional security for the parity bits in the event of a failure or error (Wysocki paragraph [0040], A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity).
Regarding claim 13, Hyun teaches An operating method of a storage system including a plurality of storage devices each including a nonvolatile memory device, (Hyun Fig. 1; Hyun paragraph [0042], In the present exemplary embodiment, the plurality of nonvolatile memories 1310 may be referred to as a plurality of first memories. Also see Hyun paragraphs [0032-0033], The storage device 1300 may include a plurality of nonvolatile memories 1310, a controller 1330, and a buffer memory 1350. The plurality of nonvolatile memories 1310 may include nonvolatile memories 1311, 1312, 1313, and 1314. Each of the nonvolatile memories 1311, 1312, 1313, and 1314 may store write data transmitted by the host 1100, or may output read data requested by the host 1100. The storage device includes a nonvolatile memory device) wherein each of the nonvolatile memory devices includes including a first storage area and a second storage area separate from the first storage area, (Hyun paragraph [0033], The plurality of nonvolatile memories 1310 may include nonvolatile memories 1311, 1312, 1313, and 1314. Each of the nonvolatile memories 1311, 1312, 1313, and 1314 may store write data transmitted by the host 1100, or may output read data requested by the host 1100. To this end, each of the nonvolatile memories 1311, 1312, 1313, and 1314 may include memory area(s) for storing data. Each of the plurality of nonvolatile memories is stated as including memory area(s) for storing data, indicating distinct/separate storage areas) the method comprising: writing first data in the first storage area of a first storage device of the plurality of storage devices; (Hyun paragraph [0054], The data chunks D01, D02, and D03 may be sequentially processed. Hereinafter, “sequentially” may refer to the following order: the data chunk D01, the data chunk D02, and the data chunk D03. For example, the data chunks D01, D02, and D03 may be sequentially buffered in the buffer memory 1350) generating a first intermediate parity from the first data; (Hyun paragraph [0009], The controller may generate a first intermediate parity using the first data chunk) writing the first intermediate parity (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b. Herein, the final parity may be a parity (e.g., the parity P03) which is distributively stored in the nonvolatile memories 1310 together with the data chunks (e.g., D01 to D03), and the intermediate parity may be an intermediate result obtained while the final parity is calculated. Intermediate parity may be generated before final parity for write operation) writing second data in the first storage area of a second storage device of the plurality of storage devices; (Hyun paragraph [0007], The second memory may buffer the first and second data chunks. The controller may generate a first intermediate parity using the first data chunk, which is processed immediately before the second data chunk in connection with the target data. When the second data chunk is not a data chunk which is processed last in connection with the target data and the first intermediate parity is buffered in the second memory, the controller may generate a second intermediate parity using the buffered first intermediate parity and the second data chunk, and may output the second intermediate parity to the second memory to be buffered. Also see Hyun paragraph [0134]) generating a second intermediate parity from the first intermediate parity and the second data; (Hyun paragraph [0078], The parity operator 1333b may perform the parity operation on the data chunk D12 and the intermediate parity P11 to generate next intermediate parity P12 associated with the data D1. Second intermediate parity data can be generated based on second data and first intermediate parity data) and writing the second intermediate parity (Hyun paragraph [0007], and may output the second intermediate parity to the second memory to be buffered) writing third data in the first storage area of a third storage device; (Hyun paragraph [0075], At time t19, the parity operation associated with the data chunk D31 may be performed. The parity operator 1333b may receive the data chunk D31 along the route A, and may generate the intermediate parity P31, associated with the third data D3, based on the data chunk D31, Hyun paragraph [0075], ... and the data chunk D31 may be output to the nonvolatile memories 1310) generating a parity from the second intermediate parity and the third data; (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b. Herein, the final parity may be a parity (e.g., the parity P03) which is distributively stored in the nonvolatile memories 1310 together with the data chunks (e.g., D01 to D03), and the intermediate parity may be an intermediate result obtained while the final parity is calculated. A final parity may be generated using an intermediate parity, which can be the second intermediate parity, and the most recent data (i.e., D03)) and writing the parity in the first storage area of the fourth storage device (RAID stripes can store final parity, see Hyun paragraph [0063], At time t10, the cache memory 1331 may output the final parity P03 to the nonvolatile memories 1310, in response to a request of the RAID engine 1333. Thus, the nonvolatile memories 1310 may distributively store the data chunks D01, D02, and D03 and the final parity P03).
Hyun does not teach writing the first intermediate parity in the second storage area of a fourth storage device of the plurality of storage devices; and writing the second intermediate parity in the second storage area of the fourth storage device; wherein a write speed of the second storage area is faster than a write speed of the first storage area.
However, Wysocki teaches writing the first intermediate parity in the second storage area of a fourth storage device of the plurality of storage devices; and writing the second intermediate parity in the second storage area of the fourth storage device (Wysocki paragraph [0040], In various embodiments, a RAID data layout may combine a plurality of physical storage devices into a logical drive for purposes of reliability, capacity, and/or performance. A level 5 RAID system may provide a high level of redundancy by striping both data and parity information across at least three storage devices. Data striping may be combined with distributed parity to provide a recovery path in case of failure. In some embodiments, strips of a storage device may be used to store data. A strip may be a range of logical block addresses (LBAs) written to a single storage device in a parity RAID system. A RAID controller may divide incoming host writes into strips of writes across member storage devices in a RAID volume. A stripe is a set of corresponding strips on each member storage device in the RAID volume. In an N-drive RAID 5 system, for example, each stripe contains N−1 data strips and one parity strip. A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity. The parity information, including intermediate/partial parity bits, can be written to a plurality of storage zones in storage devices, corresponding to RAID stripes).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun with those of Wysocki. Wysocki teaches storing the parity and temporary parity in the RAID storage device, which can provide additional security for the parity bits in the event of a failure or error (Wysocki paragraph [0040], A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity).
Hyun in view of Wysocki does not teach wherein a write speed of the second storage area is faster than a write speed of the first storage area.
However, Fujita teaches wherein a write speed of the second storage area is faster than a write speed of the first storage area (Fujita paragraph [0020], The second storage section 8 may be a high-speed nonvolatile memory (hNVM) 11 such as an MRAM. It is desirable that the second storage section 8 can write at least at the speed equal to or higher than that of the DRAM 10. More desirably, the second storage section 8 has a write latency of 100 ns or less. Since the second storage section 8 need only have a write latency of 100 ns or less, the second storage section 8 does not necessarily have to be configured with an MRAM, and may be configured with another nonvolatile memory. The second storage section 8 has a smaller storage capacity than that of the first storage section 7. The second storage section 8 has higher cost per unit bit than that of the first storage section 7).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki with those of Fujita. Fujita teaches a plurality of storage areas, wherein one storage area may be designed to perform at a faster write speed, which can optimize write commands to ensure that the memory system is performing at an ideal frequency by targeting higher frequency storage areas with improved write speed (i.e., see Fujita paragraph [0020], Since the second storage section 8 need only have a write latency of 100 ns or less, the second storage section 8 does not necessarily have to be configured with an MRAM, and may be configured with another nonvolatile memory. The second storage section 8 has a smaller storage capacity than that of the first storage section 7. The second storage section 8 has higher cost per unit bit than that of the first storage section 7. However, in the embodiment, by significantly reducing the storage capacity of the second storage section 8 compared with the first storage section 7, an excessive rise in part cost is prevented, and the need for a backup power supply is eliminated. Thus, reduction in total cost can be realized).
Regarding claim 15, Hyun in view of Wysocki in further view of Fujita teaches The method of claim 13, wherein the first data, the second data, and the third data correspond to sequential logical addresses (Hyun paragraph [0054], The data chunks D01, D02, and D03 may be sequentially processed. Hereinafter, “sequentially” may refer to the following order: the data chunk D01, the data chunk D02, and the data chunk D03. For example, the data chunks D01, D02, and D03 may be sequentially buffered in the buffer memory 1350. For example, the data chunks D01, D02, and D03 may be sequentially referenced to generate the parity P03. The data is written sequentially, followed by the corresponding parity bit).
Regarding claim 20, Hyun teaches A storage system comprising: a random access memory; a plurality of storage devices; (Hyun Fig. 14; Hyun paragraph [0042], In the present exemplary embodiment, the plurality of nonvolatile memories 1310 may be referred to as a plurality of first memories. Further, the buffer memory 1350 located outside the controller 1330 may be referred to as a second memory, and the cache memory 1331 located inside the controller 1330 may be referred to as a third memory. Plurality of storage devices with cache and controller as processing circuitry, see Hyun paragraph [0165]) and a processing circuitry configured to control the random access memory and the plurality of storage devices, (Hyun Fig. 14; Hyun paragraph [0042], In the present exemplary embodiment, the plurality of nonvolatile memories 1310 may be referred to as a plurality of first memories. Further, the buffer memory 1350 located outside the controller 1330 may be referred to as a second memory, and the cache memory 1331 located inside the controller 1330 may be referred to as a third memory. Plurality of storage devices with cache and controller as processing circuitry, see Hyun paragraph [0165]) wherein each of the plurality of storage devices includes a nonvolatile memory device (Hyun Fig. 1; Hyun paragraph [0042], In the present exemplary embodiment, the plurality of nonvolatile memories 1310 may be referred to as a plurality of first memories. Also see Hyun paragraphs [0032-0033], The storage device 1300 may include a plurality of nonvolatile memories 1310, a controller 1330, and a buffer memory 1350. The plurality of nonvolatile memories 1310 may include nonvolatile memories 1311, 1312, 1313, and 1314. Each of the nonvolatile memories 1311, 1312, 1313, and 1314 may store write data transmitted by the host 1100, or may output read data requested by the host 1100. The storage device includes a nonvolatile memory device) Wherein each of the nonvolatile memory devices include a first storage area and a second storage area separate from the first storage area, (Hyun paragraph [0033], The plurality of nonvolatile memories 1310 may include nonvolatile memories 1311, 1312, 1313, and 1314. Each of the nonvolatile memories 1311, 1312, 1313, and 1314 may store write data transmitted by the host 1100, or may output read data requested by the host 1100. To this end, each of the nonvolatile memories 1311, 1312, 1313, and 1314 may include memory area(s) for storing data. Each of the plurality of nonvolatile memories is stated as including memory area(s) for storing data, indicating distinct/separate storage areas) wherein the processing circuitry is configured to assign a zone to the first storage areas of the plurality of storage devices, (Hyun paragraph [0005], With RAID, data is managed in units of stripes. One stripe is divided into a plurality of data chunks, and the divided data chunks are distributively stored in a plurality of separate storage areas. Further, a parity is generated based on the divided data chunks, and the generated parity is stored in one of the storage areas. When some of the data chunks are lost or damaged, the parity is used to recover or restore the lost or damaged data chunk(s). RAID stripe data areas are applied to the storage areas) write first data in the first storage area of a first storage device of the plurality of storage devices, (Hyun paragraph [0054], The data chunks D01, D02, and D03 may be sequentially processed. Hereinafter, “sequentially” may refer to the following order: the data chunk D01, the data chunk D02, and the data chunk D03. For example, the data chunks D01, D02, and D03 may be sequentially buffered in the buffer memory 1350) generate a first intermediate parity from the first data, (Hyun paragraph [0009], The controller may generate a first intermediate parity using the first data chunk) write the first intermediate parity in the random access memory (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b. Herein, the final parity may be a parity (e.g., the parity P03) which is distributively stored in the nonvolatile memories 1310 together with the data chunks (e.g., D01 to D03), and the intermediate parity may be an intermediate result obtained while the final parity is calculated. Intermediate parity may be generated before final parity for write operation) write second data in the first storage area of a second storage device of the plurality of storage devices, (Hyun paragraph [0007], The second memory may buffer the first and second data chunks. The controller may generate a first intermediate parity using the first data chunk, which is processed immediately before the second data chunk in connection with the target data. When the second data chunk is not a data chunk which is processed last in connection with the target data and the first intermediate parity is buffered in the second memory, the controller may generate a second intermediate parity using the buffered first intermediate parity and the second data chunk, and may output the second intermediate parity to the second memory to be buffered. Also see Hyun paragraph [0134]) generate a second intermediate parity from the first intermediate parity and the second data, (Hyun paragraph [0078], The parity operator 1333b may perform the parity operation on the data chunk D12 and the intermediate parity P11 to generate next intermediate parity P12 associated with the data D1. Second intermediate parity data can be generated based on second data and first intermediate parity data) write the second intermediate parity in the random access memory (Hyun paragraph [0007], and may output the second intermediate parity to the second memory to be buffered) write third data in the first storage area of a third storage device, generate a parity from the second intermediate parity and the third data, and write the parity in the first storage area of the fourth storage device (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b. Herein, the final parity may be a parity (e.g., the parity P03) which is distributively stored in the nonvolatile memories 1310 together with the data chunks (e.g., D01 to D03), and the intermediate parity may be an intermediate result obtained while the final parity is calculated. A final parity may be generated using an intermediate parity, which can be the second intermediate parity, and the most recent data (i.e., D03)).
Hyun does not teach write the first intermediate parity in the random access memory and the second storage area of a fourth storage device of the plurality of storage devices, write the second intermediate parity in the random access memory and the second storage area of the fourth storage device; wherein a write speed of the second storage area is faster than a write speed of the first storage area.
However, Wysocki teaches write the first intermediate parity in the random access memory and the second storage area of a fourth storage device of the plurality of storage devices, write the second intermediate parity in the random access memory and the second storage area of the fourth storage device (Wysocki paragraph [0040], In various embodiments, a RAID data layout may combine a plurality of physical storage devices into a logical drive for purposes of reliability, capacity, and/or performance. A level 5 RAID system may provide a high level of redundancy by striping both data and parity information across at least three storage devices. Data striping may be combined with distributed parity to provide a recovery path in case of failure. In some embodiments, strips of a storage device may be used to store data. A strip may be a range of logical block addresses (LBAs) written to a single storage device in a parity RAID system. A RAID controller may divide incoming host writes into strips of writes across member storage devices in a RAID volume. A stripe is a set of corresponding strips on each member storage device in the RAID volume. In an N-drive RAID 5 system, for example, each stripe contains N−1 data strips and one parity strip. A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity. The parity information, including intermediate/partial parity bits, can be written to a plurality of storage zones in storage devices, corresponding to RAID stripes).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun with those of Wysocki. Wysocki teaches storing the parity and temporary parity in the RAID storage device, which can provide additional security for the parity bits in the event of a failure or error (Wysocki paragraph [0040], A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity).
Hyun in view of Wysocki does not teach wherein a write speed of the second storage area is faster than a write speed of the first storage area.
However, Fujita teaches wherein a write speed of the second storage area is faster than a write speed of the first storage area (Fujita paragraph [0020], The second storage section 8 may be a high-speed nonvolatile memory (hNVM) 11 such as an MRAM. It is desirable that the second storage section 8 can write at least at the speed equal to or higher than that of the DRAM 10. More desirably, the second storage section 8 has a write latency of 100 ns or less. Since the second storage section 8 need only have a write latency of 100 ns or less, the second storage section 8 does not necessarily have to be configured with an MRAM, and may be configured with another nonvolatile memory. The second storage section 8 has a smaller storage capacity than that of the first storage section 7. The second storage section 8 has higher cost per unit bit than that of the first storage section 7).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki with those of Fujita. Fujita teaches a plurality of storage areas, wherein one storage area may be designed to perform at a faster write speed, which can optimize write commands to ensure that the memory system is performing at an ideal frequency by targeting higher frequency storage areas with improved write speed (i.e., see Fujita paragraph [0020], Since the second storage section 8 need only have a write latency of 100 ns or less, the second storage section 8 does not necessarily have to be configured with an MRAM, and may be configured with another nonvolatile memory. The second storage section 8 has a smaller storage capacity than that of the first storage section 7. The second storage section 8 has higher cost per unit bit than that of the first storage section 7. However, in the embodiment, by significantly reducing the storage capacity of the second storage section 8 compared with the first storage section 7, an excessive rise in part cost is prevented, and the need for a backup power supply is eliminated. Thus, reduction in total cost can be realized).
Claim(s) 9 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hyun in view of Wysocki in further view of Fujita as applied to claims 8 and 14 above, and further in view of Muchherla et al. (US Publication No. 2024/0045616 -- "Muchherla").
Regarding claim 9, Hyun in view of Wysocki in further view of Fujita and further in view of Muchherla teaches The storage system of claim 8, (see Hyun and Wysocki above) wherein, the first intermediate parity is invalidated after the parity is written (Muchherla claim 12, wherein the processing device is further to: scan the first block and the second block in response to the completion of the second pass of programming the first block and the second block; determine whether the first block and the second block contain defects; and invalidate the first temporary parity data and the second temporary parity data in response to determining that the first block and the second block do not contain defects. The first, and potentially second, intermediate parity bits can be invalidated after the parity has been written and the write is confirmed) in the RAID area of the first RAID stripe corresponding to the third storage device (Hyun paragraph [0063], At time t10, the cache memory 1331 may output the final parity P03 to the nonvolatile memories 1310, in response to a request of the RAID engine 1333. Thus, the nonvolatile memories 1310 may distributively store the data chunks D01, D02, and D03 and the final parity P03. Final parity may be written in the storage device).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki and Fujita with those of Muchherla. Muchherla explicitly teaches invalidating the intermediate parity bits after the final parity bit is written, which removes the intermediate parity bits from the cache/storage and allows for future intermediate parity bits to be written (Muchherla paragraph [0018], Aspects of the present disclosure address the above and other deficiencies by buffering a combination of user data and temporary parity data in place of at least a portion of the user data. The temporary parity data takes up less space than the user data and allows the user data to be cleared from the buffer sooner, thereby requiring fewer buffer blocks. Because there are fewer buffer blocks required, the use of temporary parity data reduces the overprovisioning penalty. Additionally, there is not an increase in UBER that would typically accompany a smaller buffer size because data loss is only a risk when the errors exceed the error correction capability of the temporary parity data).
Regarding claim 16, Hyun in view of Wysocki in further view of Fujita and further in view of Muchherla teaches The method of claim 13, further comprising: (see Hyun and Wysocki and Fujita above) invalidating the first intermediate parity of the second storage area of the fourth storage device after writing the second intermediate parity in the second storage area of the fourth storage device; and invalidating the second intermediate parity of the second storage area of the fourth storage device after writing the parity in the first storage area of the fourth storage device (Muchherla claim 12, wherein the processing device is further to: scan the first block and the second block in response to the completion of the second pass of programming the first block and the second block; determine whether the first block and the second block contain defects; and invalidate the first temporary parity data and the second temporary parity data in response to determining that the first block and the second block do not contain defects. The first, and potentially second, intermediate parity bits can be invalidated after the parity has been written and the write is confirmed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki and Fujita with those of Muchherla. Muchherla explicitly teaches invalidating the intermediate parity bits after the final parity bit is written, which removes the intermediate parity bits from the cache/storage and allows for future intermediate parity bits to be written (Muchherla paragraph [0018], Aspects of the present disclosure address the above and other deficiencies by buffering a combination of user data and temporary parity data in place of at least a portion of the user data. The temporary parity data takes up less space than the user data and allows the user data to be cleared from the buffer sooner, thereby requiring fewer buffer blocks. Because there are fewer buffer blocks required, the use of temporary parity data reduces the overprovisioning penalty. Additionally, there is not an increase in UBER that would typically accompany a smaller buffer size because data loss is only a risk when the errors exceed the error correction capability of the temporary parity data).
Regarding claim 17, Hyun in view of Wysocki in further view of Fujita and further in view of Muchherla teaches The method of claim 13, further comprising: (see Hyun and Wysocki and Fujita above) invalidating the first intermediate parity and the second intermediate parity of the second storage area of the fourth storage device after writing the parity in the first storage area of the fourth storage device (Muchherla claim 12, wherein the processing device is further to: scan the first block and the second block in response to the completion of the second pass of programming the first block and the second block; determine whether the first block and the second block contain defects; and invalidate the first temporary parity data and the second temporary parity data in response to determining that the first block and the second block do not contain defects. The first, and potentially second, intermediate parity bits can be invalidated after the parity has been written and the write is confirmed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki and Fujita with those of Muchherla. Muchherla explicitly teaches invalidating the intermediate parity bits after the final parity bit is written, which removes the intermediate parity bits from the cache/storage and allows for future intermediate parity bits to be written (Muchherla paragraph [0018], Aspects of the present disclosure address the above and other deficiencies by buffering a combination of user data and temporary parity data in place of at least a portion of the user data. The temporary parity data takes up less space than the user data and allows the user data to be cleared from the buffer sooner, thereby requiring fewer buffer blocks. Because there are fewer buffer blocks required, the use of temporary parity data reduces the overprovisioning penalty. Additionally, there is not an increase in UBER that would typically accompany a smaller buffer size because data loss is only a risk when the errors exceed the error correction capability of the temporary parity data).
Claim(s) 11-12 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hyun in view of Wysocki in further view of Fujita as applied to claims 8 and 14 above, and further in view of Desai et al. (US Publication No. 2023/0325278 -- "Desai").
Regarding claim 11, Hyun in view of Wysocki in further view of Fujita and further in view of Desai teaches The storage system of claim 8, wherein, when an error occurs in the first RAID stripe, the processing circuitry is configured to determine whether the parity is written in the RAID area of the first RAID stripe and whether the first intermediate parity is written (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b. Herein, the final parity may be a parity (e.g., the parity P03) which is distributively stored in the nonvolatile memories 1310 together with the data chunks (e.g., D01 to D03), and the intermediate parity may be an intermediate result obtained while the final parity is calculated. The final parity may be checked when an error occurs, in the RAID stripe, see Hyun paragraph [0063], The RAID engine 1333 may determine, based on the meta- or header information, that the parity P03 is the final parity. At time t10, the cache memory 1331 may output the final parity P03 to the nonvolatile memories 1310, in response to a request of the RAID engine 1333. Thus, the nonvolatile memories 1310 may distributively store the data chunks D01, D02, and D03 and the final parity P03) in the second storage area of the at least one storage device, (Wysocki paragraph [0040], In various embodiments, a RAID data layout may combine a plurality of physical storage devices into a logical drive for purposes of reliability, capacity, and/or performance. A level 5 RAID system may provide a high level of redundancy by striping both data and parity information across at least three storage devices. Data striping may be combined with distributed parity to provide a recovery path in case of failure. In some embodiments, strips of a storage device may be used to store data. A strip may be a range of logical block addresses (LBAs) written to a single storage device in a parity RAID system. A RAID controller may divide incoming host writes into strips of writes across member storage devices in a RAID volume. A stripe is a set of corresponding strips on each member storage device in the RAID volume. In an N-drive RAID 5 system, for example, each stripe contains N−1 data strips and one parity strip. A parity strip may be the exclusive OR (XOR) of the data in the data strips in the stripe. The storage device that stores the parity for the stripe may be rotated per-stripe across the member storage devices. Parity may be used to restore data on a storage device of the RAID system should the storage device fail, become corrupted or lose power. Different algorithms may be used that, during a write operation to a stripe, calculate partial parity that is an intermediate value for determining parity. The parity information, including intermediate/partial parity bits, can be written to a plurality of storage zones in storage devices, corresponding to RAID stripes) and recover the first RAID stripe based on data written in the first RAID stripe and the first intermediate parity (Desai paragraph [0073], As discussed above, any of the intermediate parity data generated for subsets of data may be utilized to reconstruct a portion of that subset of data in the event that portion of the subset of the data is unrecoverable from its storage location) in response to a determination that the parity is not written in the RAID area of the first RAID stripe and that the first intermediate parity is written in the second storage area of the at least one storage device (Desai paragraph [0054], while also generating and storing intermediate parity data for those subsets of the primary data so that they may be reconstructed in the event they are unrecoverable from the storage subsystem 212. As discussed below, such operations reduce performance issues such as those that produce the “excursions” and reduced QoS in storage device write performance discussed above, and reduce storage device cost by reducing the need for larger volatile memory systems and associated power backup subsystem required for non-volatile memory system used to back up the volatile memory system. Furthermore, one of skill in the art in possession of the present disclosure will appreciate how the RAID data write operations discussed in the specific examples above are RAIDS data writes that generate parity data for primary data in order to allow the reconstruction of a single segment of the primary data in the event that it become unrecoverable, and that the teachings below may be extended to RAID6 data writes that generate both parity data and “Q” data for primary data in order to allow the reconstruction of two segments of the primary data in the event that it become unrecoverable while remaining within the scope of the present disclosure as well. RAID stripe data can be recovered via an intermediate parity bit if available (and correspondingly, final parity is not completed)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki and Fujita with those of Desai. Desai teaches using an intermediate parity for data recovery. Particularly, Desai teaches using an intermediate parity stored in a cache for recovery, but also has the ability to access the intermediate parity stored in non-volatile memory if an error occurs where it cannot be recovered via volatile memory. This improves the reliability of the data recovery by also storing the intermediate parity in NVM (see Desai paragraph [0003], For example, RAIDS techniques provide for the generation and storage of parity data with “primary” data (e.g., which includes data provided by a host for storage) that is written to a storage subsystem in a storage device, and one of skill in the art in possession of the present disclosure will appreciate how, in the event a portion of the primary data written to the storage subsystem in the storage device is not recoverable, the portions of the primary data that are recoverable and its corresponding parity data may be used to reconstruct the portion of the primary data that is not recoverable. However, due the possibility of write errors, power loss, or other issues that may occur during the writing of primary data to storage subsystems in storage devices, conventional storage devices operate to store the primary data (and any associated data/metadata) in their volatile memory systems (e.g., in buffers) until all the primary data and its corresponding parity data have been successfully written to the storage subsystem in the storage device, which can raise some issues).
Regarding claim 12, Hyun in view of Wysocki in further view of Fujita and further in view of Desai teaches The storage system of claim 1, wherein the processing circuitry is further configured to store the intermediate parity corresponding to the parity in the random access memory, (Hyun paragraph [0057], The cache memory 1331 may store operation results of the parity operator 1333b. For example, the cache memory 1331 may include parity areas 1331a and 1331b allocated to store a final parity and an intermediate parity calculated by the parity operator 1333b. Herein, the final parity may be a parity (e.g., the parity P03) which is distributively stored in the nonvolatile memories 1310 together with the data chunks (e.g., D01 to D03), and the intermediate parity may be an intermediate result obtained while the final parity is calculated. Intermediate parity may be stored and accessed in cache) generate the parity using the intermediate parity written in the second storage area of the at least one storage device among the plurality of storage devices in response to an error occurring in the intermediate parity stored in the random access memory or a power-on event occurring after a power-off event, (Desai claim 6, detect a power loss during a storage operation to store a third subset of the first primary data in the storage subsystem; store, in response to detecting the power loss, the first intermediate parity data and the second intermediate parity data in a non-volatile memory system; determine, in response to power becoming available subsequent to detecting the power loss, that a first portion of the first subset of the first primary data stored in the storage subsystem is unrecoverable; and use the first intermediate parity data stored in the non-volatile memory system to recover the first portion of the first subset of the first primary data. The intermediate parity may be recovered from non-volatile memory if necessary and cannot be accessed via the volatile memory) and generate the parity using the intermediate parity stored in the random access memory in response to the error not occurring in the intermediate parity stored in the random access memory or the power-off event and the power-on event not occurring (Desai claim 5, determine that a storage operation to store a third subset of the first primary data in the storage subsystem has failed; determine that a first portion of the first subset of the first primary data stored in the storage subsystem is unrecoverable; and use the first intermediate parity data stored in the volatile memory system to recover the first portion of the first subset of the first primary data. If no error or power event occurs, the intermediate parity stored in volatile memory can be used to recover data).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki and Fujita with those of Desai. Desai teaches using an intermediate parity for data recovery. Particularly, Desai teaches using an intermediate parity stored in a cache for recovery, but also has the ability to access the intermediate parity stored in non-volatile memory if an error occurs where it cannot be recovered via volatile memory. This improves the reliability of the data recovery by also storing the intermediate parity in NVM (see Desai paragraph [0003], For example, RAIDS techniques provide for the generation and storage of parity data with “primary” data (e.g., which includes data provided by a host for storage) that is written to a storage subsystem in a storage device, and one of skill in the art in possession of the present disclosure will appreciate how, in the event a portion of the primary data written to the storage subsystem in the storage device is not recoverable, the portions of the primary data that are recoverable and its corresponding parity data may be used to reconstruct the portion of the primary data that is not recoverable. However, due the possibility of write errors, power loss, or other issues that may occur during the writing of primary data to storage subsystems in storage devices, conventional storage devices operate to store the primary data (and any associated data/metadata) in their volatile memory systems (e.g., in buffers) until all the primary data and its corresponding parity data have been successfully written to the storage subsystem in the storage device, which can raise some issues).
Regarding claim 18, Hyun in view of Wysocki in further view of Fujita and further in view of Desai teaches The method of claim 13, further comprising: (see Hyun and Wysocki above) recovering the first data, the second data, and the second intermediate parity based on the first data, the second data, and the second intermediate parity in response to an error occurring in the first data or the second data before the parity is written in the first storage area of the fourth storage device (Desai paragraph [0073], As discussed above, any of the intermediate parity data generated for subsets of data may be utilized to reconstruct a portion of that subset of data in the event that portion of the subset of the data is unrecoverable from its storage location. In response to an error, the intermediate parity bits can be used for data recovery, Desai paragraph [0054], while also generating and storing intermediate parity data for those subsets of the primary data so that they may be reconstructed in the event they are unrecoverable from the storage subsystem 212. As discussed below, such operations reduce performance issues such as those that produce the “excursions” and reduced QoS in storage device write performance discussed above, and reduce storage device cost by reducing the need for larger volatile memory systems and associated power backup subsystem required for non-volatile memory system used to back up the volatile memory system. Furthermore, one of skill in the art in possession of the present disclosure will appreciate how the RAID data write operations discussed in the specific examples above are RAIDS data writes that generate parity data for primary data in order to allow the reconstruction of a single segment of the primary data in the event that it become unrecoverable, and that the teachings below may be extended to RAID6 data writes that generate both parity data and “Q” data for primary data in order to allow the reconstruction of two segments of the primary data in the event that it become unrecoverable while remaining within the scope of the present disclosure as well. RAID stripe data can be recovered via an intermediate parity bit if available (and correspondingly, final parity is not completed)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki and Fujita with those of Desai. Desai teaches using an intermediate parity for data recovery. Particularly, Desai teaches using an intermediate parity stored in a cache for recovery, but also has the ability to access the intermediate parity stored in non-volatile memory if an error occurs where it cannot be recovered via volatile memory. This improves the reliability of the data recovery by also storing the intermediate parity in NVM (see Desai paragraph [0003], For example, RAIDS techniques provide for the generation and storage of parity data with “primary” data (e.g., which includes data provided by a host for storage) that is written to a storage subsystem in a storage device, and one of skill in the art in possession of the present disclosure will appreciate how, in the event a portion of the primary data written to the storage subsystem in the storage device is not recoverable, the portions of the primary data that are recoverable and its corresponding parity data may be used to reconstruct the portion of the primary data that is not recoverable. However, due the possibility of write errors, power loss, or other issues that may occur during the writing of primary data to storage subsystems in storage devices, conventional storage devices operate to store the primary data (and any associated data/metadata) in their volatile memory systems (e.g., in buffers) until all the primary data and its corresponding parity data have been successfully written to the storage subsystem in the storage device, which can raise some issues).
Regarding claim 19, Hyun in view of Wysocki in further view of Fujita and further in view of Desai teaches The method of claim 13, further comprising: (see Hyun and Wysocki above) recovering the first data, the second data, the third data, and the parity based on the first data, the second data, the third data, and the parity in response to an error occurring in the first data, the second data, or the third data after the parity is written in the first storage area of the fourth storage device (Desai paragraph [0073], As discussed above, any of the intermediate parity data generated for subsets of data may be utilized to reconstruct a portion of that subset of data in the event that portion of the subset of the data is unrecoverable from its storage location. In response to an error, the intermediate parity bits can be used for data recovery, Desai paragraph [0054], while also generating and storing intermediate parity data for those subsets of the primary data so that they may be reconstructed in the event they are unrecoverable from the storage subsystem 212. As discussed below, such operations reduce performance issues such as those that produce the “excursions” and reduced QoS in storage device write performance discussed above, and reduce storage device cost by reducing the need for larger volatile memory systems and associated power backup subsystem required for non-volatile memory system used to back up the volatile memory system. Furthermore, one of skill in the art in possession of the present disclosure will appreciate how the RAID data write operations discussed in the specific examples above are RAIDS data writes that generate parity data for primary data in order to allow the reconstruction of a single segment of the primary data in the event that it become unrecoverable, and that the teachings below may be extended to RAID6 data writes that generate both parity data and “Q” data for primary data in order to allow the reconstruction of two segments of the primary data in the event that it become unrecoverable while remaining within the scope of the present disclosure as well. RAID stripe data can be recovered via an intermediate parity bit if available (and correspondingly, final parity is not completed)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hyun and Wysocki and Fujita with those of Desai. Desai teaches using an intermediate parity for data recovery. Particularly, Desai teaches using an intermediate parity stored in a cache for recovery, but also has the ability to access the intermediate parity stored in non-volatile memory if an error occurs where it cannot be recovered via volatile memory. This improves the reliability of the data recovery by also storing the intermediate parity in NVM (see Desai paragraph [0003], For example, RAIDS techniques provide for the generation and storage of parity data with “primary” data (e.g., which includes data provided by a host for storage) that is written to a storage subsystem in a storage device, and one of skill in the art in possession of the present disclosure will appreciate how, in the event a portion of the primary data written to the storage subsystem in the storage device is not recoverable, the portions of the primary data that are recoverable and its corresponding parity data may be used to reconstruct the portion of the primary data that is not recoverable. However, due the possibility of write errors, power loss, or other issues that may occur during the writing of primary data to storage subsystems in storage devices, conventional storage devices operate to store the primary data (and any associated data/metadata) in their volatile memory systems (e.g., in buffers) until all the primary data and its corresponding parity data have been successfully written to the storage subsystem in the storage device, which can raise some issues).
Response to Arguments
Applicant's arguments filed January 21st, 2026 have been fully considered but they are not persuasive.
Applicant argues:
“In sum, without conceding as to any of the Examiner's assertions that are not specifically addressed herein, Applicants note that the cited art fails to disclose or suggest all of the elements of the claims. For at least the reasons above, a prima facie case of obviousness cannot be established with regard to claims 1, 13, and 20. Consequently, a prima facie case of obviousness cannot be established with regard to claims 2-8, 10, 14-15, and 20, at least by virtue of their dependency from claims 1 and 13. Accordingly, Applicants request the Examiner to reconsider and withdraw the above rejection. Claims 9 and 16-17 stand rejected under 35 U.S.C. § 103 as being unpatentable over Hyun in view of Wysocki and Fujita as applied to claims 8 and 14 above, and further in view of in view of U.S. Application Patent Publication No. 2024/0045616 ("Muchherla"). Applicants traverse this rejection for at least the reason that Muchherla does not overcome the deficiencies of Hyun, Wysocki and/or Fujita. From even a cursory review, it is readily apparent that Muchherla does not overcome the deficiencies of Hyun and Wysocki in view of Fujita. Accordingly, Hyun in view of Wysocki , Fujita, and Muchherla fails to render claims 1 and 13 as obvious to one skilled in the art. Consequently, a prima facie case of obviousness cannot be established with regard to claims 9 and 16-17, at least by virtue of their dependency from claims 1 and 13.”
The examiner respectfully disagrees. Upon further consideration of the claim amendments with respect to the cited references, the examiner notes that while the claim amendment does distinguish from the Fujita reference that was previously added in the Non-Final Rejection, the concept of disclosing each of the nonvolatile memory devices including a distinct first and storage areas is in fact disclosed by the Hyun reference. Specifically, the plurality of nonvolatile memories disclosed in Hyun may each contain a plurality of storage areas that are distinct (i.e., see Hyun paragraph [0033], The plurality of nonvolatile memories 1310 may include nonvolatile memories 1311, 1312, 1313, and 1314. Each of the nonvolatile memories 1311, 1312, 1313, and 1314 may store write data transmitted by the host 1100, or may output read data requested by the host 1100. To this end, each of the nonvolatile memories 1311, 1312, 1313, and 1314 may include memory area(s) for storing data. Each of the plurality of nonvolatile memories is stated as including memory area(s) for storing data, indicating distinct/separate storage areas) as cited in the rejection above. In light of the newly cited portion of Hyun, the 35 USC 103 Rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miyoshi et al. (US Publication No. 2020/0334103) teaches a similar concept of utilizing parity and intermediate parity bits in a RAID structure, including a storage drive containing a plurality of nonvolatile memories which can be subdivided further (i.e., see Miyoshi Fig. 5A-5B; Miyoshi paragraph [0102], As described above, even in a case in which the RAID group is configured across a plurality of drive boxes, each drive box 14 manages the RAID group information and the DB information, and thus it is possible to detect the transfer destination of the intermediate parity generated from the new data and the old data on the basis of other drive boxes constituting the RAID group, drives, or the address information in the drives. In other words, the RAID group can be configured with an arbitrary combination of a plurality of drive boxes 14 connected to the storage controller 12, and the flexibility and the reliability of the system configuration can be improved. Further, data is directly transferred between the drives without the intervention of the storage controller by employing a protocol in which data can directly be transferred from the data transfer source to the transfer destination such as the NVMe protocol for the detected transfer destination, and thus the processing load of the storage controller can be reduced).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.C.K./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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