Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 18 objected to because of the following informalities: there is a grammatical problem in “to iteratively executing the machine-readable process.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 9, 16, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, it recites “one or more special caches;” however, this is not a term of art and the specification merely refers to the term and never defines or characterizes it (see Spec at ¶¶ 13, 16, 102, 107, 113, 124, and 134). Therefore, the metes and bounds of the “one or more special caches” cannot be determined. Claim 16 corresponds to claim 6; therefore, it is indefinite for the same reason.
Regarding claim 9, it refers to “benchmark metrics;” however, only “a benchmark metric” has been defined. Therefore, reference to “the benchmark metrics” lacks antecedent basis. Claim 19 corresponds to claim 9; therefore, it is indefinite for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 11-13, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong (US 2009/0241122) and further in view of Tsirkin (US 2018/0239626).
Regarding claim 1, Wong teaches: A method comprising:
executing, by a virtual (¶ 58, “heavily used parallel code segments 406 are passed to operating system 408 to be executed using two or more of processing resource combinations 410” and ¶ 48, “The various combinations of resources that are analyzed by the illustrative embodiments may comprise physical processors, virtual processors, or even one or more cores within a physical processor chip”);
determining, by the virtual (¶ 59, “The score given to each parallel code segment may be based on a metric associated with each individual parallel code segment, such as floating-point operations per second (FLOPS), elapsed time for processing the code segment, or any other benchmark measurement for rating the speed of the processing resource combination”);
iteratively executing, by the virtual (¶ 62, “Once the sampling engine collects the heavily used parallel code segments from the application, the operating system executes each of the heavily used parallel code segments using two or more of the processing resource combinations (step 604)” and “As the operating system runs each of the heavily used parallel code segments using each of the two or more processing resource combinations, the operating system gives a score to each parallel code segment (step 606), which are recorded in a performance data structure”); and
determining, by the virtual (¶ 63, “Based on the accepted performance level, the performance analyzer selects the identified combination of processing resources that uses the fewest processing resources to run the application (step 610)”).
Wong does not teach; however, Tsirkin teaches: executing, by a virtual machine, a benchmark test to evaluate performance of hyperthreading (¶ 29, “a hypervisor 160 may execute a VCPU 174A of a virtual machine 170A in a first hyper-thread 122A of a physical processor 120A (blocks 302 & 304). Then, the hypervisor 160 may execute a monitoring task in a second hyper-thread 122B of the physical processor 120B (blocks 306 & 308)”).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to have applied the known technique of executing, by a virtual machine, a benchmark test to evaluate performance of hyperthreading, as taught by Tsirkin, in the same way to the determining a hyperthreading arrangement, as taught by Wong. Both inventions are in the field of hyperthreading scheduling, and combining them would have predictably resulted in “efficient virtual machine memory monitoring with hyper-threading,” as indicated by Tsirkin (¶ 3).
Regarding claim 2, Wong teaches: The method of claim 1, wherein the benchmark metric is an execution duration for the machine-readable process on a single core (¶ 59, “The score given to each parallel code segment may be based on a metric associated with each individual parallel code segment, such as floating-point operations per second (FLOPS), elapsed time for processing the code segment”), and wherein the execution metrics are execution durations for the machine-readable process concurrently across two threads (¶ 58, “the user may have processing resource combinations 410 that include four physical processors, three physical processors, two physical processors, or even one physical processor”).
Regarding claim 3, Wong teaches: The method of claim 1, wherein executing the machine-readable process on the core of the host device comprises selecting, by the virtual machine, one of the cores of the virtual machine in which to execute the machine-readable process (¶ 63, “Based on the accepted performance level, the performance analyzer selects the identified combination of processing resources that uses the fewest processing resources to run the application (step 610)”).
Regarding claim 5, Tsirkin teaches: The method of claim 1, wherein the machine-readable process is configured for the host device, to increase shared resources and partition resources used by a respective core, to increase an execution duration for instances in which the machine-readable process is executed by two threads of a single core of the host device (¶ 9, “Because the processor resources are shared and the architectural state is duplicated for the two hyper-threads, communication through shared memory between the two hyper-threads within the same processor is relatively cheap and efficient. However, because the central processing unit (CPU) execution engine is shared between multiple hyper-threads, unless one of the hyper-threads is halted, the other hyper-thread typically executes at best at half the maximum speed due to the execution engine conflict”).
Claims 11-13, 15, and 20 recite commensurate subject matter as claims 1-3 and 5. Therefore, they are rejected for the same reasons.
Claim(s) 4, 7, 10, 14, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong and Tsirkin, as applied above, and further in view of Cropper (US 2015/0355931).
Regarding claim 4, Wong and Tsirkin do not teach; however, Cropper teaches: wherein each core of the virtual machine is executed on a respective core, or a respective thread of the core, of the multi-core processing system of the host device (¶ 114, “When the SMT parameter is off (step 2620=YES), each vCPU is placed on a different physical core (step 2630)”).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to have applied the known technique of wherein each core of the virtual machine is executed on a respective core, or a respective thread of the core, of the multi-core processing system of the host device, as taught by Cropper, in the same way to the shared resources, as taught by Wong and Tsirkin. Both inventions are in the field of running virtual processors on a host CPU, and combining them would have predictably resulted in “a more efficient usage of CPU cores and threads,” as indicated by Cropper (¶ 126).
Regarding claim 7, Wong and Tsirkin do not teach; however, Cropper teaches: selecting, by the virtual machine, according to the hyperthreading arrangement, cores of the virtual machine to execute on respective threads of the multi-core processing system of the host device (¶ 114, “When the SMT parameter is off (step 2620=YES), each vCPU is placed on a different physical core (step 2630). When the SMT parameter is on (step 2620=NO), vCPUs can be placed on different hardware threads on the same physical core (step 2640). Method 2600 is then done”).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to have applied the known technique of selecting, by the virtual machine, according to the hyperthreading arrangement, cores of the virtual machine to execute on respective threads of the multi-core processing system of the host device, as taught by Cropper, in the same way to the virtual machine on the host device, as taught by Wong and Tsirkin. Both inventions are in the field of running virtual processors on a host CPU, and combining them would have predictably resulted in “a more efficient usage of CPU cores and threads,” as indicated by Cropper (¶ 126).
Regarding claim 10, Wong and Tsirkin do not teach; however, Cropper teaches: provisioning, by an intermediary device, the virtual machine to the host device for execution (¶ 99, “A host is then selected that has resources that satisfy the resource requirements in the cloud VM request (step 730). The VM is then deployed on the selected host computer system (step 740)”).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to have applied the known technique of provisioning, by an intermediary device, the virtual machine to the host device for execution, as taught by Cropper, in the same way to the virtual machine on a host device, as taught by Wong and Tsirkin. Both inventions are in the field of running virtual processors on a host CPU, and combining them would have predictably resulted in “a more efficient usage of CPU cores and threads,” as indicated by Cropper (¶ 126).
Claims 14 and 17 recite commensurate subject matter as claims 4 and 7. Therefore, they are rejected for the same reasons.
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong and Tsirkin, as applied above, and further in view of Hrusecky (US 2006/0184741).
Regarding claim 6, Wong and Tsirkin do not teach; however, Hrusecky teaches: one or more execution ports or a layer 1 cache (¶ 8, “A multithreaded (SMT) processor fetches data from memory and stores it into a single L1 data cache array”), and wherein the partition resources comprise one or more special caches (¶ 32, “At any one time the data cache can be divided into a first portion that is designated for the exclusive use of a one thread, a portion that is designated for the exclusive use of the other thread, and a portion that is designated as shared between the two threads”).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to have applied the known technique of one or more execution ports or a layer 1 cache, and wherein the partition resources comprise one or more special caches, as taught by Hrusecky, in the same way to the shared resources, as taught by Wong and Tsirkin. Both inventions are in the field of running software on a multithreaded processor, and combining them would have predictably resulted in “sharing data in a cache among threads in a simultaneous multi-threaded processor,” as indicated by Hrusecky (¶ 2).
Claim 16 recites commensurate subject matter as claim 6. Therefore, it is rejected for the same reason.
Claim(s) 8, 9, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong and Tsirkin, as applied above, and further in view of Harris (US 2018/0113965).
Regarding claim 8, Wong and Tsirkin do not teach; however, Harris teaches: selecting, by the virtual machine, a first core and a second core of the virtual machine (¶ 62, “two threads may be executed on the core, such as to assess if the core suffers a loss in peak performance when co-scheduling multiple software threads on different hardware thread contexts provided by the core”); executing, by the virtual machine, the machine-readable process concurrently on the first core and the second core, the first core executed on a first thread of the multi-core processing system and the second core executed on a second thread of the multi-core processing system (¶ 145, “the experiments where repeated on a two socket Intel Sandy Bridge machine with 8 cores per socket, providing 32 hardware threads in total, according to one example evaluation embodiment”); and determining, by the virtual machine, first execution metrics for the first thread and the second thread, responsive to executing the machine-readable process concurrently on the first core and the second core (¶ 62, “two threads may be executed on the core, such as to assess if the core suffers a loss in peak performance when co-scheduling multiple software threads on different hardware thread contexts provided by the core. Performance may be measured in instructions executed per unit time”).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to have applied the known technique of selecting, by the virtual machine, a first core and a second core of the virtual machine; executing, by the virtual machine, the machine-readable process concurrently on the first core and the second core, the first core executed on a first thread of the multi-core processing system and the second core executed on a second thread of the multi-core processing system; and determining, by the virtual machine, first execution metrics for the first thread and the second thread, responsive to executing the machine-readable process concurrently on the first core and the second core, as taught by Harris, in the same way to the iteratively executing the machine-readable process, as taught by Wong and Tsirkin. Both inventions are in the field of scoring different multithreading configurations, and combining them would have predictably resulted in “modeling the performance of parallel workloads with differing thread counts and placements,” as indicated by Harris (¶ 2).
Regarding claim 9, Harris teaches: The method of claim 8, wherein the benchmark metrics comprise a benchmark execution duration and wherein the first execution metrics comprise a first execution duration (¶ 76, “the workload may be run with a single thread to get the time t1”), the method further comprising: comparing, by the virtual machine, the first execution duration to the benchmark execution duration (¶ 77, “the execution time recorded at step x (t.sub.x) may be normalized relative to this sequential execution time r.sub.x=t.sub.x/t.sub.1”); and associating, by the virtual machine, the first thread and the second thread as being of the same core of the multi-core processing system (¶ 62, “in some embodiments, two threads may be executed on the core, such as to assess if the core suffers a loss in peak performance when co-scheduling multiple software threads on different hardware thread contexts provided by the core”), responsive to the first execution duration exceeding the benchmark execution duration (¶ 87, “Taking the unknown factors remaining in these two runs burstiness may be defined as the percentage extra time required due to collocation”).
Claims 18 and 19 recite commensurate subject matter as claims 8 and 9. Therefore, they are rejected for the same reasons.
Conclusion
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/JACOB D DASCOMB/ Primary Examiner, Art Unit 2198
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