Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 is objected to because of the following informalities:
Regarding claim 1, variable “N-M” needs to be defined. Note, it is not clear why variable “N-M” is defined in claim 9 and NOT in independent claim 1. Therefore, it is suggested, “N-M is an integer greater than or equal to 1” claimed in claim 9 is deleted and moved to independent claim 1. Alternatively, replacing “N-M stage power amplifiers” with “first stage amplifier”. Note, claim 1 discloses “a final stage amplifier”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim(s) 1-10, 12 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FENG et al. (20160294333), hereafter called FENG.
Regarding claims 1, NAMIE (Fig. 2) discloses a power amplifier circuit, comprising: N-stage power amplifiers (106 and 104) connected in series, provided with an input end receiving a radio frequency (RF) input signal (RF IN) and an output end outputting a RF output signal (RF OUT), in the N-stage power amplifiers, an output end of first stage amplifier (106) and an output end of a final stage amplifier (104) being grounded through their respective harmonic termination/trap filters (110 and 108) read as frequency doubling suppression circuits which are configured to suppress frequency doubling of the N-stage power amplifiers during operation, N being an integer greater than or equal to 2.
Regarding claim 2, wherein suppression circuits (110 and 108) operable as trap circuit.
Regarding claim 3, wherein the frequency doubling suppression circuit comprises at least one of a double frequency suppression circuit (108).
Regarding claim 4, wherein an output end of each stage amplifier in the N-stage power amplifiers (110 and 108) is connected to at least one of the frequency doubling suppression circuits (110 and 108).
Regarding claim 5, wherein output ends of last two stage amplifiers in the N-stage power amplifiers are connected to the frequency doubling suppression circuits (110 and 108) respectively.
Regarding claim 6, wherein frequency doubling suppression circuits (110 and 108) connected to output ends of at least two stage power amplifiers have the same structure.
Regarding claim 7, wherein each of the frequency doubling suppression circuits comprises at least an inductor-capacitor (LC) series circuit or an LC parallel circuit.
Regarding claim 8, wherein a resonant frequency of at least one of frequency doubling suppression circuits connected to at least two stage power amplifiers is adjustable (switch capacitor(s)).
Regarding claim 9, wherein the frequency doubling suppression circuit with adjustable resonant frequency comprises a plurality of parallel branches, an end of each of the plurality of parallel branches is connected to the output end of the N-M stage power amplifiers in the N-stage power amplifiers, and another end of each of the plurality of parallel branches is grounded, the frequency doubling suppression circuit is adjusted by turning on or off the plurality of parallel branches by switch (S1-Sn).
Regarding claim 10, wherein the frequency doubling suppression circuit with adjustable resonant frequency further comprises an inductor (L0/L0’), each of the plurality of parallel branches comprises at least one capacitor provided with a first end connected to the output end of the N-M stage power amplifiers and a second end connected to a first end of the inductor, a second end of the inductor is grounded.
Regarding claims 12 and 13, wherein the power amplifier can be formed on a chip, see para.[0089].
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, prior art(s) does not disclose the frequency doubling suppression circuit with adjustable resonant frequency further comprises a control switch, the control switch is a single-pole multi-throw switch, and is provided with a plurality of first ends connected to the second end of the at least one capacitor, and a second end connected to the first end of the inductor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843