DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/06/2024 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Objections
Claim 14 is objected to because of the following informalities: Claim 14 recites the limitation “according to claim 11” in line 1 of the claim. This appears to mean “according to claim 13” in order to avoid antecedent basis issues. Appropriate correction is required.
Claim 15 is objected to because of the following informalities: Claim 14 recites the limitation “according to claim 11” in line 1 of the claim. This appears to mean “according to claim 13” in order to avoid antecedent basis issues. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-9, 11-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi et al. U.S. Patent Application 2013/0107075 (hereinafter “Kobayashi”).
Regarding claim 1, Kobayashi teaches an electronic device (refer to figures 1, 2A, and 2B), comprising: a first substrate structure (i.e. first member 308)(figs.1 and 2A), comprising a first substrate (i.e. first substrate 101)(fig.1); a plurality of electronic elements (i.e. pixel part 301A)(fig.2A), disposed on the first substrate (implicit)(refer to fig.2A); and a second substrate structure (i.e. second member 309)(figs.1 and 2B), coupled to the first substrate structure (implicit)(refer to fig.1) and comprising: a second substrate (i.e. second substrate 121)(fig.1); a protection circuit (i.e. protection diode circuit 315)(figs.1 and 2B), disposed on the second substrate (implicit)(refer to figs.1 and 2B); a driving circuit (refer to vertical scanning circuit VSR, horizontal scanning circuit HSR, and readout circuit RC)(fig.2B)(refer also to amplification transistors 306 and reset transistors 307)(fig.3), disposed on the second substrate (implicit)(refer to fig.2B), and configured to drive at least a part of the plurality of electronic elements (implicit)(refer to [0038] and [0039]); and a bonding pad (i.e. connection portion 314B)(figs.1 and 2B), disposed on the second substrate (implicit)(refer to figs.1 and 2B), wherein the protection circuit is respectively coupled to the bonding pad and the driving circuit (implicit)(refer to diode 315)(fig.2B).
Regarding claim 7, Kobayashi teaches the electronic device according to claim 1, wherein the protection circuit is closer to the bonding pad than the driving circuit (implicit)(refer to protection diode circuit 315)(fig.2B).
Regarding claim 8, Kobayashi teaches the electronic device according to claim 1, wherein the protection circuit comprises a diode, a transistor, a guard ring or a capacitor (refer to protection diode circuit 315)(fig.10A).
Regarding claim 9, Kobayashi teaches the electronic device according to claim 1, wherein the second substrate structure further comprises: a stress release layer (i.e. inter-layer insulating film 127)(fig.1), disposed between the bonding pad and the second substrate (implicit), and a material of the stress release layer at least comprising an organic material (refer to [0070]).
Regarding claim 11, Kobayashi teaches the electronic device according to claim 1, wherein the bonding pad does not overlap the driving circuit (implicit)(refer to connection portion 314B)(fig.1).
Regarding claim 12, Kobayashi teaches the electronic device according to claim 1, wherein the bonding pad comprises a plurality of first bonding pads (refer to pad part 312b)(fig.2b), and the plurality of first bonding pads are arranged on a side of the second substrate (implicit).
Regarding claim 13, Kobayashi teaches the electronic device according to claim 1, wherein the second substrate comprises a center line (inherent)(there is inherently a center axis)(refer also to center line in the figure below)(fig.2B), and the bonding pad comprises at least one first bonding pad (i.e. first bonding pad in the figure below)(fig.2B) and at least one second bonding pad (i.e. second bonding pad in the figure below)(fig.2B), wherein the center line divides the second substrate into a first area and a second area (refer to first area and second area in the figure below)(fig.2B), the at least one first bonding pad is located in the first area (implicit), and the at least one second bonding pad is located in the second area (implicit).
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Regarding claim 14, Kobayashi teaches the electronic device according to claim 13, wherein a position of the at least one first bonding pad is symmetrical to a position of the at least one second bonding pad with respect to the center line (implicit)(refer to fig.2B above).
Regarding claim 15, Kobayashi teaches the electronic device according to claim 13, wherein a number of the at least one first bonding pad is the same as a number of the at least one second bonding pad (implicit)(refer to fig.2B above).
Regarding claim 16, Kobayashi teaches the electronic device according to claim 1, wherein the second substrate structure further comprises: a pixel definition layer (i.e. inter-layer insulating film 127)(fig.1), disposed on the bonding pad and having an opening, wherein the opening exposes a portion of the bonding pad (implicit).
Regarding claim 17, Kobayashi teaches the electronic device according to claim 1, wherein the electronic element comprises a photoelectric element, a pyroelectric element, a piezoelectric element, a sensing element or an antenna element (refer to [0033]).
Regarding claim 18, Kobayashi teaches the electronic device according to claim 1, wherein the protection circuit comprises a node (i.e. node 149)(fig.10A), a diode (i.e. first diode 145)(fig.10A), another diode (i.e. second diode 146)(fig.10A), a high power supply voltage (i.e. VDD)(fig.10A) and a low power supply voltage (i.e. VSS)(fig.10A), and the node is electrically connected to the high power supply voltage and the low power supply voltage through the diode and the another diode respectively (implicit).
Regarding claim 20, Kobayashi teaches the electronic device according to claim 1, wherein the protection circuit is configured to reduce damage caused by electrostatic discharge (refer to [0050]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi as applied to claim 1 above, and further in view of Ruby et al. U.S. Patent No. 4,782,381 (hereinafter “Ruby”).
Regarding claim 2, Kobayashi teaches the electronic device according to claim 1, wherein the second substrate structure further comprises: an insulating layer (i.e. inter-layer insulating film 126)(fig.1), disposed on the second substrate (implicit), and comprising a via hole (refer to vias in the figure below)(fig.1); however, Kobayashi does not teach wherein in a cross-sectional view, a portion of the bonding pad is filled in the via hole. However, Ruby teaches wherein in a cross-sectional view, a portion of the bonding pad is filled in the via hole (refer to via in the figure below)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Kobayashi to include the bonding pad and via construction of Ruby to provide the advantage of using a common, well-known method of creating vias and bonding pads which makes for easier manufacture.
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Regarding claim 3, Kobayashi and Ruby teach the electronic device according to claim 2, wherein in a top view, the bonding pad overlaps the via hole and an overlapping area is formed (implicit)(refer to Kobayashi figure 1 and Ruby figure 1).
Regarding claim 4, Kobayashi and Ruby teach the electronic device according to claim 3, wherein the bonding pad has a bonding area (refer to Ruby bonding area in the figure above)(fig.1) and a non-bonding area (refer to Ruby non-bonding area in the figure above)(fig.1), and the via hole overlaps the non-bonding area (implicit)(refer to Ruby figure 1).
Regarding claim 5, Kobayashi and Ruby teach the electronic device according to claim 4, wherein the second substrate structure further comprises: a metal trace (i.e. Ruby metal trace in the figure above)(fig.1), electrically connected to the bonding pad through the via hole (implicit), wherein the metal trace does not overlap the bonding area (implicit).
Regarding claim 6, Kobayashi and Ruby teach the electronic device according to claim 4, wherein the second substrate structure further comprises: a solder ball (i.e. Ruby solder ball in the figure above)(fig.1)(refer also to Ruby col. 4 lines 39-42), disposed on the bonding area of the bonding pad (implicit)(refer to Ruby solder ball in the figure above)(fig.1)(refer also to Ruby col. 4 lines 39-42).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi.
Regarding claim 10, Kobayashi teaches the electronic device according to claim 9; however, Kobayashi does not teach wherein the bonding pad overlaps the driving circuit. However, it would have been an obvious matter of design choice to have wherein the bonding pad overlaps the driving circuit, since applicant has not disclosed that having the bonding pad overlap the driving circuit solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the bonding pad not overlapping the driving circuit. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Kobayashi to include wherein the bonding pad overlaps the driving circuit to provide the advantage of creating a more compact circuit.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi as applied to claim 1 above, and further in view of Lin U.S. Patent No. 6,025,631 (hereinafter “Lin”).
Regarding claim 19, Kobayashi teaches the electronic device according to claim 1, wherein the protection circuit comprises a node (i.e. node 149)(fig.10A), a device (i.e. diode 145)(fig.10A), another device (i.e. diode 146)(fig.10A), a high power supply voltage (i.e. VDD)(fig.10A) and a low power supply voltage (i.e. VSS)(fig.10A), and the node is electrically connected to the high power supply voltage and the low power supply voltage through the device and the another device respectively (implicit); however, Kobayashi does not teach wherein the device is a transistor and the another device is another transistor. However, Lin teaches wherein the device is a transistor (i.e. p-type CMOS transistor 40)(fig.4) and the another device is another transistor (i.e. n-type CMOS transistor 41)(fig.4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Kobayashi to include the transistors of Lin to provide the advantage of using a well-known alternative ESD circuit to diodes in order to use a type of component that is more easily manufactured in the type of substrate that a thin film transistor would be manufactured in.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838