DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
This Office Action is in response to Applicant’s application 18/467,755 filed on September 15, 2023 in which claims 1 to 20 are pending.
Drawings
The drawings submitted on September 15 2023 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS), filed on September 15, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Notation
References to patents will be in the form of (C: L) where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of (¶ XXXX).
Claim Rejections - 35 USC § 112
Claims 4 and 11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The following limitation the metal sidewall spacer surrounds the dielectric pedestal on all sides
is not described in the specification or drawing. Figure 4 and paragraph 0058 describes the method of forming metal spacers (118) and in the method of making the metal spacers surrounds the side surfaces of the dielectric pedestal (110) and the not all the sides as claimed.
The limitations all sides should be amended to include only side surface because the broadest reason of interpretation of all sides includes top surface and bottom surface.
Therefore, to avoid any 112 issues the following limitation “all sides” should be defined as side surfaces that don’t include the bottom and top surface.
The office interprets the following limitation as side surfaces on the side of the bottom and top surface of the dielectric pedestal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Fox, III (US 2019/0006234 A1; hereinafter “Fox”) in view of Yang et al. (US 2021/0233843 A1; hereinafter “Yang”).
Regarding claim 1, Fox teaches in figure 5 and related text e.g. a vertical antifuse structure comprising:
a metal sidewall spacer (20; Fig.5; ¶ 0009) arranged on a vertical sidewall of a dielectric pedestal (18; Fig.5);
Fox does not teach a fuse dielectric layer on top of the dielectric pedestal; and a conductive element on top of the fuse dielectric layer and directly above the metal sidewall spacer.
However, Yang teaches a fuse dielectric layer (12; Fig.9; ¶ 0023) on top of the dielectric pedestal (14; Fig.9; ¶ 0026); and a conductive element (10, Fig.9; ¶ 0020)) on top of the fuse dielectric layer (10) and directly above the metal sidewall spacer (18L and 16L; the office treats 18L and 16L as one metal spacer).
(Office note: the direction of Figure 9 is used upside down. The figures in the prior art record can be used in any direction as X-axis and Y-axis can rotate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have a fuse dielectric layer on top of the dielectric pedestal; and a conductive element on top of the fuse dielectric layer and directly above the metal sidewall spacer in the device of Fox as taught by Yang for the purpose of having enhanced programming efficiency and highly reliable connection (¶ 0004).
Regarding claim 2, Fox as modified by Yang teaches a conductive line (26; Fig.9; ¶ 0041; 24 can be omitted at ¶ 0048) immediately below and directly contacting a bottommost surface of the metal sidewall spacer (18 can be in direct contact with 26; ¶ 0048).
Regarding claim 3, Fox as modified by Yang teaches wherein an entirety of a bottommost surface of the metal sidewall spacer (the bottom surface of 18) directly contacts a topmost surface of the conductive line (direct contacts the upper surface of 26).
Regarding claim 4, Fox teaches wherein the metal sidewall spacer (20; Fig.4; ¶ 0009) surrounds the dielectric pedestal on all sides
Regarding claim 5, Fox as modified by Young teaches a vertical distance between a topmost surface of the metal sidewall spacer (Young; 16L; Fig.10) and a bottommost surface of the conductive element (10) is equal to a thickness of the fuse dielectric layer (12).
Regarding claim 8, Fox teaches in figure 5 and related text e.g. a vertical antifuse structure comprising:
a metal sidewall spacer (20; Fig.5; ¶ 0009) arranged on a vertical sidewall of a dielectric pedestal (18; Fig.5);
Fox does not teach a conductive element directly above the metal sidewall spacer; and a fuse dielectric layer between and separating the metal sidewall spacer from the conductive element.
However, Yang teaches a conductive element (10, Fig.9; ¶ 0020)) directly above the metal sidewall spacer (18L and 16L; the office treats 18L and 16L as one metal spacer) and a fuse dielectric layer (12; Fig.9; ¶ 0023) between and separating the metal sidewall spacer (18 L and 16L) from the conductive element (10).
(Office note: the direction of Figure 9 is used upside down. The figures in the prior art record can be used in any direction as X-axis and Y-axis can rotate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have a fuse dielectric layer on top of the dielectric pedestal; and a conductive element on top of the fuse dielectric layer and directly above the metal sidewall spacer in the device of Fox as taught by Yang for the purpose of having enhanced programming efficiency and highly reliable connection (¶ 0004).
Regarding claim 9, Fox as modified by Yang teaches a conductive line (26; Fig.9; ¶ 0041; 24 can be omitted at ¶ 0048) immediately below and directly contacting a bottommost surface of the metal sidewall spacer (18 can be in direct contact with 26; ¶ 0048).
Regarding claim 10, Fox as modified by Yang teaches wherein an entirety of a bottommost surface of the metal sidewall spacer (the bottom surface of 18) directly contacts a topmost surface of the conductive line (direct contacts the upper surface of 26).
Regarding claim 11, Fox teaches wherein the metal sidewall spacer (20; Fig.4; ¶ 0009) surrounds the dielectric pedestal on all sides.
Regarding claim 12, Fox as modified by Young teaches a vertical distance between a topmost surface of the metal sidewall spacer (Young; 16L; Fig.10) and a bottommost surface of the conductive element (10) is equal to a thickness of the fuse dielectric layer (12).
Allowable Subject Matter
Claims 15-20 are allowed.
Claims 6, 7, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 is objected to since the prior art does not teach “…wherein the conductive element further comprises another metal sidewall spacer surrounding another dielectric pedestal, wherein a topmost surface of the fuse dielectric layer directly contacts a bottommost surface of the another metal sidewall spacer.”
Claim 7 is objected to since the prior art does not teach “a conductive link in direct contact with and extending between a topmost surface of the metal sidewall spacer and a bottommost surface of the conductive element through the fuse dielectric layer.”
Claim 15 is allowed since the prior art does not teach the following limitations: “…second conductive element directly above the second metal sidewall spacer; and a fuse dielectric layer, the fuse dielectric layer arranged between and separating the first metal sidewall spacer from the first conductive element, and the fuse dielectric layer arranged between and separating the second metal sidewall spacer from the second conductive element.”
The closest prior art reference Wang et al. (US 2008/ 012138 A1) teaches a vertical antifuse structure comprising: a first metal sidewall spacer (102; Fig.9; ¶ 0025) disposed on a vertical sidewall of a first dielectric pedestal (22; Fig.9; ¶ 0025); a first conductive element (142; Fig.9; ¶ 0036) directly above the first metal sidewall spacer (102); a second metal (202) sidewall spacer disposed on a vertical sidewall of a second dielectric pedestal (22; Fig.9). Wang explicitly teaches the fuse dielectric layer (134; Fig.9) formed in one device (150) and does not teach a fuse dielectric layer formed in the second device (200).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mounir S Amer whose telephone number is (571)270-3683. The examiner can normally be reached Monday-Friday 9:00-5:30.
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/Mounir S Amer/ Primary Examiner, Art Unit 2818