DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/05/2026 has been entered.
Application Status
This office action is responsive to the Request for Continued Examination, filed on 01/05/2026 (Foreign Priority Date: 09/20/2022).
This action has been made NON-FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments filed 03/16/2026 have been fully considered but they are not persuasive.
Applicant alleges the following: “It is submitted, however, that the Office has not met its burden of showing that '751 publication discloses "dedicated buffer operable to store early primitive assembly data during operation of the shader and to supply the early primitive assembly data to a late primitive assembly circuit element" and "the early primitive assembly data generator further operable to release the portion of the system cache responsive to completion of storing the early primitive assembly data in the dedicated buffer" as set forth in claim 1… It is submitted, however, that the Office has not met its burden that the '751 discloses "a dedicated buffer operable to store early primitive assembly data during operation of the shader and to supply the early primitive assembly data to a late primitive assembly circuit element responsive to completion of operation of the shader" and "the early primitive assembly data generator further operable to release the portion of the system cache responsive to completion of storing the early primitive assembly data in the dedicated buffer." as set forth in claim 1. Indeed, the Office has not shown how the '751 publication discloses a dedicated buffer in the context of claimed subject matter, let alone a buffer operable to supply early primitive assembly data to a late primitive assembly circuit element responsive to completion of operation of a shader as set forth in claim 1.” The examiner is not persuaded. Langtind discloses the Applicant’s claim language of “a dedicated buffer operable to store in Paragraphs 0027-0031; 0204-0208. Langtind goes on to disclose the Applicant’s claim limitations “early primitive assembly data during operation of the shader” in Figure 3, Item 31; Paragraphs 0011-0016; 0189-0191. Moreover, Langtind’s Figure 3, Item 31; Paragraphs 0011-0016; 0189-0191 discloses the Applicant’s claim limitation of “and to supply the early primitive assembly data to a late primitive assembly circuit element responsive to completion of operation of the shader.” Additionally, Langtind discloses the Applicant’s claim limitation of “wherein the early primitive assembly data generator” in Figure 3, Item 31; Figure 5; Paragraphs 0011-0016; 0189-0191. Further, Langtind discloses “further operable to release the portion of the system cache” in Figure 5; Paragraphs 0229-02331. Moreover, Langtind discloses “responsive to completion of storing the early primitive assembly data in the dedicated buffer” in Figure 5; Paragraphs 0229-0233. Because "applicants may amend claims to narrow their scope, a broad construction during prosecution creates no unfairness to the applicant or patentee." In re ICON Health and Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007) (citing In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004)). Accordingly, the examiner maintains the rejection.
Applicant alleges the following: “Assignee submits that the Office has not shown how the applied documents show a dedicated buffer that is configured to "preserve a processing order as received at an input stage by the input prefetcher" as set forth in claim 18. As such, it is submitted that claim 18 further distinguishes over the applied documents.” The examiner is not persuaded. Langtind discloses the Applicant’s claim limitation of “wherein the dedicated buffer is configured to preserve a processing order” in Paragraphs 0059-0060. Moreover,
Langtind’s Paragraphs 0059- 0060 discloses the Applicant’s claim limitations of “as received at an input stage by the input prefetcher.” MPEP § 2106 states Office personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed Cir. 1997). Accordingly, the examiner maintains the rejection.
Regarding the Applicant remarks pertaining to “Obviousness,” the examiner is not persuaded. In this case, we find such a modification of an old process using a new source of data to be obvious. In KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007), the Supreme Court held that “if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill.” Id. at 417. “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” Id. at 416; see also id. at 417 (“If a person of ordinary skill can implement a predictable variation, § 103 likely bars its patentability.”); In re Schreiber, 128 F.3d 1473, 1477 (Fed. Cir. 1997) (“It is well settled that the recitation of a new intended use for an old product does not make a claim to that old product patentable.” (citations omitted)). The examiner does not find that the evidence shows having “a compressor” to be “uniquely challenging or difficult for one of ordinary skill in the art.” Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 418). Moreover, both references are in the same field of endeavor, such as graphics processing systems. Additionally, the Applicant’s response is merely a citation of case law and fails to provide any explanation of how it is relevant to the examiner’s rejection. MPEP 710.01 discusses applicant responses that fail to point out the examiner’s supposed errors and therefore do not comply with 37 CFR 1.111(b). Accordingly, the obvious rejection is maintained by the examiner.
Applicant alleges the following: “The '086 patent is directed to, among other things, graphics processing. It is submitted, however, that the Office has not shown how the '086 patent discloses or suggest "a dedicated buffer operable to store early primitive assembly data during operation of the shader and to supply the early primitive assembly data to a late primitive assembly circuit element responsive to completion of operation of the shader" and "the early primitive assembly data generator further operable to release the portion of the system cache responsive to completion of storing the early primitive assembly data in the dedicated buffer." As such, it is submitted that the Office has not met its burden of showing that the '086 patent makes up for the deficiencies of the '751 publication in showing all of the subject matter of independent base claims 1 and 10. Accordingly, it is submitted that claims 2 and 11 distinguish over any combination of the '751 publication and '086 patent, proper or otherwise.” The examiner is not persuaded. The Applicant is rehashing arguments already previously addressed above. More specifically, Paragraph 0204 of Langtind recites “At this stage, each (complete) primitive output by the early primitive assembly circuit 31 comprises an identifier for the primitive in the form of a sequence number for the primitive, and a sequence of vertex indices from the input index vertex stream, corresponding to the indices for the vertices to be used for the primitive.” Accordingly, the examiner maintains the rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-10, 12-14 and 17 are rejected under 35 U.S.C. 102(a)(2) as being (a)(2) by Langtind, US 20220245751.
The applied reference has a common Arm Limited with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim 1:
Langtind discloses a primitive assembly circuit (See Langtind Abstract; Paragraph 0031), comprising:
an input prefetcher operable to fetch index data (See Langtind Paragraph 0060) from a portion of a system cache (See Langtind Paragraphs 0080-0082);
an early primitive assembly data generator operable to supply primitive input to a shader (See Langtind Figure 3, Item 31; Paragraphs 0011-0016; 0189-0191);
and a dedicated buffer operable to store (See Langtind Paragraphs 0027-0031; 0204-0208) early primitive assembly data during operation of the shader (See Langtind Figure 3, Item 31; Paragraphs 0011-0016; 0189-0191) and to supply the early primitive assembly data to a late primitive assembly circuit element responsive to completion of operation of the shader (See Langtind Figure 3, Item 31; Paragraphs 0011-0016; 0189-0191),
wherein the early primitive assembly data generator (See Langtind Figure 3, Item 31; Figure 5; Paragraphs 0011-0016; 0189-0191) further operable to release the portion of the system cache (See Langtind Figure 5; Paragraphs 0229-02332) responsive to completion of storing the early primitive assembly data in the dedicated buffer (See Langtind Figure 5; Paragraphs 0229-0233).
Claim 3:
Langtind discloses comprising a presence/absence bitmap to reduce data of culled primitives to a one-bit absence indicator (See Langtind Paragraph 0131).
Claim 4:
Langtind discloses the compressor operable to use a base-and-offset position indicator for a primitive vertex (See Langtind Paragraphs 0027-0031).
Claim 5:
Langtind discloses a substitution table operable to substitute a reduced length identifier for a vertex identifier (See Langtind Figure 5; Paragraphs 0068-0071 and 0230-0232).
Claim 6:
Langtind discloses the early primitive assembly data generator further operable to release an input cache (See Langtind Paragraphs 0080-0082) responsive to completion of storing the early primitive assembly data in the dedicated buffer (See Langtind Paragraphs 0027-0031; 0204-0208).
Claim 7:
Langtind discloses the dedicated buffer being located in a local memory of the primitive assembly circuit (See Langtind Paragraphs 0027-0031; 0204-0208).
Claim 8:
Langtind discloses the shader being an index-driven vertex shader (See Langtind Paragraph 0011).
Claim 9:
Langtind discloses a tiler for partitioning image data into tiles for processing (See Langtind Paragraphs 0150-0151).
Claims 10, and 12-14 and 16:
Claims 10 and 12-14 and 16 are rejected on the same basis as claims 1 and 3-7.
Claim 17:
Claim 17 is rejected on the same basis as claim 1.
Claim 18:
Langtind discloses wherein the dedicated buffer is configured to preserve a processing order (See Langtind Paragraphs 0059-0060) as received at an input stage by the input prefetcher (See Langtind Paragraphs 0059- 0060).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Langtind, US 20220245751 in view of Croxford, US 10964086.
Claim 2:
Langtind disclosed early primitive assembly data generator but failed to explicitly disclose a compressor. However, Croxford disclosed this feature in Column 25, Lines 15-41. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Langtind by the teachings of Croxford in order to enable improved primitive assembly circuit while using a compressor, more effectively (See Croxford Abstract).
As modified:
The combination of Langtind and Croxford discloses the following:
the early primitive assembly data generator further operating a compressor to compress (See Croxford Column 25, Lines 15-41) the early primitive assembly data before storage in the dedicated buffer (See Langtind Paragraphs 0027-0031; 0204-0208).
Claim 11:
Claim 11 is rejected on the same basis as claim 2.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11288850 discloses when it is determined that an index corresponds to the start of a complete primitive, the method comprises (the primitive assembly circuit) determining the position of that complete primitive in an output sequence of primitives, wherein determining the position in the output sequence of primitives for an identified complete primitive comprises using a prefix sum to determine the number of complete primitives in the sequence of indices up to that complete primitive. For instance, by performing the prefix sum over the entire set of indices is thus possible to determine a count of the total number of primitives in the set of indices. Or, by modifying the function to re-set the count of primitives at each primitive restart, it would also be possible to determine a count of the number of primitives in each sequence of indices (i.e. since the most recent primitive restart).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEREE N BROWN whose telephone number is (571)272-4229. The examiner can normally be reached M-F 5:30-2:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SAID BROOME can be reached at (571) 272-2931. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEREE N BROWN/Primary Examiner, Art Unit 2612 March 30, 2026
1 Langtind in Figure 5; Paragraphs 0229-0233 discloses “as shown in FIG. 5, the vertex cache 45 includes a vertex loader circuit 62 that will fetch the vertices (the vertex attributes) from where they are stored and load them into the vertex cache 45, together with a vertex output circuit 63 for outputting vertices from the cache to the late primitive assembly circuit (stage) 33”.
2 Langtind in Figure 5; Paragraphs 0229-0233 discloses “as shown in FIG. 5, the vertex cache 45 includes a vertex loader circuit 62 that will fetch the vertices (the vertex attributes) from where they are stored and load them into the vertex cache 45, together with a vertex output circuit 63 for outputting vertices from the cache to the late primitive assembly circuit (stage) 33”.
Prosecution Insights