DETAILED ACTION
Claims 1 – 10 have been presented for examination.
This office action is in response to submission of the application on 09/15/2023.
The instant Office Action relies on Wang et al. (US 2022/0114317) which is cited on the IDS.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regard to claim 5 (and similarly claim 10), it recites “finding whether there is a voltage having a value greater than a value of the current in a voltage after an area in which the current decreases”. It is unclear how a voltage can be greater than a value of a current, or how a current can be in a voltage. The limitation is interpreted for examination purposes as noting an area of negative differential resistance (see the instant application Paragraph 72 “Referring to FIGS. 2, SA, and SB, the NDR may be analyzed by the LUT 140. In the LUT 140, there may be a section in which the current decreases even though the voltage increases. The section is called the NDR section.”).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 – 10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., an abstract idea) without significantly more.
Independent claim 1 recites at Step 1 a statutory category (i.e. a process) method of processing a neural network model for a circuit simulator, comprising: generating a lookup table (LUT) using size information of a semiconductor device included in the source file and parameters included in the neural network file. At Step 2A, Prong I the recited limitations, alone or in combination, amount to steps that, under its broadest reasonable interpretation, cover performance of the limitations in the mind in combination with using a pen and paper (see MPEP 2106.04(a)(2)(III)). For example, the “generating” amounts to modeling actions recited at a high-level of generality requiring no more than judgement and evaluations. Accordingly, the claim recites an abstract idea.
At Step 2A, Prong II this judicial exception is not integrated into a practical application since the claimed invention further claims: reading a source file input to a circuit simulator; reading a neural network file when the source file is read. The “reading” amounts to insignificant data gathering since it is recited at a high-level of generality, and since the “generating” step relies on the received elements in a generic manner (see MPEP 2106.04(d)). The claim is directed to an abstract idea.
At Step 2B the claim does not recite additional elements that, alone or in an ordered combination, are sufficient to amount to significantly more than the judicial exception. The recited “reading” covers well-understood, routine, and conventional activity since it is generic and covers receiving data by any electronics means (see MPEP 2106.05(d)(II) “i. Receiving or transmitting data over a network”). Considering the additional elements in combination does not add anything more than when considering them individually since the “reading” requires no more than generic computer functions. For at least these reasons, the claim is not patent eligible.
Dependent claim 2 – 5 recite(s) at Step 1 the same statutory category as the parent claim(s), and further recite(s): Claim 3 wherein the LUT is not generated when the source file is not read. Claim 4 wherein the generating of the LUT includes: confirming the parameters of the neural network file according to the request signal; confirming the size information of the semiconductor device; Claim 5 analyzing whether there is a section in which a current decreases when a bias voltage increases in the generated LUT; finding whether there is a voltage having a value greater than a value of the current in a voltage after an area in which the current decreases, when there is a section in which the current decreases as the bias voltage increases; and finding a first current value at a voltage at which the current starts to decrease and a second current value greater than the first current value at the voltage after the area in which the current decreases, when there is the voltage having the value greater than the value of the current, and connecting the first current value to the second current value. At Step 2A, Prong I the recited limitations, alone or in combination, amount to steps that, under its broadest reasonable interpretation, cover performance of the limitations in the mind in combination with using a pen and paper (see MPEP 2106.04(a)(2)(III)). For example, the “is not generated when” conditionally performs the parent claim “generating” and does not exclude its performance in the broadest reasonable interpretation. The “confirming” and “analyzing” and “finding” require no more than judgements and evaluations based on observations to reasonably perform. Accordingly, the claim recites an abstract idea.
At Step 2A, Prong II this judicial exception is not integrated into a practical application since the claimed invention further claims: Claim 2 wherein the LUT is stored in a volatile memory; Claim 4 wherein the generating of the LUT includes: receiving a request signal for generating the LUT from the circuit simulator; allocating a storage space for the parameters to a volatile memory; allocating a storage space for the size information of the semiconductor device to the volatile memory; and allocating a storage space for the LUT to the volatile memory. For example, the “receiving” amounts to insignificant data gathering since it is recited at a high-level of generality, and since the “confirming” step relies on the received elements in a generic manner (see MPEP 2106.04(d)). The “allocating a storage space” amounts to insignificant data outputting since it does not more than directly enable the outputting of specific data. The claim is directed to an abstract idea.
At Step 2B the claim(s) do not recite additional elements that, alone or in an ordered combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the “receiving” and “allocating a storage space” amount(s) to insignificant data gathering. Considering the additional elements in combination does not add anything more than when considering them individually since the “receiving” and “allocating a storage space” requires no more than generic computer functions. For at least these reasons, the claim(s) are not patent eligible.
Independent claim 6 recites at Step 1 a statutory category (i.e. a machine) device for processing a neural network model for a circuit simulator, comprising: generate an LUT using size information of a semiconductor device included in the source file and parameters included in the neural network file. At Step 2A, Prong I the recited limitations, alone or in combination, amount to steps that, under its broadest reasonable interpretation, cover performance of the limitations in the mind in combination with using a pen and paper (see MPEP 2106.04(a)(2)(III)). For example, the “generate” amounts to modeling actions recited at a high-level of generality requiring no more than judgement and evaluations. Accordingly, the claim recites an abstract idea.
At Step 2A, Prong II this judicial exception is not integrated into a practical application since the claimed invention further claims: a processor configured to execute instructions; and a volatile memory configured to store the instructions, wherein the instructions are implemented to implement the steps; read a source file input to a circuit simulator; read a neural network file when the source file is read. The “processor” and “volatile memory” are recited at a high-level of generality such that they amount to no more than mere application of the judicial exception using generic computer components which does not amount to an improvement in computer functionality (see MPEP 2106.04(a)(I)). The “read” amounts to insignificant data gathering since it is recited at a high-level of generality, and since the “generating” step relies on the received elements in a generic manner (see MPEP 2106.04(d)). The claim is directed to an abstract idea.
At Step 2B the claim does not recite additional elements that, alone or in an ordered combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the recited “processor” and “volatile memory” amount to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The recited “read” covers well-understood, routine, and conventional activity since it is generic and covers receiving data by any electronics means (see MPEP 2106.05(d)(II) “i. Receiving or transmitting data over a network”). Considering the additional elements in combination does not add anything more than when considering them individually since the “read” requires no more than generic computer functions. For at least these reasons, the claim is not patent eligible.
Dependent claim 7 – 10 recite(s) at Step 1 the same statutory category as the parent claim(s), and further recite(s): Claim 8 wherein the LUT is not generated when the source file is not read. Claim 9 wherein the generating of the LUT includes: confirm the parameters of the neural network file according to the request signal; confirm the size information of the semiconductor device; Claim 10 analyze whether there is a section in which a current decreases when a bias voltage increases in the generated LUT; find whether there is a voltage having a value greater than a value of the current in a voltage after an area in which the current decreases, when there is a section in which the current decreases as the bias voltage increases; and find a first current value at a voltage at which the current starts to decrease and a second current value greater than the first current value at the voltage after the area in which the current decreases, when there is the voltage having the value greater than the value of the current, and connecting the first current value to the second current value. At Step 2A, Prong I the recited limitations, alone or in combination, amount to steps that, under its broadest reasonable interpretation, cover performance of the limitations in the mind in combination with using a pen and paper (see MPEP 2106.04(a)(2)(III)). For example, the “is not generated when” conditionally performs the parent claim “generate” and does not exclude its performance in the broadest reasonable interpretation. The “confirm” and “analyze” and “find” require no more than judgements and evaluations based on observations to reasonably perform. Accordingly, the claim recites an abstract idea.
At Step 2A, Prong II this judicial exception is not integrated into a practical application since the claimed invention further claims: Claim 7 wherein the LUT is stored in a volatile memory; Claim 9 wherein the generating of the LUT includes: receive a request signal for generating the LUT from the circuit simulator; allocate a storage space for the parameters to a volatile memory; allocate a storage space for the size information of the semiconductor device to the volatile memory; and allocate a storage space for the LUT to the volatile memory. For example, the “receive” amounts to insignificant data gathering since it is recited at a high-level of generality, and since the “confirm” step relies on the received elements in a generic manner (see MPEP 2106.04(d)). The “allocate a storage space” amounts to insignificant data outputting since it does not more than directly enable the outputting of specific data. The claim is directed to an abstract idea.
At Step 2B the claim(s) do not recite additional elements that, alone or in an ordered combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the “receive” and “allocate a storage space” amount(s) to insignificant data gathering. Considering the additional elements in combination does not add anything more than when considering them individually since the “receive” and “allocate a storage space” requires no more than generic computer functions. For at least these reasons, the claim(s) are not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 3 and 6 - 8are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. US 2022/0114317 (henceforth “Wang (317)”) in view of Son et al. (US 2020/0012757) (henceforth “Son (757)”). Wang (317) and Son (757) are analogous art because they solve the same problem of circuit simulation, and because they are from the same field of endeavor of modeling circuits.
With regard to claim 1, Wang (317) teaches a method of processing a neural network model for a circuit simulator, comprising: (Abstract a neural network is trained for use in combination with a circuit simulator)
reading a source file input to a circuit simulator; reading a neural network file when the source file is read; and (Paragraph 87 neural network file is used in combination with a circuit simulation file, where both would need to be read when performing computations (when the source file is read) “(The parameters may be stored in the same file as the equations or in a different file from the equations.) The resulting model, implemented in the programming language of the simulator, takes the inputs such as voltage biases and device instance parameters from the circuit simulator, performs internal computation based on the neural network parameters, and outputs, e.g., the terminal currents and charges of the device to the circuit simulator.”)
generating circuit simulations using size information of a semiconductor device included in the source file and parameters included in the neural network file. (Paragraph 61 input parameters from the files comprise W of transistor (size information in source file) “the input parameters 212 include two types … device instance parameters (for a typical FET, this includes gate length L, FET width W, temperature T, etc.).”, and Paragraph 56 neural network uses size information of transistor (using parameters included in the neural network file) “The neural network model 102 can be operated to process a plurality of transistor characteristics … a gate length L of the transistor (or simulated transistor), a gate width W of the transistor (or simulated transistor),”)
Wang (317) does not appear to explicitly disclose: that the generating is a lookup table (LUT).
However, Son (757) teaches:
generating a lookup table (LUT) from circuit simulations using information and parameters included in a source model. (Paragraph 85 and Figure 5 the circuit simulation model from Wang (317) including the source files can be used to generate a LUT “In the pre-simulation process, a spice simulation for the digital circuit 1 is performed using a spice model corresponding to an actual manufacturing process” Figure 9
PNG
media_image1.png
187
479
media_image1.png
Greyscale
)
It would have been obvious to one of ordinary skill in the art to combine the method of simulating a circuit comprising a neural network and device parameters disclosed by Wang (317) with the method of generating a LUT based on circuit simulations disclosed by Son (757). One of ordinary skill in the art would have been motivated to make this modification in order to reduce circuit simulation time (Son (757) Paragraph 4 “Accordingly, there is a demand for a technique of efficiently reducing a simulation time for a digital circuit”).
With regard to claim 6, Wang (317) teaches a device for processing a neural network model for a circuit simulator, comprising: a processor configured to execute instructions; and a volatile memory configured to store the instructions, wherein the instructions are implemented to: (Abstract a neural network is trained for use in combination with a circuit simulator, and Figure 10 computer system)
read a source file input to a circuit simulator; read a neural network file when the source file is read; and (Paragraph 87 neural network file is used in combination with a circuit simulation file, where both would need to be read when performing computations (when the source file is read) “(The parameters may be stored in the same file as the equations or in a different file from the equations.) The resulting model, implemented in the programming language of the simulator, takes the inputs such as voltage biases and device instance parameters from the circuit simulator, performs internal computation based on the neural network parameters, and outputs, e.g., the terminal currents and charges of the device to the circuit simulator.”)
generate circuit simulations using size information of a semiconductor device included in the source file and parameters included in the neural network file. (Paragraph 61 input parameters from the files comprise W of transistor (size information in source file) “the input parameters 212 include two types … device instance parameters (for a typical FET, this includes gate length L, FET width W, temperature T, etc.).”, and Paragraph 56 neural network uses size information of transistor (using parameters included in the neural network file) “The neural network model 102 can be operated to process a plurality of transistor characteristics … a gate length L of the transistor (or simulated transistor), a gate width W of the transistor (or simulated transistor),”)
Wang (317) does not appear to explicitly disclose: that the generating is a lookup table (LUT).
However, Son (757) teaches:
generate a lookup table (LUT) from circuit simulations using information and parameters included in a source model. (Paragraph 85 and Figure 5 the circuit simulation model from Wang (317) including the source files can be used to generate a LUT “In the pre-simulation process, a spice simulation for the digital circuit 1 is performed using a spice model corresponding to an actual manufacturing process” Figure 9
PNG
media_image1.png
187
479
media_image1.png
Greyscale
)
It would have been obvious to one of ordinary skill in the art to combine the method of simulating a circuit comprising a neural network and device parameters disclosed by Wang (317) with the method of generating a LUT based on circuit simulations disclosed by Son (757). One of ordinary skill in the art would have been motivated to make this modification in order to reduce circuit simulation time (Son (757) Paragraph 4 “Accordingly, there is a demand for a technique of efficiently reducing a simulation time for a digital circuit”).
With regard to claim 2, Wang (317) in view of Son (757) teaches all the elements of the parent claim 1, and further teaches:
wherein the LUT is stored in a memory. (Son (757) Paragraph 124 “If each of the LUT 20 and the control circuit 30 is implemented as a software module, the software modules for the LUT 20 and the control circuit 30 may be stored in a storage medium together with or separately from the software module for the model circuit 1”)
in a volatile memory (Wang (317) “For example, memory 1810 may include one or more volatile devices such as random access memory (RAM).”)
It would have been obvious to one of ordinary skill in the art to combine the method of simulating a circuit comprising a neural network and device parameters disclosed by Wang (317) with the method of storing a LUT based on circuit simulations disclosed by Son (757). One of ordinary skill in the art would have been motivated to make this modification in order to reduce circuit simulation time (Son (757) Paragraph 4 “Accordingly, there is a demand for a technique of efficiently reducing a simulation time for a digital circuit”).
With regard to claim 3, Wang (317) in view of Son (757) teaches all the elements of the parent claim 1, and further teaches: wherein the LUT is not generated when the source file is not read. (Wang (317) Paragraph 87 the circuit simulation reads from the input files, where not reading the files precludes performing the normal operation of the circuit simulation (when the source file is not read))
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (317) in view of Son (757), and further in view of Khandelwal et al. (WO 2022/232680) (henceforth “Khandelwal (680)”). Wang (317) in view of Son (757) and Khandelwal (680) are analogous art because they solve the same problem of circuit simulation, and because they are from the same field of endeavor of modeling circuits.
With regard to claim 4 and 9, Wang (317) in view of Son (757) teaches all the elements of the parent claim 1 and 6, and further teaches wherein the generating of the LUT includes:
receiving a request signal for generating the LUT from the circuit simulator; (Son (757) Paragraph 26 a simulation device controls the LUT (receiving a request signal) which is generated in accordance with simulation operations (from the circuit simulator) “In this embodiment, the simulation device further includes a control circuit 30 for controlling the model circuit 10 and the LUT 20 to perform a simulation operation”)
confirming the parameters of the neural network file according to the request signal; (Wang (317) Paragraph 87 a neural network is conditionally utilized (confirming parameters of the neural network) after a simulation (according to request signal) “If the fitting was found to be sufficiently accurate in operation 330, then in operation 360, the computing system converts the trained neural network model into circuit simulation code such as the Verilog-A hardware description language (HDL) or Common Model Interface (CMI) for use with the Cadence® Spectre® Circuit Simulator”)
allocating a storage space for the parameters to a memory; allocating a storage space for the size information of the semiconductor device to the volatile memory; and allocating a storage space for the LUT to the volatile memory. (Son (757) Paragraph 71 – 72 operation parameters of the circuit are stored in a table “FIGS. 7 and 8 show tables for storing control signals and operation parameters provided to the model circuit 10 of FIG. 2 for each index in FIG. 6. Hereinafter, the tables shown in FIGS. 7 and 8 may be referred to as third tables 23 and 23-1, respectively.”, and Paragraph 81 various tables can be stored in the LUT, where storing the parameters of Wang (317) can be performed with wholly predictable results “In this embodiment, the LUT 20 may include the first table 21, the second table 22, and the third table 23 or 23-1 described above”)
in a volatile memory (Wang (317) “For example, memory 1810 may include one or more volatile devices such as random access memory (RAM).”)
Wang (317) in view of Son (757) does not appear to explicitly disclose: confirming the size information of the semiconductor device.
However, Khandelwal (680) teaches:
confirming a size information of a semiconductor device; (Paragraph 67 a user indicates the process technology, where the user would not knowingly input a false process technology (confirming) “the indication may be input by a user and/or extracted from the first data object. In certain embodiments, technique 800 may identify the first process technology from the first data object representing an original circuit 802,”, and Paragraph 41 process technology includes size information “Generally, process technology nodes refer to a size of a transistor gate length of a particular semiconductor manufacturing process technology”)
It would have been obvious to one of ordinary skill in the art to combine the method of simulating a circuit comprising a neural network and device parameters disclosed by Wang (317) in view of Son (757) with the method of indicating process technology for circuit simulations disclosed by Khandelwal (680). One of ordinary skill in the art would have been motivated to make this modification in order to desirably simulate circuit designs (Khandelwal (680) Abstract “A technique for designing circuits including receiving a data object”).
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (317) in view of Son (757), and further in view of Yang, X. “MEMRISTOR BASED NEURAL NETWORKS: FEASIBILITY, THEORIES AND APPROACHES” (henceforth “Yang (Thesis)””). Wang (317) in view of Son (757) and Yang (Thesis) are analogous art because they solve the same problem of circuit simulation, and because they are from the same field of endeavor of modeling circuits.
With regard to claim 5 and 10, Wang (317) in view of Son (757) teaches all the elements of the parent claim 1 and 6, and does not appear to explicitly disclose: analyzing whether there is a section in which a current decreases when a bias voltage increases in the generated LUT; finding whether there is a voltage having a value greater than a value of the current in a voltage after an area in which the current decreases, when there is a section in which the current decreases as the bias voltage increases; and finding a first current value at a voltage at which the current starts to decrease and a second current value greater than the first current value at the voltage after the area in which the current decreases, when there is the voltage having the value greater than the value of the current, and connecting the first current value to the second current value.
However, Yang (Thesis) teaches:
analyzing whether there is a section in which a current decreases when a bias voltage increases in a generated LUT; finding whether there is a voltage having a value greater than a value of the current in a voltage after an area in which the current decreases, when there is a section in which the current decreases as the bias voltage increases; and finding a first current value at a voltage at which the current starts to decrease and a second current value greater than the first current value at the voltage after the area in which the current decreases, when there is the voltage having the value greater than the value of the current, and connecting the first current value to the second current value. (Figure 16 voltage vs current shows negative differential resistance regions which are instantly identified by looking at the graph (connecting the first current value to the second current value)
PNG
media_image2.png
354
372
media_image2.png
Greyscale
, and Page 47 the voltages and related currents can be represented using a LUT (in a generated LUT) “A general solution to programming a memristor to a specific value is the use of a lookup table which contains the corresponding voltage and duration required.”)
It would have been obvious to one of ordinary skill in the art to combine the method of simulating a circuit comprising a neural network and device parameters disclosed by Wang (317) in view of Son (757) with the viewing and interpretation of negative differential resistance areas disclosed by Yang (Thesis). One of ordinary skill in the art would have been motivated to make this modification in order to desirably operate neural networks comprising a memresitor (Yang (Thesis) Abstract “Memristor-based neural networks refer to the utilisation of memristors, the newly emerged nanoscale devices, in building neural networks”).
With regard to the prior art rejection(s), any cited portion of the relied upon reference(s), either by pointing to specific sections or as quotations, is intended to be interpreted in the context of the reference(s) as a whole as would be understood by one of ordinary skill in the art. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention since the entire reference is considered to provide disclosure relating to the cited portions. Further, the claims and only the claims form the metes and bounds of the invention. Office personnel are to give the claims their broadest reasonable interpretation in light of the supporting disclosure. Unclaimed limitations appearing in the specification are not read into the claim. Prior art was referenced using terminology familiar to one of ordinary skill in the art. Such an approach is broad in concept and can be either explicit or implicit in meaning. Examiner’s notes are provided with the cited references to assist the applicant to better understand how the examiner interprets the applied prior art. Such comments are entirely consistent with the intent and spirit of compact prosecution.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFRED H. WECHSELBERGER whose telephone number is (571)272-8988. The examiner can normally be reached M - F, 10am to 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Emerson Puente can be reached at 571-272-3652. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALFRED H. WECHSELBERGER/ExaminerArt Unit 2187
/ANDRE PIERRE LOUIS/Primary Patent Examiner, Art Unit 2187 August 25, 2026
Prosecution Insights