DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities: It appears that the claim language “at least one the first heat dissipation channel” should be changed to “at least one first heat dissipation channel” and the claim language “at least one the second heat dissipation channel” should be changed to “at least one second heat dissipation channel.” Appropriate correction is required.
Claims 19 and 20 are objected to because of the following informalities: It appears that the claim language “wherein the forming” should be changed to “wherein forming.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-9, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fong et al (US 2018/0082989).
Regarding Claim 1, Fong et al discloses a memory (memory devices [0014] Fig 1), comprising: a first semiconductor structure (shown in annotated Fig 1) and a second semiconductor structure (shown in annotated Fig 1) that are bonded to each other (shown in annotated Fig 1),
wherein the first semiconductor structure (shown in annotated Fig 1) comprises a first dielectric layer (inter-layer structures with high thermal conductivity (and low electrical conductivity) [0199] and may be SiO2, SiC, or Al2O3, [0200] shown in annotated Fig 1) and a first conductive pillar (inter-layer metal connections [0036] shown in annotated Fig 1) located in the first dielectric layer (shown in annotated Fig 1),
the second semiconductor structure (shown in annotated Fig 1) comprises a second dielectric layer (inter-layer structures with high thermal conductivity (and low electrical conductivity) [0199] and may be SiO2, SiC, or Al2O3, [0200] shown in annotated Fig 1) and a second conductive pillar (inter-layer metal connections [0036] shown in annotated Fig 1) located in the second dielectric layer (shown in annotated Fig 1), and
the second conductive pillar (shown in annotated Fig 1) is connected with the first conductive pillar (shown in annotated Fig 1); and
a heat dissipation channel (coolant flow channels [0062] shown in annotated Fig 1) located in at least one of the first dielectric layer (shown in annotated Fig 1) or the second dielectric layer (shown in annotated Fig 1),
wherein the heat dissipation channel (shown in annotated Fig 1) is disposed as being spaced apart (shown in annotated Fig 1) from at least one of the first conductive pillar (shown in annotated Fig 1) or the second conductive pillar (shown in annotated Fig 1).
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Regarding Claim 2, Fong et al discloses the limitations of claim 1 as explained above. Fong et al further discloses
wherein the heat dissipation channel (shown in annotated Fig 1) comprises: a first heat dissipation channel (shown in annotated Fig 1) located in the first dielectric layer (shown in annotated Fig 1) and disposed as being spaced apart from the first conductive pillar (shown in annotated Fig 1); and
a second heat dissipation channel (shown in annotated Fig 1) located in the second dielectric layer (shown in annotated Fig 1) and disposed as being spaced apart from the second conductive pillar (shown in annotated Fig 1),
wherein the second heat dissipation channel (shown in annotated Fig 1) is communicated with the first heat dissipation channel (shown in annotated Fig 1).
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Regarding Claim 3, Fong et al discloses the limitations of claim 2 as explained above. Fong et al further discloses
wherein: the first semiconductor structure (shown above in annotated Fig 1) comprises a plurality of the first conductive pillars (shown above in annotated Fig 1);
the second semiconductor structure (shown above in annotated Fig 1) comprises a plurality of the second conductive pillars (shown above in annotated Fig 1);
the heat dissipation channel (shown above in annotated Fig 1) comprises: at least one first heat dissipation channel (shown above in annotated Fig 1) located between two adjacent ones the plurality of the first conductive pillars (shown above in annotated Fig 1); and at least one second heat dissipation channel (shown above in annotated Fig 1) located between two adjacent ones of the plurality of the second conductive pillars (shown above in annotated Fig 1).
Regarding Claim 4, Fong et al discloses the limitations of claim 3 as explained above. Fong et al further discloses
wherein the heat dissipation channel (shown in annotated Fig 1) further comprises:
a third heat dissipation channel (shown in annotated Fig 1) located in the first dielectric layer (shown in annotated Fig 1) and between two adjacent ones of the first conductive pillars (shown in annotated Fig 1),
wherein an extension direction (shown in annotated Fig 1) of the third heat dissipation channel (shown in annotated Fig 1) intersects an extension direction (shown in annotated Fig 1) of the first heat dissipation channel (shown in annotated Fig 1); and
a fourth heat dissipation channel (shown in annotated Fig 1) located in the second dielectric layer (shown in annotated Fig 1) and between two adjacent ones of the second conductive pillars (shown in annotated Fig 1),
wherein the fourth heat dissipation channel (shown in annotated Fig 1) is communicated with the third heat dissipation channel (shown in annotated Fig 1), and
an extension direction (shown in annotated Fig 1) of the fourth heat dissipation channel intersects an extension direction (shown in annotated Fig 1) of the second heat dissipation channel (shown in annotated Fig 1).
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Regarding Claim 6, Fong et al discloses the limitations of claim 1 as explained above. Fong et al further discloses
wherein the heat dissipation channel (shown in annotated Fig 1) comprises a gap (shown in annotated Fig 1 (the examiner notes that a gap may be filled with material and still be considered a gap) or a plastic molding dielectric.
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Regarding Claim 7, Fong et al discloses a memory (memory devices [0014] Fig 1), comprising: a first semiconductor structure (shown in annotated Fig 1) and a second semiconductor structure (shown in annotated Fig 1) that are bonded to each other (shown in annotated Fig 1),
wherein the first semiconductor structure (shown in annotated Fig 1) comprises a first dielectric layer (inter-layer structures with high thermal conductivity (and low electrical conductivity) [0199] and may be SiO2, SiC, or Al2O3, [0200] shown in annotated Fig 1) and a first conductive pillar (inter-layer metal connections [0036] shown in annotated Fig 1) partially located in the first dielectric layer (shown in annotated Fig 1),
the second semiconductor structure (shown in annotated Fig 1) comprises a second dielectric layer (inter-layer structures with high thermal conductivity (and low electrical conductivity) [0199] and may be SiO2, SiC, or Al2O3, [0200] shown in annotated Fig 1) and a second conductive pillar (inter-layer metal connections [0036] shown in annotated Fig 1) partially located in the second dielectric layer (shown in annotated Fig 1), and
the second conductive pillar (shown in annotated Fig 1) is connected with the first conductive pillar (shown in annotated Fig 1); and
a filling layer (shown in annotated Fig 1) located between the first dielectric layer (shown in annotated Fig 1) and the second dielectric layer (shown in annotated Fig 1),
wherein a connection face (shown in annotated Fig 1) of the first conductive pillar (shown in annotated Fig 1) and the second conductive pillar (shown in annotated Fig 1) is located in the filling layer (shown in annotated Fig 1).
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Regarding Claim 8, Fong et al discloses the limitations of claim 7 as explained above. Fong et al further discloses
wherein the first conductive pillar (shown in annotated Fig 1) comprises a first conductive sub-pillar (shown in annotated Fig 1) and a second conductive sub-pillar (shown in annotated Fig 1), the first conductive sub-pillar (shown in annotated Fig 1) is located in the first dielectric layer (shown in annotated Fig 1), and the second conductive sub-pillar (shown in annotated Fig 1) is located in the filling layer (shown in annotated Fig 1).
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Regarding Claim 9, Fong et al discloses the limitations of claim 8 as explained above. Fong et al further discloses
wherein the second conductive pillar (shown in annotated Fig 1) comprises a third conductive sub-pillar (shown in annotated Fig 1) and a fourth conductive sub-pillar (shown in annotated Fig 1), the third conductive sub-pillar (shown in annotated Fig 1) is located in the second dielectric layer (shown in annotated Fig 1), and the fourth conductive sub-pillar (shown in annotated Fig 1) is located in the filling layer (shown in annotated Fig 1).
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Regarding Claim 14, Fong et al discloses the limitations of claim 9 as explained above. Fong et al further discloses
wherein the forming the heat dissipation channel (shown in annotated Fig 1) comprises:
forming a first heat dissipation channel (shown in annotated Fig 1) located in the first dielectric layer (shown in annotated Fig 1) and disposed as being spaced apart from the first conductive pillar (shown in annotated Fig 1); and
forming a second heat dissipation channel (shown in annotated Fig 1) located in the second dielectric layer (shown in annotated Fig 1) and disposed as being spaced apart from the second conductive pillar (shown in annotated Fig 1),
wherein the second heat dissipation channel (shown in annotated Fig 1) is communicated with the first heat dissipation channel (shown in annotated Fig 1).
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It should be noted that Claim 9, from which Claim 14 depends, is drawn to a device and the limitation "formed depending on the presence or absence" is a process limitation. It has been held that a "product by process claim" is directed to the product per se, no matter how actually it is made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Fong et al (US 2018/0082989) in view of Lee et al (US 2023/0307318).
Fong et al discloses the limitations of claim 1 as explained above. Fong et al does not disclose
wherein the heat dissipation channel comprises a plurality of annular sub-channels connected sequentially;
the memory comprises first regions located inside the annular sub-channels and second regions located outside the annular sub-channels,
wherein at least one of: the connected first conductive pillar and second conductive pillar are located in the first regions; and
the connected first conductive pillar and second conductive pillar are located in the second regions.
Lee et al, in the related art of semiconductor devices that include semiconductor packaging for memory chips, discloses
wherein the heat dissipation channel (cooling channel 710 [0061] Fig 10) comprises a plurality of annular sub-channels (apertures 720 [0061]) connected sequentially.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Fong et al to include a heat dissipation channel that comprises a plurality of annular sub-channels as taught by Lee et al in order to provide fluid communication between the cooling channel and the cooling space [0063]. Further, a person of ordinary skill in the art would have recognized that having sub-channels would help optimize the fluid flow which would further improve the cooling capability of the device (see MPEP 2143.I(D)).
The combination of Fong et al and Lee et al now discloses
the memory (memory devices [0014] Fig 1 Fong et al) comprises first regions (shown in annotated Fig 10 Lee et al) located inside the annular sub-channels (720 Fig 10 Lee et al) and second regions (shown in annotated Fig 10 Fong et al) located outside the annular sub-channels (720 Fig 10 Lee et al),
wherein at least one of: the connected first conductive pillar (shown in annotated Fig 1 Fong et al) and second conductive pillar (shown in annotated Fig 1 Fong et al) are located in the first regions (shown in annotated Fig 10 Lee et al); and
the connected first conductive pillar (shown in annotated Fig 1 Fong et al) and second conductive pillar (shown in annotated Fig 1 Fong et al) are located in the second regions (shown in annotated Fig 10 Lee et al).
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Claims 10-13, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fong et al (US 2018/0082989) in view of Colgan et al (US 2009/0284921).
Regarding Claim 10, Fong et al discloses a fabrication method of a memory (memory devices [0014] Fig 1), the method comprising: forming a first semiconductor structure (shown in annotated Fig 1),
wherein the first semiconductor structure (shown in annotated Fig 1) comprises a first dielectric layer (inter-layer structures with high thermal conductivity (and low electrical conductivity) [0199] and may be SiO2, SiC, or Al2O3, [0200] shown in annotated Fig 1), a first heat conduction layer (layer that contains coolant flow channels [0062] shown in annotated Fig 1) covering the first dielectric layer (shown in annotated Fig 1), and a first conductive pillar (inter-layer metal connections [0036] shown in annotated Fig 1) located in the first dielectric layer (shown in annotated Fig 1) and the first heat conduction layer (shown in annotated Fig 1);
forming a second semiconductor structure (shown in annotated Fig 1), wherein the second semiconductor structure (shown in annotated Fig 1) comprises a second dielectric layer (inter-layer structures with high thermal conductivity (and low electrical conductivity) [0199] and may be SiO2, SiC, or Al2O3, [0200] shown in annotated Fig 1), a second heat conduction layer (layer that contains coolant flow channels [0062] shown in annotated Fig 1) covering the second dielectric layer (shown in annotated Fig 1), and a second conductive pillar (inter-layer metal connections [0036] shown in annotated Fig 1) located in the second dielectric layer (shown in annotated Fig 1) and the second heat conduction layer (shown in annotated Fig 1);
forming a heat dissipation channel (coolant flow channels [0062] shown in annotated Fig 1), wherein the heat dissipation channel (shown in annotated Fig 1) is located in at least one of the first heat conduction layer (shown in annotated Fig 1) or the second heat conduction layer (shown in annotated Fig 1), and the heat dissipation channel (shown in annotated Fig 1) is disposed as being spaced apart from at least one of the first conductive pillar (shown in annotated Fig 1) or the second conductive pillar (shown in annotated Fig 1);
after ([0115]-[0116]) forming the heat dissipation channel (shown in annotated Fig 1), bonding ([0115]-[0116]) the second semiconductor structure (shown in annotated Fig 1) and the first semiconductor structure (shown in annotated Fig 1), with the second conductive pillar (shown in annotated Fig 1) being connected with the first conductive pillar (shown in annotated Fig 1), and the second heat conduction layer (shown in annotated Fig 1) being connected with the first heat conduction layer (shown in annotated Fig 1) to form a heat conduction structure (shown in annotated Fig 1).
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Fong et al does not disclose
replacing the heat conduction structure with a filling layer, wherein a connection face of the first conductive pillar and the second conductive pillar is located in the filling layer.
Colgan et al, in the related art of semiconductor devices that include heat sinks, discloses
replacing the heat conduction structure (channel cooler device 30 [0043] Fig 1) with a filling layer (thermal bond TB1 [0043] Fig 1),
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Fong et al to include replacing the heat conduction structure with a filling layer as taught by Colgan et al in order to meet the cooling requirements of chips that have lower cooling requirements [0040] and since the micro channel cooler can be replaced when needed [0043]. Further, a person of ordinary skill in the art would have recognized that having a cooling channel structure replaced with a filling layer would allow for less cooling which would expand the functional capability of the device to also include chips with lower cooling requirements (see MPEP 2143.I(D)).
The combination of Fong et al and Colgan et al now discloses
wherein a connection face of the first conductive pillar (shown above in annotated Fig 1 Fong et al) and the second conductive pillar (shown above in annotated Fig 1 Fong et al) is located in the filling layer (TB1 Fig 1 Colgan et al).
Regarding Claim 11, the combination of Fong et al and Colgan et al discloses the limitations of claim 10 as explained above. The combination of Fong et al and Colgan et al further discloses
further comprising: introducing a heat dissipation medium (coolant fluids [0279] Fong et al) into the heat dissipation channel (shown above in annotated Fig 1 Fong et al).
Regarding Claim 12, the combination of Fong et al and Colgan et al discloses the limitations of claim 10 as explained above. The combination of Fong et al and Colgan et al further discloses
further comprising: controlling a flow rate of the introduced heat dissipation medium (shown above in annotated Fig 1) according to a temperature (temperature-controlled cleaving process [0076] Fong et al) of at least one of the first semiconductor structure (shown above in annotated Fig 1 Fong et al) and the second semiconductor structure (shown above in annotated Fig 1 Fong et al).
Regarding Claim 13, the combination of Fong et al and Colgan et al discloses the limitations of claim 11 as explained above. The combination of Fong et al and Colgan et al further discloses
wherein the heat dissipation medium (shown above in annotated Fig 1 Fong et al) comprises a gas or a liquid (coolant fluids [0279] Fong et al).
Regarding Claim 16, the combination of Fong et al and Colgan et al discloses the limitations of claim 10 as explained above. The combination of Fong et al and Colgan et al further discloses
wherein the forming the heat dissipation channel (shown in annotated Fig 1 Fong et al) comprises: forming a first heat dissipation channel (shown in annotated Fig 1) located in the first heat conduction layer (shown in annotated Fig 1 Fong et al) and disposed as being spaced apart from the first conductive pillar (shown in annotated Fig 1 Fong et al); and
forming a second heat dissipation channel (shown in annotated Fig 1 Fong et al) located in the second heat conduction layer (shown in annotated Fig 1 Fong et al) and disposed as being spaced apart from the second conductive pillar (shown in annotated Fig 1 Fong et al),
wherein the second heat dissipation channel (shown in annotated Fig 1 Fong et al) is communicated with the first heat dissipation channel (shown in annotated Fig 1 Fong et al)
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Regarding Claim 17, the combination of Fong et al and Colgan et al discloses the limitations of claim 10 as explained above. The combination of Fong et al and Colgan et al further discloses
further comprising: forming a third heat conduction layer (shown in annotated Fig 1 Fong et al) in the first heat dissipation channel (shown in annotated Fig 1 Fong et al), with a bottom of the third heat conduction layer (shown in annotated Fig 1 Fong et al) being located in the first heat conduction layer (shown in annotated Fig 1 Fong et al); and
forming a fourth heat conduction layer (shown in annotated Fig 1 Fong et al) in the second heat dissipation channel (shown in annotated Fig 1 Fong et al), with a bottom of the fourth heat conduction layer (shown in annotated Fig 1 Fong et al) being located in the second heat conduction layer (shown in annotated Fig 1 Fong et al),
wherein after bonding ([0115]-[0116] Fong et al) the second semiconductor structure (shown in annotated Fig 1 Fong et al) and the first semiconductor structure (shown in annotated Fig 1 Fong et al), the third heat conduction layer (shown in annotated Fig 1 Fong et al) is connected with the fourth heat conduction layer (shown in annotated Fig 1 Fong et al).
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Regarding Claim 18, the combination of Fong et al and Colgan et al discloses the limitations of claim 17 as explained above. The combination of Fong et al and Colgan et al further discloses
further comprising: removing the heat conduction structure (shown above in annotated Fig 1 Fong et al), the third heat conduction layer (shown above in annotated Fig 1 Fong et al), and the fourth heat conduction layer (shown above in annotated Fig 1 Fong et al) to form a gap in the first dielectric layer (shown above in annotated Fig 1 Fong et al) and the second dielectric layer (shown above in annotated Fig 1 Fong et al); and
filling the gap (shown in annotated Fig 1 (the examiner notes that a gap may be filled with material and still be considered a gap) with a filling material (filled polymer [0043]) to form the filling layer (TB1 Fig 1 Colgan et al).
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Regarding Claim 20, the combination of Fong et al and Colgan et al discloses the limitations of claim 10 as explained above. The combination of Fong et al and Colgan et al further discloses
wherein the forming the first semiconductor structure (shown in annotated Fig 1 Fong et al) comprises: forming a first dielectric material layer (shown in annotated Fig 1 Fong et al) covering a first substrate (shown in annotated Fig 1 Fong et al);
forming a first via (shown in annotated Fig 1 Fong et al) penetrating through the first dielectric material layer (shown in annotated Fig 1 Fong et al);
forming the first conductive pillar (shown in annotated Fig 1 Fong et al) in the first via (shown in annotated Fig 1 Fong et al); and
forming the first heat conduction layer (shown in annotated Fig 1 Fong et al) covering the first dielectric layer (shown in annotated Fig 1 Fong et al);
the forming the second semiconductor structure (shown in annotated Fig 1 Fong et al) comprises: forming a second dielectric material layer (shown in annotated Fig 1 Fong et al) covering a second substrate (shown in annotated Fig 1 Fong et al);
forming a second via (shown in annotated Fig 1 Fong et al) penetrating through the second dielectric material layer (shown in annotated Fig 1 Fong et al);
forming the second conductive pillar (shown in annotated Fig 1 Fong et al) in the second via (shown in annotated Fig 1 Fong et al);
and
forming the second heat conduction layer (shown in annotated Fig 1 Fong et al) covering the second dielectric layer (shown in annotated Fig 1 Fong et al).
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The combination of Fong et al and Colgan et al, as applied to claim 10, does not directly disclose
removing part of the first dielectric material layer along a direction facing the first substrate, with the remaining first dielectric material layer constituting the first dielectric layer; and
removing part of the second dielectric material layer along a direction facing the second substrate, with the remaining second dielectric material layer constituting the second dielectric layer.
However, Fong et al, in the related art of semiconductor devices that include transistors, discloses
removing parts of the dielectric layer that are damaged from the hydrogen process ([0018] Fig 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fong et al and Colgan et al, as applied to claim 10, to include removing part of the first dielectric material layer and the second dielectric material layer as taught by Fong et al in order to provide a smoothing process and removed damaged areas as referred to by Fong et al [0018]. Further, a person of ordinary skill in the art would have recognized that having a smoothing process to provide smooth layers would be advantageous in providing stronger bonds which would give better structural support and resist unwanted damage to the device (see MPEP 2143.I(D)).
The combination of Fong et al and Colgan et al now discloses
removing ([0018] Fig 6 Fong et al) part of the first dielectric material layer (shown above in annotated Fig 1 Fong et al) along a direction facing the first substrate (shown above in annotated Fig 1 Fong et al), with the remaining first dielectric material layer (shown above in annotated Fig 1 Fong et al) constituting the first dielectric layer (shown above in annotated Fig 1 Fong et al); and
removing ([0018] Fig 6 Fong et al) part of the second dielectric material layer (shown above in annotated Fig 1 Fong et al) along a direction facing the second substrate (shown above in annotated Fig 1 Fong et al), with the remaining second dielectric material layer (shown above in annotated Fig 1 Fong et al) constituting the second dielectric layer (shown above in annotated Fig 1 Fong et al).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Fong et al (US 2018/0082989) in view of Campbell et al (US 2014/0071626).
Regarding Claim 15, Fong et al discloses the limitations of claim 14 as explained above. Fong et al does not directly disclose
further comprising: forming a plastic molding dielectric in the communicated first heat dissipation channel and second heat dissipation channel.
Campbell et al, in the related art of semiconductor devices that include CMOS devices, discloses
further comprising: forming a plastic molding dielectric (the thermally conductive sheet 411 of the three-dimensional folded structure 410 may comprise a thermally conductive plastic molded into the desired fin configuration [0043] Fig 4C) in the communicated first heat dissipation channel (lower portion of coolant-carrying channels 415 [0043]) and second heat dissipation channel (upper portion of coolant-carrying channels 415 [0043]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Fong et al to include further comprising: forming a plastic molding dielectric in the communicated first heat dissipation channel and second heat dissipation channel as taught by Campbell et al in order to thermally conduct during the operation of the coolant-carrying channels [0043] which would optimize the cooling capability of the device. Further, a person of ordinary skill in the art would have recognized that having a plastic molding dielectric would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Fong et al (US 2018/0082989) in view of Colgan et al (US 2009/0284921), and in further view of Tsai (US 2008/0048235).
Regarding Claim 19, the combination of Fong et al and Colgan et al discloses the limitations of claim 10 as explained above. The combination of Fong et al and Colgan et al further discloses
wherein the forming the first semiconductor structure (shown in annotated Fig 1 Fong et al) comprises: forming a first via (shown in annotated Fig 1 Fong et al) penetrating through the first dielectric layer (shown in annotated Fig 1 Fong et al);
forming a first conductive sub-pillar (shown in annotated Fig 1 Fong et al) in the first via (shown in annotated Fig 1 Fong et al);
the forming the second semiconductor structure (shown in annotated Fig 1 Fong et al) comprises: forming a second via (shown in annotated Fig 1) penetrating through the second dielectric layer (shown in annotated Fig 1 Fong et al); and
forming a third conductive sub-pillar (shown in annotated Fig 1 Fong et al) in the second via (shown in annotated Fig 1 Fong et al).
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The combination of Fong et al and Colgan et al does not disclose
performing electroplating on the first conductive sub-pillar to form a second conductive sub-pillar, wherein the first conductive pillar comprises the first conductive sub-pillar and the second conductive sub-pillar; and
after forming the second conductive sub-pillar, forming the first heat conduction layer covering the first dielectric layer;
performing electroplating on the third conductive sub-pillar to form a fourth conductive sub-pillar, wherein the second conductive pillar comprises the third conductive sub-pillar and the fourth conductive sub-pillar; and
after forming the fourth conductive sub-pillar, forming the second heat conduction layer covering the second dielectric layer.
Tsai, in the related art of semiconductor devices that include memory devices, discloses
forming an opening in the stacked structure exposing the contact plug, forming a conductive pillar in the opening and the conductive pillar electrically connecting the contact plug, performing at least one electrochemical plating process to form an electroplating structure on the surface of the conductive pillar [0009].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fong et al and Colgan et al to include an electroplating process on a conductive sub-pillar to form another conductive sub-pillar as taught by Tsai in order to have sufficient mechanical supporting strength to prevent leaning or collapsing [0011]. Further, a person of ordinary skill in the art would have recognized that using electroplating do form a conductive pillar comprising sub-pillars is well known in the art and would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Fong et al, Colgan et al, and Tsai now discloses
performing electroplating ([0009] Tsai) on the first conductive sub-pillar (shown in annotated Fig 1 Fong et al) to form a second conductive sub-pillar (shown in annotated Fig 1 Fong et al), wherein the first conductive pillar (shown in annotated Fig 1 Fong et al) comprises the first conductive sub-pillar (shown in annotated Fig 1 Fong et al) and the second conductive sub-pillar (shown in annotated Fig 1 Fong et al); and
after (steps of electroplating [0009] Tsai) forming the second conductive sub-pillar (shown in annotated Fig 1 Fong et al), forming the first heat conduction layer (shown in annotated Fig 1 Fong et al) covering the first dielectric layer (shown in annotated Fig 1 Fong et al) (coolant flow channels are formed before the first semiconductor structure and the second semiconductor structure are bonded ([0115]-[0116]) Fong et al);
performing electroplating ([0009] Tsai) on the third conductive sub-pillar (shown in annotated Fig 1 Fong et al) to form a fourth conductive sub-pillar (shown in annotated Fig 1 Fong et al), wherein the second conductive pillar (shown in annotated Fig 1 Fong et al) comprises the third conductive sub-pillar (shown in annotated Fig 1 Fong et al) and the fourth conductive sub-pillar (shown in annotated Fig 1 Fong et al); and
after (steps of electroplating [0009] Tsai) forming the fourth conductive sub-pillar (shown in annotated Fig 1 Fong et al), forming the second heat conduction layer (shown in annotated Fig 1 Fong et al) covering the second dielectric layer (shown in annotated Fig 1 Fong et al) (coolant flow channels are formed before the first semiconductor structure and the second semiconductor structure are bonded ([0115]-[0116]) Fong et al).
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Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al (US 2019/0252325) which discloses forming conductive pillars through the electroplating method [0022], and Lee et al’2015 (US 2015/0262953) which discloses forming conductive pillars through the electroplating method [Claim 5/Claim 13].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812