Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Transistor Structure .
The disclosure is objected to because of the following informalities: in paragraph.
Appropriate correction is required.
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Fig. 1B of Yamazaki, reproduced here with annotations added by the examiner.
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Fig. 3A of Yamazaki, reproduced here with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 7-10, 12-15, and 17-19 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Yamazaki et. al., Pub. No. US 2015/0187824 A1, hereafter referred to as Yamazaki.
Regarding claim 1, Yamazaki teaches all of the limitations of the claim in Figs. 1B and 3A, both reproduced above with annotations added by the examiner, and in the associated text: “An electronic device, comprising: a substrate” (Fig. 1B, substrate 700); “and a transistor disposed on the substrate” (transistor 150), “wherein the transistor comprises: a gate electrode” (electrode 102); “a semiconductor layer at least partially overlapping the gate electrode” (semiconductor layer 108), “wherein the semiconductor layer comprises a first sub-semiconductor layer” (Fig. 3A, sublayer 108b) “and a second sub-semiconductor layer disposed on the first sub-semiconductor layer” (Fig. 3A, sublayer 108c), “and the second sub-semiconductor layer comprises indium, gallium and zinc” ([0145]: “The… oxide semiconductor layer 108b, and the oxide semiconductor layer 108c are each formed using a material including one or both of In and Ga. Typical examples [include]… an In-M-Zn oxide (an oxide including In, an element M, and Zn; the element M is one or plurality of metal elements selected from Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf which have larger bonding strength to oxygen than In does).” (emphasis added by the examiner)); “a drain electrode electrically connected to the semiconductor layer” (electrode 119); “and a source electrode electrically connected to the semiconductor layer” (electrode 109), “wherein in the second sub-semiconductor layer, an atomic percentage of indium is less than an atomic percentage of gallium, and the atomic percentage of gallium is less than an atomic percentage of zinc” ([0150]: “For example, an In--Ga--Zn oxide which is formed using a target having an atomic ratio of In:Ga:Zn=…1:3:4, 1:3:6, ...can be used for each of the oxide semiconductor layers 108a and 108c containing In or Ga”).
Regarding claim 3, Yamazaki anticipates “The electronic device of claim 1, wherein an atomic ratio of indium, gallium and zinc is 1:3:6-8 in the second sub-semiconductor layer” by teaching that sublayer 108c in Fig. 3A may have an atomic ratio of indium to gallium to zinc of 1:3:6, which is within the claimed range ([0150]; also see MPEP 2131.03 I: ““If the prior art discloses a point within the claimed range, the prior art anticipates the claim.” UCB, Inc. v. Actavis Labs. UT, Inc., 65 F.4th 679, 687, 2023 USPQ2d 448 (Fed. Cir. 2023).”).
Regarding claim 4, Yamazaki further teaches “The electronic device of claim 1, wherein the first sub-semiconductor layer comprises indium” ([0150]: “Further, an In--Ga--Zn oxide which is formed using a target having an atomic ratio of In:Ga:Zn=… 1:1:1… can be used for the oxide semiconductor layer 108b.”), “and the atomic percentage of indium in the second sub-semiconductor layer is less than an atomic percentage of indium in the first sub-semiconductor layer.” ([0150]; in particular, using a ratio of 1:3:6 for sublayer 108c in Fig. 3A and a ratio of 1:1:1 for sublayer 108b will yield an atomic percentage of indium of 10% in the second sublayer, and 33.3% in the first sublayer, which is larger than the percentage in the second sublayer). It is assumed for the purposes of examination that the atomic percentages are calculated excluding oxygen in accordance with the applicant’s disclosure.
Regarding claim 5, Yamazaki further teaches “The electronic device of claim 1, wherein the first sub-semiconductor layer comprises indium, gallium and zinc, and an atomic ratio of indium, gallium and zinc is 1:1:1 in the first sub-semiconductor layer” ([0150]; as noted in the discussion of claim 4 above, the first sublayer 108b is composed of an indium-gallium-zinc oxide and may have an atomic ratio of In:Ga:Zn of 1:1:1).
Regarding claim 7, Yamazaki further teaches “The electronic device of claim 1, further comprising: an insulating layer disposed on the transistor” (Fig. 1B, insulating layer 113); “and a metal layer disposed on the insulating layer” ([0187]: “The… electrode 114… can be formed with a single-layer structure or a stacked-layer structure using any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, manganese, silver, tantalum, and tungsten, or an alloy containing any of these metals as its main component.”; Fig. 1B, the lower metal layer of the stacked metal layer structure 114), “wherein the metal layer penetrates the insulating layer to electrically connect to the drain electrode” (Fig. 1B, electrode 119).
Regarding claim 8, Yamazaki further teaches “The electronic device of claim 7, wherein the metal layer” (Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]) “electrically connects to the drain electrode” (Fig. 1B, electrode 119) “through a via of the insulating layer” (Fig. 1B, insulating layer 113).
Regarding claim 9, Yamazaki further teaches “The electronic device of claim 7, further comprising: a conductive layer” (Fig. 1B, the upper metal layer of the stacked metal layer structure 114) “disposed on the metal layer” (Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]) “and electrically connecting to the drain electrode” (Fig. 1B, electrode 119) “through the metal layer”.
Regarding claim 10, Yamazaki teaches all of the limitations of the claim: “An electronic device, comprising: a substrate” (Fig. 1B, substrate 700); “and a transistor disposed on the substrate” (Fig. 1B, transistor 150), “wherein the transistor comprises: a gate electrode” (electrode 102); “a semiconductor layer at least partially overlapping the gate electrode” (semiconductor layer 108), “wherein the semiconductor layer comprises a first sub-semiconductor layer” (Fig. 3A, sublayer 108b) “and a second sub-semiconductor layer disposed on the first sub-semiconductor layer” (Fig. 3A, sublayer 108c), “and the second sub-semiconductor layer comprises indium, gallium and zinc” ([0145]); “a drain electrode electrically connected to the semiconductor layer” (electrode 119); “and a source electrode electrically connected to the semiconductor layer” (electrode 109), “wherein a thickness of the drain electrode is less than a thickness of the semiconductor layer, and a thickness of the source electrode is less than the thickness of the semiconductor layer” ([0147]: “The [thickness] of… the oxide semiconductor layer 108c [is] greater than or equal to 3 nm and less than or equal to 100 nm… The thickness of the oxide semiconductor layer 108b is greater than or equal to 3 nm and less than or equal to 200 nm…”, [0227]: “Next, a conductive layer 127 for forming the electrode 109 and the electrode 119 is formed… In this embodiment, as the conductive layer 127, 100-nm-thick tungsten is deposited by a sputtering method.”; the disclosed ranges allow for a semiconductor layer 108 with a thickness of up to 300 nm, which is greater than the thickness of the source and drain electrodes 109 and 119).
Regarding claim 12, Yamazaki further teaches “The electronic device of claim 10, wherein in the second sub-semiconductor layer, an atomic percentage of indium is less than an atomic percentage of gallium, and the atomic percentage of gallium is less than an atomic percentage of zinc”. ([0150]; in particular, as pointed out in the discussion of claim 1 above, Yamazaki discloses atomic ratios of In:Ga:Zn of 1:3:4 and 1:3:6, both of which satisfy the new limitation introduced by this claim).
Regarding claim 13, Yamazaki anticipates “The electronic device of claim 10, wherein an atomic ratio of indium, gallium and zinc is 1:3:6-8 in the second sub-semiconductor layer” by teaching that sublayer 108c in Fig. 3A may have an atomic ratio of 1:3:6, which lies within the claimed range ([0150]; also see MPEP 2131.03 I).
Regarding claim 14, Yamazaki further teaches “The electronic device of claim 10, wherein the first sub-semiconductor layer comprises indium” ([0150]; as noted in the discussion of claim 4 above, the first sublayer 108b is composed of an indium-gallium-zinc oxide and may have an atomic ratio of In:Ga:Zn of 1:1:1), “and the atomic percentage of indium in the second sub-semiconductor layer is less than an atomic percentage of indium in the first sub-semiconductor layer”. ([0150]; as pointed out in the discussion of claim 4 above, letting the ratio of In:Ga:Zn in the second sublayer 108c be 1:3:6 and that in the first sublayer 108b be 1:1:1 yields atomic percentages of In of 10% in the second sublayer and 33.3% in the first sublayer, which satisfy the new limitation introduced by this claim).
Regarding claim 15, Yamazaki further teaches “The electronic device of claim 10, wherein the first sub-semiconductor layer comprises indium, gallium and zinc, and an atomic ratio of indium, gallium and zinc is 1:1:1 in the first sub-semiconductor layer” ([0150]; as noted in the discussion of claim 4 above, the first sublayer 108b is composed of an indium-gallium-zinc oxide and may have an atomic ratio of In:Ga:Zn of 1:1:1).
Regarding claim 17, Yamazaki further teaches “The electronic device of claim 10, further comprising: an insulating layer disposed on the transistor” (Fig. 1B, insulating layer 113); “and a metal layer disposed on the insulating layer” (Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]), “wherein the metal layer penetrates the insulating layer to electrically connect to the drain electrode” (Fig. 1B, electrode 119).
Regarding claim 18, Yamazaki further teaches “The electronic device of claim 17, wherein the metal layer” (Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]) “electrically connects to the drain electrode” (Fig. 1B, electrode 119) “through a via of the insulating layer” (Fig. 1B, insulating layer 113).
Regarding claim 19, Yamazaki further teaches “The electronic device of claim 17, further comprising: a conductive layer” (Fig. 1B, the upper metal layer of the stacked metal layer structure 114) “disposed on the metal layer” (Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]) “and electrically connecting to the drain electrode” (Fig. 1B, electrode 119) “through the metal layer”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 6, 11, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki.
Regarding claim 2, Yamazaki teaches “The electronic device of claim 1”, but does not teach a device “wherein a thickness of the second sub-semiconductor layer ranges from 800 Å to 2000 Å.”
However, Yamazaki does teach a thickness of sublayer 108c in Fig. 3A in the overlapping range of 3 nm to 100 nm ([0147]: “The [thickness] of… the oxide semiconductor layer 108c [is] greater than or equal to 3 nm and less than or equal to 100 nm”).
It would have been obvious to one of ordinary skill in the art to modify the transistor of Yamazaki so that the second semiconductor sublayer has a thickness within the range, 800 Å to 2000 Å (or 80 nm to 200 nm), as current case law holds that the fact that Yamazaki teaches a range of thicknesses of the second sublayer that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I: “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)”).
Regarding claim 6, Yamazaki teaches “The electronic device of claim 1”, but does not teach a device “wherein a thickness of the first sub-semiconductor layer ranges from 800 Å to 2000 Å.”
However, Yamazaki does teach a thickness of sublayer 108b in Fig. 3A in the overlapping range of 3 nm to 200 nm ([0147]: “The thickness of the oxide semiconductor layer 108b is greater than or equal to 3 nm and less than or equal to 200 nm”).
It would have been obvious to one of ordinary skill in the art to modify the transistor of Yamazaki so that the first semiconductor sublayer has a thickness within the range, 800 Å to 2000 Å (or 80 nm to 200 nm), as current case law holds that the fact that Yamazaki teaches a range of thicknesses of the first sublayer that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I).
Regarding claim 11, Yamazaki teaches “The electronic device of claim 10”, but does not teach a device “wherein a thickness of the second sub-semiconductor layer ranges from 800 Å to 2000 Å.”
However, Yamazaki does teach a thickness of sublayer 108c in Fig. 3A in the overlapping range of 3 nm to 100 nm ([0147]: “The [thickness] of… the oxide semiconductor layer 108c [is] greater than or equal to 3 nm and less than or equal to 100 nm”).
It would have been obvious to one of ordinary skill in the art to modify the transistor of Yamazaki so that the second semiconductor sublayer has a thickness within the range, 800 Å to 2000 Å (or 80 nm to 200 nm), as current case law holds that the fact that Yamazaki teaches a range of thicknesses of the second sublayer that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I).
Regarding claim 16, Yamazaki teaches “The electronic device of claim 10”, but does not teach a device “wherein a thickness of the first sub-semiconductor layer ranges from 800 Å to 2000 Å.”
However, Yamazaki does teach a thickness of sublayer 108b in Fig. 3A in the overlapping range of 3 nm to 200 nm ([0147]: “The thickness of the oxide semiconductor layer 108b is greater than or equal to 3 nm and less than or equal to 200 nm”).
It would have been obvious to one of ordinary skill in the art to modify the transistor of Yamazaki so that the first semiconductor sublayer has a thickness within the range, 800 Å to 2000 Å (or 80 nm to 200 nm), as current case law holds that the fact that Yamazaki teaches a range of thicknesses of the first sublayer that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. More specifically, Goto
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818