Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on May 29, 2026, under 37 CFR 1.312 has been entered. All objections raised by the examiner to the applicant’s title and specification in the previous office action have been addressed. Therefore, all objections to the specification are withdrawn.
Response to Arguments
Applicant's arguments filed May 29, 2026, have been fully considered but they are not persuasive.
Regarding the remarks on claim rejections under 35 U.S.C. 102 and 103, the applicant makes the following two arguments. First, the applicant argues that Yamazaki et. al., Pub. No. US 2015/0187824, hereafter referred to as Yamazaki, does not teach that the electrode 114 in Fig. 3A consists of a transparent conductive material disposed on a metal layer. Second, the applicant argues that Yamazaki does not teach that the electrodes 109 and 119, corresponding to source and drain electrodes on a transistor, are disposed on an upper surface of the semiconductor layer.
In response to both arguments, neither of the features described by the applicant was actually recited in the original claims, only in the specification. While understanding of the language of the claims may be gleaned from the specification, claim limitations cannot be imported from the specification (see MPEP 2111.01: ““Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim. For example, a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment.” Superguide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875, 69 USPQ2d 1865, 1868 (Fed. Cir. 2004).”). The applicant’s argument that Yamazaki fails to teach the limitations in question is based on importing limitations from the specification into the claims, namely that the conductive layer disposed on the metal layer is specifically a transparent conductive layer and that the source and drain electrodes must contact an upper surface of the semiconductor layer, that were not recited in the original claims.
In response to the first argument in particular, the examiner must respectfully disagree with the applicant’s argument that Yamazaki fails to teach an electrode 114 consisting of a metal layer and a transparent conductive layer. Paragraph [0188] of Yamazaki discloses a number of conductive oxides as possible materials for one or more layers of the electrode 114, two of which, indium tin oxide and indium zinc oxide, are known to be transparent conductors. Therefore, Yamazaki anticipates the limitation, “wherein the conductive layer comprises a transparent conductive material”, in the amended claims 1 and 10.
In light of the above arguments, the examiner maintains that the rejections of the original claims 1, 3-5, 7-10, 12-15, and 17-19 under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Yamazaki and of the original claims 2, 6, 11, and 16 under 35 U.S.C. 103 as being unpatentable over Yamazaki were proper. However, in light of the applicant’s amendments to claims 1, 8-9, 10, and 18-19 and the cancellation of claims 7 and 17, the original rejections are rendered moot and have necessitated the new grounds for rejection detailed below.
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Fig. 1B of Yamazaki, reproduced with annotations added by the examiner.
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Fig. 3A of Yamazaki, reproduced with annotations added by the examiner.
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Fig. 10B of Yamazaki, reproduced with annotations added by the examiner.
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Fig. 36D of Yamazaki, reproduced with annotations added by the examiner.
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Fig. 5A of Goto, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Goto et. al., Pub. No. US 2017/0358682, hereafter referred to as Goto.
Regarding claim 1, Yamazaki teaches “An electronic device, comprising: a substrate” (Yamazaki Fig. 1B, reproduced above with annotations added by the examiner, substrate 700); “and a transistor disposed on the substrate” (Yamazaki Figs. 1B and 3A, reproduced above with annotations added by the examiner, transistor 150), “wherein the transistor comprises: a gate electrode” (Yamazaki Figs. 1B and 3A, electrode 102); “a semiconductor layer at least partially overlapping the gate electrode” (Yamazaki Figs. 1B and 3A, semiconductor layer 108), “wherein the semiconductor layer comprises a first sub-semiconductor layer” (Yamazaki Fig. 3A, sublayer 108b) “and a second sub-semiconductor layer disposed on the first sub-semiconductor layer” (Yamazaki Fig. 3A, sublayer 108c), “and the second sub-semiconductor layer comprises indium, gallium and zinc” (Yamazaki [0145]: “The… oxide semiconductor layer 108b, and the oxide semiconductor layer 108c are each formed using a material including one or both of In and Ga. Typical examples [include]… an In-M-Zn oxide (an oxide including In, an element M, and Zn; the element M is one or plurality of metal elements selected from Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf which have larger bonding strength to oxygen than In does).” (emphasis added by the examiner)); “a drain electrode electrically connected to the semiconductor layer” (Yamazaki Figs. 1B and 3A, electrode 119); “and a source electrode electrically connected to the semiconductor layer” (Yamazaki Figs. 1B and 3A, electrode 109), “an insulating layer disposed on the transistor” (Yamazaki Fig. 1B, insulating layer 113); “and a metal layer disposed on the insulating layer” (Yamazaki [0187-0188]: “The… electrode 114… can be formed with a single-layer structure or a stacked-layer structure using any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, manganese, silver, tantalum, and tungsten, or an alloy containing any of these metals as its main component… Note that a conductive material containing oxygen such as indium tin oxide, zinc oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added… may be used. It is also possible to use a stacked-layer structure formed using a material containing the above metal element and conductive material containing oxygen.”; Fig. 1B, the lower layer of the stacked conductive layer structure 114, assumed hereafter to be made of a metal), “wherein the metal layer penetrates the insulating layer to electrically connect to the drain electrode” (Yamazaki Fig. 1B, electrode 119), “a conductive layer” (Yamazaki Fig. 1B, the upper metal layer of the stacked metal layer structure 114) “disposed on the metal layer” (Yamazaki Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]) “and electrically connecting to the drain electrode” (Yamazaki Fig. 1B, electrode 119), “wherein the conductive layer comprises a transparent conductive material” (Yamazaki [0188]: “Note that a conductive material containing oxygen such as indium tin oxide, zinc oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added… may be used. It is also possible to use a stacked-layer structure formed using a material containing the above metal element and conductive material containing oxygen.” (emphasis added by the examiner); Fig. 1B, the upper layer of the stacked conductive layer structure 114, hereafter assumed to be one of indium tin oxide or indium zinc oxide, both of which are transparent conductors), and “wherein in the second sub-semiconductor layer, an atomic percentage of indium is less than an atomic percentage of gallium, and the atomic percentage of gallium is less than an atomic percentage of zinc” (Yamazaki [0150]: “For example, an In--Ga--Zn oxide which is formed using a target having an atomic ratio of In:Ga:Zn=…1:3:4, 1:3:6, ...can be used for each of the oxide semiconductor layers 108a and 108c containing In or Ga”), but does not teach “(a drain electrode) covering a part of an upper surface of the semiconductor layer” and “(a source electrode) covering another part of the upper surface of the semiconductor layer”. Yamazaki instead teaches that the drain and source electrodes cover a lower surface of the semiconductor layer (see Yamazaki Fig. 1B).
Goto, on the other hand, does teach “(a drain electrode) covering a part of an upper surface of the semiconductor layer” (Goto [0104]; Fig. 5A, reproduced above with annotations added by the examiner, note that the electrode 112a contacts part of the upper surface of the semiconductor layer 106_1) and “(a source electrode) covering another part of the upper surface of the semiconductor layer” (Goto [0104]; Fig. 5A, note that the electrode 112b contacts a different part of the upper surface of the semiconductor layer 106_1).
The source and drain electrodes of Goto can be incorporated in the device of Yamazaki by disposing the source and drain electrodes of Yamazaki on the upper surface of the semiconductor layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to dispose the source and drain electrodes of Yamazaki on the upper surface of the semiconductor layer as taught by Goto because the electrodes will function just as well disposed on the upper surface of the semiconductor layer and it would be a simple substitution of one element for another.
Regarding claim 2, the combination of Yamazaki and Goto described in the discussion of claim 1 teaches “The electronic device of claim 1”, but does not teach “wherein a thickness of the second sub-semiconductor layer ranges from 800 Å to 2000 Å.”
However, Yamazaki does teach a thickness of sublayer 108c in Fig. 3A in the overlapping range of 3 nm to 100 nm (Yamazaki [0147]: “The [thickness] of… the oxide semiconductor layer 108c [is] greater than or equal to 3 nm and less than or equal to 100 nm”).
It would have been obvious to one of ordinary skill in the art to modify the transistor of the combined device of Yamazaki and Goto described in the discussion of claim 1 so that the second semiconductor sublayer has a thickness within the range, 800 Å to 2000 Å (or 80 nm to 200 nm), as current case law holds that the fact that the combination of Yamazaki and Goto described in the discussion of claim 1 teaches a range of thicknesses of the second sublayer that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I: “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)”).
Regarding claim 3, the combination of Yamazaki and Goto described in the discussion of claim 1 anticipates “The electronic device of claim 1, wherein an atomic ratio of indium, gallium and zinc is 1:3:6-8 in the second sub-semiconductor layer” by teaching that sublayer 108c in Fig. 3A may have an atomic ratio of indium to gallium to zinc of 1:3:6, which is within the claimed range (Yamazaki [0150]; also see MPEP 2131.03 I: ““If the prior art discloses a point within the claimed range, the prior art anticipates the claim.” UCB, Inc. v. Actavis Labs. UT, Inc., 65 F.4th 679, 687, 2023 USPQ2d 448 (Fed. Cir. 2023).”).
Regarding claim 4, the combination of Yamazaki and Goto described in the discussion of claim 1 further teaches “The electronic device of claim 1, wherein the first sub-semiconductor layer comprises indium” (Yamazaki [0150]: “Further, an In--Ga--Zn oxide which is formed using a target having an atomic ratio of In:Ga:Zn=… 1:1:1… can be used for the oxide semiconductor layer 108b.”), “and the atomic percentage of indium in the second sub-semiconductor layer is less than an atomic percentage of indium in the first sub-semiconductor layer.” (Yamazaki [0150]; in particular, using a ratio of 1:3:6 for sublayer 108c in Fig. 3A and a ratio of 1:1:1 for sublayer 108b will yield an atomic percentage of indium of 10% in the second sublayer, and 33.3% in the first sublayer, which is larger than the percentage in the second sublayer). It is assumed for the purposes of examination that the atomic percentages are calculated excluding oxygen in accordance with the applicant’s disclosure.
Regarding claim 5, the combination of Yamazaki and Goto described in the discussion of claim 1 further teaches “The electronic device of claim 1, wherein the first sub-semiconductor layer comprises indium, gallium and zinc, and an atomic ratio of indium, gallium and zinc is 1:1:1 in the first sub-semiconductor layer” (Yamazaki [0150]; as noted in the discussion of claim 4 above, the first sublayer 108b is composed of an indium-gallium-zinc oxide and may have an atomic ratio of In:Ga:Zn of 1:1:1).
Regarding claim 6, the combination of Yamazaki and Goto described in the discussion of claim 1 teaches “The electronic device of claim 1”, but does not teach a device “wherein a thickness of the first sub-semiconductor layer ranges from 800 Å to 2000 Å.”
However, Yamazaki does teach a thickness of sublayer 108b in Fig. 3A in the overlapping range of 3 nm to 200 nm ([0147]: “The thickness of the oxide semiconductor layer 108b is greater than or equal to 3 nm and less than or equal to 200 nm”).
It would have been obvious to one of ordinary skill in the art to modify the transistor of the combined device of Yamazaki and Goto described in the discussion of claim 1 so that the first semiconductor sublayer has a thickness within the range, 800 Å to 2000 Å (or 80 nm to 200 nm), as current case law holds that the fact that the combination of Yamazaki and Goto described in the discussion of claim 1 teaches a range of thicknesses of the first sublayer that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I).
Regarding claim 8, the combination of Yamazaki and Goto described in the discussion of claim 1 further teaches “The electronic device of claim 1, wherein the metal layer” (Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]) “electrically connects to the drain electrode” (Fig. 1B, electrode 119) “through a via of the insulating layer” (Fig. 1B, insulating layer 113).
Regarding claim 9, the combination of Yamazaki and Goto described in the discussion of claim 1 further teaches “The electronic device of claim 1, wherein the conductive layer” (Yamazaki Fig. 1B, the upper layer of the stacked conductive layer structure 114) “is electrically connected to the drain electrode” (Yamazaki Fig. 1B, electrode 119) “through the metal layer”.
Regarding claim 10, Yamazaki teaches “An electronic device, comprising: a substrate” (Yamazaki Fig. 1B, substrate 700); “and a transistor disposed on the substrate” (Yamazaki Fig. 1B, transistor 150), “wherein the transistor comprises: a gate electrode” (Yamazaki Figs. 1B and 3A, electrode 102); “a semiconductor layer at least partially overlapping the gate electrode” (Yamazaki Figs. 1B and 3A, semiconductor layer 108), “wherein the semiconductor layer comprises a first sub-semiconductor layer” (Yamazaki Fig. 3A, sublayer 108b) “and a second sub-semiconductor layer disposed on the first sub-semiconductor layer” (Yamazaki Fig. 3A, sublayer 108c), “and the second sub-semiconductor layer comprises indium, gallium and zinc” (Yamazaki [0145]); “a drain electrode electrically connected to the semiconductor layer” (Yamazaki Figs. 1B and 3A, electrode 119); “and a source electrode electrically connected to the semiconductor layer” (Yamazaki Figs. 1B and 3A, electrode 109), “an insulating layer disposed on the transistor” (Yamazaki Fig. 1B, insulating layer 113); “and a metal layer disposed on the insulating layer” (Yamazaki [0187-0188]; Fig. 1B, the lower layer of the stacked conductive layer structure 114, assumed hereafter to be made of a metal), “wherein the metal layer penetrates the insulating layer to electrically connect to the drain electrode” (Yamazaki Fig. 1B, electrode 119), “a conductive layer” (Yamazaki Fig. 1B, the upper metal layer of the stacked metal layer structure 114) “disposed on the metal layer” (Yamazaki Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]) “and electrically connecting to the drain electrode” (Yamazaki Fig. 1B, electrode 119), “wherein the conductive layer comprises a transparent conductive material” (Yamazaki [0188]; Fig. 1B, the upper layer of the stacked conductive layer structure 114, hereafter assumed to be one of indium tin oxide or indium zinc oxide, both of which are transparent conductors), and “wherein a thickness of the drain electrode is less than a thickness of the semiconductor layer, and a thickness of the source electrode is less than the thickness of the semiconductor layer” (Yamazaki [0147]: “The [thickness] of… the oxide semiconductor layer 108c [is] greater than or equal to 3 nm and less than or equal to 100 nm… The thickness of the oxide semiconductor layer 108b is greater than or equal to 3 nm and less than or equal to 200 nm…”, [0227]: “Next, a conductive layer 127 for forming the electrode 109 and the electrode 119 is formed… In this embodiment, as the conductive layer 127, 100-nm-thick tungsten is deposited by a sputtering method.”; the disclosed ranges allow for a semiconductor layer 108 with a thickness of up to 300 nm, which is greater than the thickness of the source and drain electrodes 109 and 119), but does not teach “(a drain electrode) covering a part of an upper surface of the semiconductor layer” and “(a source electrode) covering another part of the upper surface of the semiconductor layer”. Yamazaki instead teaches that the drain and source electrodes cover a lower surface of the semiconductor layer (see Yamazaki Fig. 1B).
Goto, on the other hand, does teach “(a drain electrode) covering a part of an upper surface of the semiconductor layer” (Goto [0104]; Fig. 5A, note that the electrode 112a contacts part of the upper surface of the semiconductor layer 106_1) and “(a source electrode) covering another part of the upper surface of the semiconductor layer” (Goto [0104]; Fig. 5A, note that the electrode 112b contacts a different part of the upper surface of the semiconductor layer 106_1).
The source and drain electrodes of Goto can be incorporated in the device of Yamazaki by disposing the source and drain electrodes of Yamazaki on the upper surface of the semiconductor layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to dispose the source and drain electrodes of Yamazaki on the upper surface of the semiconductor layer as taught by Goto because the electrodes will function just as well disposed on the upper surface of the semiconductor layer and it would be a simple substitution of one element for another.
Regarding claim 11, the combination of Yamazaki and Goto described in the discussion of claim 10 teaches “The electronic device of claim 10”, but does not teach a device “wherein a thickness of the second sub-semiconductor layer ranges from 800 Å to 2000 Å.”
However, Yamazaki does teach a thickness of sublayer 108c in Fig. 3A in the overlapping range of 3 nm to 100 nm ([0147]: “The [thickness] of… the oxide semiconductor layer 108c [is] greater than or equal to 3 nm and less than or equal to 100 nm”).
It would have been obvious to one of ordinary skill in the art to modify the transistor of the combined device of Yamazaki and Goto described in the discussion of claim 10 so that the second semiconductor sublayer has a thickness within the range, 800 Å to 2000 Å (or 80 nm to 200 nm), as current case law holds that the fact that the combination of Yamazaki and Goto described in the discussion of claim 10 teaches a range of thicknesses of the second sublayer that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I).
Regarding claim 12, the combination of Yamazaki and Goto described in the discussion of claim 10 further teaches “The electronic device of claim 10, wherein in the second sub-semiconductor layer, an atomic percentage of indium is less than an atomic percentage of gallium, and the atomic percentage of gallium is less than an atomic percentage of zinc”. ([0150]; in particular, as pointed out in the discussion of claim 1 above, Yamazaki discloses atomic ratios of In:Ga:Zn of 1:3:4 and 1:3:6, both of which satisfy the new limitation introduced by this claim).
Regarding claim 13, the combination of Yamazaki and Goto described in the discussion of claim 10 anticipates “The electronic device of claim 10, wherein an atomic ratio of indium, gallium and zinc is 1:3:6-8 in the second sub-semiconductor layer” by teaching that sublayer 108c in Fig. 3A may have an atomic ratio of 1:3:6, which lies within the claimed range (Yamazaki [0150]; also see MPEP 2131.03 I).
Regarding claim 14, the combination of Yamazaki and Goto described in the discussion of claim 10 further teaches “The electronic device of claim 10, wherein the first sub-semiconductor layer comprises indium” (Yamazaki [0150]; as noted in the discussion of claim 4 above, the first sublayer 108b is composed of an indium-gallium-zinc oxide and may have an atomic ratio of In:Ga:Zn of 1:1:1), “and the atomic percentage of indium in the second sub-semiconductor layer is less than an atomic percentage of indium in the first sub-semiconductor layer”. (Yamazaki [0150]; as pointed out in the discussion of claim 4 above, letting the ratio of In:Ga:Zn in the second sublayer 108c be 1:3:6 and that in the first sublayer 108b be 1:1:1 yields atomic percentages of In of 10% in the second sublayer and 33.3% in the first sublayer, which satisfy the new limitation introduced by this claim).
Regarding claim 15, the combination of Yamazaki and Goto described in the discussion of claim 10 further teaches “The electronic device of claim 10, wherein the first sub-semiconductor layer comprises indium, gallium and zinc, and an atomic ratio of indium, gallium and zinc is 1:1:1 in the first sub-semiconductor layer” (Yamazaki [0150]; as noted in the discussion of claim 4 above, the first sublayer 108b is composed of an indium-gallium-zinc oxide and may have an atomic ratio of In:Ga:Zn of 1:1:1).
Regarding claim 16, the combination of Yamazaki and Goto described in the discussion of claim 10 teaches “The electronic device of claim 10”, but does not teach a device “wherein a thickness of the first sub-semiconductor layer ranges from 800 Å to 2000 Å.”
However, Yamazaki does teach a thickness of sublayer 108b in Fig. 3A in the overlapping range of 3 nm to 200 nm ([0147]: “The thickness of the oxide semiconductor layer 108b is greater than or equal to 3 nm and less than or equal to 200 nm”).
It would have been obvious to one of ordinary skill in the art to modify the transistor of the combined device of Yamazaki and Goto described in the discussion of claim 10 so that the first semiconductor sublayer has a thickness within the range, 800 Å to 2000 Å (or 80 nm to 200 nm), as current case law holds that the fact that the combination of Yamazaki and Goto described in the discussion of claim 10 teaches a range of thicknesses of the first sublayer that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I).
Regarding claim 18, the combination of Yamazaki and Goto described in the discussion of claim 10 further teaches “The electronic device of claim 10, wherein the metal layer” (Fig. 1B, the lower metal layer of the stacked metal layer structure 114; also see [0187]) “electrically connects to the drain electrode” (Fig. 1B, electrode 119) “through a via of the insulating layer” (Fig. 1B, insulating layer 113).
Regarding claim 19, the combination of Yamazaki and Goto described in the discussion of claim 10 further teaches “The electronic device of claim 10, wherein the conductive layer” (Yamazaki Fig. 1B, the upper metal layer of the stacked conductive layer structure 114) “is electrically connected to the drain electrode” (Yamazaki Fig. 1B, electrode 119) “through the metal layer”.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./ Examiner, Art Unit 2818
/STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818
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