DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed on 4/22/2026 have been entered.
Response to Arguments
Applicant’s arguments regarding Claims 1 and 15 have been fully considered and are persuasive, therefore the prior art rejections of Claims 1 and 15 have been withdrawn. However, a new ground of rejection, which was necessitated by Applicant’s amendments, has been found and now follows.
In the interest of compact prosecution, the examiner notes that further description of how the semiconductor die is in physical contact with the substrate and the reasons thereof would be helpful in overcoming the prior art of record. The examiner is available for an interview at Applicant’s convenience.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 10-11, 12, 15, and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Fujisawa et al (US 2021/0066247) in view of Zanati et al (2022/0189894).
Regarding Claim 1, Fujisawa et al discloses a package device (stacked die package 300B [0036] Fig 3B), comprising:
a package substrate (substrate 310 [0036]) including a first surface (shown in annotated Fig 3B), a second surface (shown in annotated Fig 3B) opposite the first surface (shown in annotated Fig 3B), and a peripheral edge (shown in annotated Fig 3B);
a die (die 320, 330, 340, 350 [0038]) on a first inner portion (shown in annotated Fig 3B) of the first surface (shown in annotated Fig 3B) of the package substrate (310), the first inner portion (shown in annotated Fig 3B) being located a first distance away (shown in annotated Fig 3B) from the peripheral edge (shown in annotated Fig 3B) of the package substrate (310);
a plurality of first substrate interconnects (DCA interconnects 312-1, 312-2, 312-3 and interconnects 314-1, 314-2, 314-3 [0037]) on a first outer portion (shown in annotated Fig 3B) of the first surface (shown in annotated Fig 3B) of the package substrate (310), the first outer portion (shown in annotated Fig 3B) surrounding the first inner portion (shown in annotated Fig 3B), the plurality of first substrate interconnects (312-1, 312-2, 312-3, 314-1, 314-2, 314-3) being electrically coupled to the die (die 320, 330, 340, 350 [0038]);
a plurality of second substrate interconnects (interconnects 305 [0036]) on a second outer portion (shown in annotated Fig 3B) of the second surface of the package substrate (310), the second outer portion (shown in annotated Fig 3B) being a portion of the second surface (shown in annotated Fig 3B) of the package substrate (310) from the peripheral edge (shown in annotated Fig 3B) to a second distance away (shown in annotated Fig 3B) from the peripheral edge (shown in annotated Fig 3B); and
one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047]), a first end of each interconnect cage (360-1, 360-2) being coupled to one or more of the first substrate interconnects (312-1, 312-2, 312-3, 314-1, 314-2, 314-3), and each interconnect cage (360-1, 360-2) being configured to provide electrical coupling between the die (320, 330, 340, 350) and connections outside a physical boundary of the package substrate (310).
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Fujisawa et al does not disclose
wherein a lower surface of the die is in physical contact with the first surface of the package substrate.
Zanati et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a lower surface of the die (semiconductor die 2 [0060] Fig 5-6) is in physical contact with the first surface of the package substrate (redistribution layer 13 [0064]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujisawa et al to include wherein a lower surface of the die is in physical contact with the first surface of the package substrate as taught by Zenati et al in order to have better electrical connection through the substrate as well as provide greater structural support. Further, a person of ordinary skill in the art would have recognized that having a lower surface of the lowest semiconductor die in physical contact with the first surface of the semiconductor substrate would be advantageous in that an interface is not required and result in a wave transition that is self-adjusted and avoids misalignment issues with the PCB [0034] (see MPEP 2143.I(D)).
Regarding Claim 10, the combination of Fujisawa et al and Zenati et al discloses the limitations of claim 1 as explained above. The combination of Fujisawa et al and Zenati et al further discloses
further comprising: another package substrate (active surface 324 of semiconductor die 320 [0042] Fig 3B) above the package substrate (substrate 310 [0036]); and
a plurality of package-to-package connects (vias 326-1 and 326-2 [0041] Fig 3B) between and electrically coupling the package substrate (310) and the another package substrate (324).
Regarding Claim 11, the combination of Fujisawa et al and Zenati et al discloses the limitations of claim 1 as explained above. The combination of Fujisawa et al and Zenati et al further discloses
further comprising: another package substrate (active surface 324 of semiconductor die 320 [0042] Fig 3B) above the package substrate (substrate 310 [0036]);
a plurality of package-to-package connects (vias 326-1 and 326-2 [0041] Fig 3B) between the package substrate (310) and the another package substrate (324); and
a plurality of another first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B) on a first surface of the another package substrate (324),
wherein for at least one interconnect cage (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al), a first end (shown in annotated Fig 3B) of the at least one interconnect cage is coupled (electrically coupled) to one or more of the another first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B).
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Regarding Claim 12, the combination of Fujisawa et al and Zenati et al discloses the limitations of claim 1 as explained above. The combination of Fujisawa et al and Zenati et al further discloses
wherein at least one interconnect cage (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047]) is flexible (wires are considered flexible as they can bend without breaking as depicted in Fig 3B).
Regarding Claim 15, Fujisawa et al discloses a method of fabricating (method of forming a stacked memory device [0067]) a package device (stacked die package 300B [0036] Fig 3B), the method comprising:
providing a package substrate (substrate 310 [0036]) including a first surface (shown in annotated Fig 3B), a second surface (shown in annotated Fig 3B) opposite the first surface (shown in annotated Fig 3B), and a peripheral edge (shown in annotated Fig 3B);
providing a die (die 320, 330, 340, 350 [0038]) on a first inner portion (shown in annotated Fig 3B) the first surface (shown in annotated Fig 3B) of the package substrate (310), the first inner portion (shown in annotated Fig 3B) being located a first distance away (shown in annotated Fig 3B) from the peripheral edge (shown in annotated Fig 3B) of the package substrate (310);
forming a plurality of first substrate interconnects (DCA interconnects 312-1, 312-2, 312-3 and interconnects 314-1, 314-2, 314-3 [0037]) on a first outer portion (shown in annotated Fig 3B) of the first surface (shown in annotated Fig 3B) of the package substrate (310), the first outer portion (shown in annotated Fig 3B) surrounding the first inner portion (shown in annotated Fig 3B), the plurality of first substrate interconnects (312-1, 312-2, 312-3, 314-1, 314-2, 314-3) being electrically coupled to the die (320, 330, 340, 350);
forming a plurality of second substrate interconnects (interconnects 305 [0036]) on a second outer portion (shown in annotated Fig 3B) of the second surface (shown in annotated Fig 3B) of the package substrate (310), the second outer portion (shown in annotated Fig 3B) being a portion of the second surface (shown in annotated Fig 3B) of the package substrate (310) from the peripheral edge (shown in annotated Fig 3B) to a second distance away (shown in annotated Fig 3B) from the peripheral edge (shown in annotated Fig 3B); and
forming one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047]), a first end of each interconnect cage (360-1, 360-2) being coupled to one or more of the first substrate interconnects (312-1, 312-2, 312-3, 314-1, 314-2, 314-3), and each interconnect cage (360-1, 360-2) being configured to provide electrical coupling between the die (320, 330, 340, 350) and connections outside a physical boundary of the package substrate (310).
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Fujisawa et al does not disclose
wherein a lower surface of the die is in physical contact with the first surface of the package substrate.
Zanati et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a lower surface of the die (semiconductor die 2 [0060] Fig 5-6) is in physical contact with the first surface of the package substrate (redistribution layer 13 [0064]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujisawa et al to include wherein a lower surface of the die is in physical contact with the first surface of the package substrate as taught by Zenati et al in order to have better electrical connection through the substrate as well as provide greater structural support. Further, a person of ordinary skill in the art would have recognized that having a lower surface of the lowest semiconductor die in physical contact with the first surface of the semiconductor substrate would be advantageous in that an interface is not required and result in a wave transition that is self-adjusted and avoids misalignment issues with the PCB [0034] (see MPEP 2143.I(D)).
Regarding Claim 24, the combination of Fujisawa et al and Zenati et al discloses the limitations of claim 15 as explained above. The combination of Fujisawa et al and Zenati et al further discloses
further comprising: providing another package substrate (active surface 324 of semiconductor die 320 [0042] Fig 3B) above the package substrate (substrate 310 [0036]); and
forming a plurality of package-to-package connects (vias 326-1 and 326-2 [0041] Fig 3B) between and electrically coupling the package substrate (310) and the another package substrate (324).
Regarding Claim 25, the combination of Fujisawa et al and Zenati et al discloses the limitations of claim 15 as explained above. The combination of Fujisawa et al and Zenati et al further discloses
further comprising: providing another package substrate (active surface 324 of semiconductor die 320 [0042] Fig 3B) above the package substrate (substrate 310 [0036]);
forming a plurality of package-to-package connects (vias 326-1 and 326-2 [0041] Fig 3B) between the package substrate (310) and the another package substrate (324); and
forming a plurality of another first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B) on a first surface of the another package substrate (324),
wherein for at least one interconnect cage (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al), a first end (shown in annotated Fig 3B) of the at least one interconnect cage is coupled (electrically coupled) to one or more of the another first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B).
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Regarding Claim 26, the combination of Fujisawa et al and Zenati et al discloses the limitations of claim 15 as explained above. The combination of Fujisawa et al and Zenati et al further discloses
wherein at least one interconnect cage (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047]) is flexible (wires are considered flexible as they can bend without breaking as depicted in Fig 3B).
Claims 2-4 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Fujisawa et al (US 2021/0066247) in view of Zanati et al (2022/0189894), and in further view of RAORANE et al (US 2019/0341342).
Regarding Claim 2, the combination of Fujisawa et al and Zanati et al discloses the limitations of claim 2 as explained above. The combination of Fujisawa et al and Zanati et al does not directly disclose
wherein one or more of the plurality of second substrate interconnects are configured to carry high speed input output (HSIO) signals, which are signal speeds greater than a minimum speed threshold.
RAORANE et al, in the related art of semiconductor devices that include semiconductor packaging devices, discloses
wherein one or more of the plurality of substrate interconnects (high-speed input/output HSIO interconnects [0016]) are configured to carry high speed input output (HSIO) signals, which are signal speeds greater than a minimum speed threshold.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al and Zanati et al to include wherein the plurality of second substrate interconnects are configured to carry HSIO signals as taught by RAORANE et al in order to reduce cross talk [0016]. Further, a person of ordinary skill in the art would have recognized reducing cross talk between signals would optimize the electrical performance [0016] of the device (see MPEP.I(D)).
The combination of Fujisawa et al, Zanati et al, and RAORANE et al now discloses
wherein the plurality of second substrate interconnects (HSIO interconnects [0016] RAORANE et al/ interconnects 305 [0036] Fujisawa et al) are configured to carry high speed input output (HSIO) signals.
Regarding Claim 3, the combination of Fujisawa et al, Zanati et al, and RAORANE et al discloses the limitations of claim 2 as explained above. The combination of Fujisawa et al, Zanati et al, and RAORANE et al further discloses
wherein all of the plurality of second substrate interconnects (HSIO interconnects [0016] RAORANE et al/ interconnects 305 [0036] Fujisawa et al) are configured to carry high speed input output (HSIO) signals.
Regarding Claim 4, the combination of Fujisawa et al, Zanati et al, and RAORANE et al discloses the limitations of claim 2 as explained above. The combination of Fujisawa et al, Zanati et al, and RAORANE et al further discloses
wherein one or more first substrate interconnects (DCA interconnects 312-1, 312-2, 312-3 and interconnects 314-1, 314-2, 314-3 [0037] Fujisawa et al) are not configured to carry HSIO signals.
Regarding Claim 16, the combination of Fujisawa et al and Zanati et al discloses the limitations of claim 15 as explained above. The combination of Fujisawa et al and Zanati et al does not directly disclose
wherein one or more of the plurality of second substrate interconnects are configured to carry high speed input output (HSIO) signals, which are signal speeds greater than a minimum speed threshold.
RAORANE et al, in the related art of semiconductor devices that include semiconductor packaging devices, discloses
wherein one or more of the plurality of substrate interconnects (high-speed input/output HSIO interconnects [0016]) are configured to carry high speed input output (HSIO) signals, which are signal speeds greater than a minimum speed threshold.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al and Zanati et al to include wherein one or more of the plurality of second substrate interconnects are configured to carry HSIO signals as taught by RAORANE et al in order to reduce cross talk [0016]. Further, a person of ordinary skill in the art would have recognized reducing cross talk between signals would optimize the electrical performance [0016] of the device (see MPEP.I(D)).
The combination of Fujisawa et al, Zanati et al, and RAORANE et al now discloses
wherein one or more of the plurality of second substrate interconnects (HSIO interconnects [0016] RAORANE et al/ interconnects 305 [0036] Fujisawa et al) are configured to carry high speed input output (HSIO) signals.
Regarding Claim 17, the combination of Fujisawa et al, Zanati et al, and RAORANE et al discloses the limitations of claim 17 as explained above. The combination of Fujisawa et al, Zanati et al, and RAORANE et al further discloses
wherein all of the plurality of second substrate interconnects (HSIO interconnects [0016] RAORANE et al/ interconnects 305 [0036] Fujisawa et al) are configured to carry high speed input output (HSIO) signals.
Regarding Claim 18, the combination of Fujisawa et al, Zanati et al, and RAORANE et al discloses the limitations of claim 16 as explained above. The combination of Fujisawa et al, Zanati et al, and RAORANE et al further discloses
wherein one or more first substrate interconnects (DCA interconnects 312-1, 312-2, 312-3 and interconnects 314-1, 314-2, 314-3 [0037] Fujisawa et al) are not configured to carry HSIO signals.
Claims 5-8, and 19-22 are rejected under 35 U.S.C. 103 as being unpatentable over Fujisawa et al (US 2021/0066247) in view of Zanati et al (2022/0189894), and in further view of Ding et al (US 2021/0057326).
Regarding Claim 5, the combination of Fujisawa et al and Zanati et al discloses the limitations of claim 1 as explained above. The combination of Fujisawa et al and Zanati et al does not directly disclose
further comprising: a printed circuit board (PCB) including a first surface, a second surface opposite the first surface, and a peripheral edge, the first surface of the PCB facing the second surface of the package substrate; and
a plurality of PCB interconnects on the first surface of the PCB, wherein the plurality of second substrate interconnects are electrically coupled to connections of the PCB.
Ding et al, in the related art of semiconductor devices that include packaging, discloses
a printed circuit board (PCB) (board 680 [0043] Fig 6) including a first surface (shown in annotated Fi 6), a second surface (shown in annotated Fig 6) opposite the first surface (shown in annotated Fig 6), and a peripheral edge (shown in annotated Fig 6), the first surface of the PCB (680) facing the second surface (shown in annotated Fig 6) of the package substrate (RDL 519 [0040] shown in annotated Fig 6); and
a plurality of PCB interconnects (solder bumps 613 [0043] Fig 6) on the first surface (shown in annotated Fig 6) of the PCB (680).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al and Zanati et al to include a PCB board as taught by Ding et al in order to allow for electrical current supplied from the electronic system [0045] to reach the package substrate. Further, a person of ordinary skill in the art would have recognized that a printed circuit board would be advantageous in providing electrical power to one or more semiconductor die and would improve the electrical functioning of the device (see MPEP 2143.I(D)).
The combination of Fujisawa et al, Zanati et al, and Ding et al now discloses
wherein the plurality of second substrate interconnects (interconnects 305 Fig 3B Fujisawa et al) are electrically coupled to connections of the PCB (680 Fig 6 Ding et al).
Regarding Claim 6, the combination of Fujisawa et al, Zanati et al, and Ding et al discloses the limitations of claim 5 as explained above. The combination of Fujisawa et al, Zanati et al, and Ding et al further discloses
wherein the one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al) includes a first interconnect cage (360-1Fujisawa et al) whose first end (shown in annotated Fig 3B Fujisawa et al) is connected (electrically connected) to the one or more first substrate interconnects (DCA interconnects 312-1, 312-2, 312-3 and interconnects 314-1, 314-2, 314-3 [0037] Fig 3B Fujisawa et al) and whose second end (shown in annotated Fig 3B Fujisawa et al) is connected (electrically connected) to one or more PCB interconnects (interconnects 305 Fig 3B Fujisawa et al/613 Fig 6 Ding et al).
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Regarding Claim 7, the combination of Fujisawa et al, Zanati et al, and Ding et al discloses the limitations of claim 5 as explained above. The combination of Fujisawa et al, Zanati et al, and Ding et al further discloses
further comprising: another package substrate (active surface 324 of semiconductor die 320 [0042] Fig 3B Fujisawa et al) on the first surface (shown above in annotated Fig 6 Ding et al) of the PCB (680 Fig 6 Ding et al); and
a plurality of another first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al) on a first surface (shown in annotated Fig 3B Fujisawa et al) of the another package substrate (324 Fig 3B Fujisawa et al),
wherein the one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al) includes another interconnect cage (360-2 Fig 3B Fujisawa et al) whose first end (shown in Fig 3B Fujisawa et al) is connected (electrically connected) to one or more of the first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al), and
wherein a second end (shown in annotated Fig 3B Fujisawa et al) of the second interconnect cage (360-2 Fig 3B Fujisawa et al) is connected (electrically connected) to one or more of the another first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al).
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Regarding Claim 8, the combination of Fujisawa et al, Zanati et al, and Ding et al discloses the limitations of claim 5 as explained above. The combination of Fujisawa et al, Zanati et al, and Ding et al further discloses
wherein the one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al) includes a third interconnect cage (360-3 Fig 3B Fujisawa et al) whose first end (shown in annotated Fig 3B Fujisawa et al) is connected (electrically connected) to the one or more first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al), and wherein a second end (shown in annotated Fig 3B Fujisawa et al) of the third interconnect cage (360-3) is configured to carry signals to or receive signals from one or more devices (voltage source, passive devices, display, audio, input devices [0049] Fig 6 Ding et al/controller, address bus 120, data bus 122, control signal bus 124, dual inline memory module DIMM [0015]-[0017] Fig 1 Fujisawa et al) physically beyond the PCB (680 Fig 6 Ding et al).
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Regarding Claim 19, the combination of Fujisawa et al and Zanati et al discloses the limitations of claim 15 as explained above. The combination of Fujisawa et al and Zanati et al does not directly disclose
further comprising: providing a printed circuit board (PCB) including a first surface, a second surface opposite the first surface, and a peripheral edge, the first surface of the PCB facing the second surface of the package substrate; and
forming a plurality of PCB interconnects on the first surface of the PCB, wherein the plurality of second substrate interconnects are electrically coupled to connections of the PCB.
Ding et al, in the related art of semiconductor devices that include packaging, discloses
a printed circuit board (PCB) (board 680 [0043] Fig 6) including a first surface (shown in annotated Fi 6), a second surface (shown in annotated Fig 6) opposite the first surface (shown in annotated Fig 6), and a peripheral edge (shown in annotated Fig 6), the first surface of the PCB (680) facing the second surface (shown in annotated Fig 6) of the package substrate (RDL 519 [0040] shown in annotated Fig 6); and
a plurality of PCB interconnects (solder bumps 613 [0043] Fig 6) on the first surface (shown in annotated Fig 6) of the PCB (680).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al and Zanati et al to include a PCB board as taught by Ding et al in order to allow for electrical current supplied from the electronic system [0045] to reach the package substrate. Further, a person of ordinary skill in the art would have recognized that a printed circuit board would be advantageous in providing electrical power to one or more semiconductor die and would improve the electrical functioning of the device (see MPEP 2143.I(D)).
The combination of Fujisawa et al, Zanati et al, and Ding et al now discloses
wherein the plurality of second substrate interconnects (interconnects 305 Fig 3B Fujisawa et al) are electrically coupled to connections of the PCB (680 Fig 6 Ding et al).
Regarding Claim 20, the combination of Fujisawa et al, Zanati et al, and Ding et al discloses the limitations of claim 19 as explained above. The combination of Fujisawa et al, Zanati et al, and Ding et al further discloses
wherein the one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al) includes a first interconnect cage (360-1Fujisawa et al) whose first end (shown in annotated Fig 3B Fujisawa et al) is connected (electrically connected) to the one or more first substrate interconnects (DCA interconnects 312-1, 312-2, 312-3 and interconnects 314-1, 314-2, 314-3 [0037] Fig 3B Fujisawa et al) and whose second end (shown in annotated Fig 3B Fujisawa et al) is connected (electrically connected) to one or more PCB interconnects (interconnects 305 Fig 3B Fujisawa et al/613 Fig 6 Ding et al).
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Regarding Claim 21, the combination of Fujisawa et al, Zanati et al, and Ding et al discloses the limitations of claim 19 as explained above. The combination of Fujisawa et al, Zanati et al, and Ding et al further discloses
further comprising: providing another package substrate (active surface 324 of semiconductor die 320 [0042] Fig 3B Fujisawa et al) on the first surface (shown above in annotated Fig 6 Ding et al) of the PCB (680 Fig 6 Ding et al); and
a plurality of another first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al) on a first surface (shown in annotated Fig 3B Fujisawa et al) of the another package substrate (324 Fig 3B Fujisawa et al),
wherein the one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al) includes another interconnect cage (360-2 Fig 3B Fujisawa et al) whose first end (shown in annotated Fig 3B Fujisawa et al) is connected (electrically connected) to one or more of the first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al), and
wherein a second end (shown in annotated Fig 3B Fujisawa et al) of the second interconnect cage (360-2 Fig 3B Fujisawa et al) is connected (electrically connected) to one or more of the another first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al).
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Regarding Claim 22, the combination of Fujisawa et al, Zanati et al, and Ding et al discloses the limitations of claim 19 as explained above. The combination of Fujisawa et al, Zanati et al, and Ding et al further discloses
wherein the one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al) includes a third interconnect cage (360-3 Fig 3B Fujisawa et al) whose first end (shown in annotated Fig 3B Fujisawa et al) is connected (electrically connected) to the one or more first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al), and wherein a second end (shown in annotated Fig 3B Fujisawa et al) of the third interconnect cage (360-3) is configured to carry signals to or receive signals from one or more devices (voltage source, passive devices, display, audio, input devices [0049] Fig 6 Ding et al/controller, address bus 120, data bus 122, control signal bus 124, dual inline memory module DIMM [0015]-[0017] Fig 1 Fujisawa et al) physically beyond the PCB (680 Fig 6 Ding et al).
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Claims 9 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Fujisawa et al (US 2021/0066247) in view of Zanati et al (2022/0189894) and Ding et al (US 2021/0057326), and in further view of Yoon et al (US 2018/0013219).
Regarding Claim 9, the combination of Fujisawa et al, Zanati et al, and Ding et al discloses the limitations of claim 5 as explained above. The combination of Fujisawa et al, Zanati et al, and Ding et al further discloses
wherein the one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al) includes a fourth interconnect cage (360-4 Fig 3B Fujisawa et al) whose first end (shown in annotated Fig 3B Fujisawa et al) is connected to the one or more first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al).
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The combination of Fujisawa et al, Zanati et al, and Ding et al does not directly disclose
the connector configured to mate with a complementary connector, the connector being one of male and female, and the complementary connector being the other of male and female.
Yoon et al, in the related art of semiconductor devices that include semiconductor packaging devices, discloses
the connector (female connection member 110 and male connection member 120 [0032] Fig 6) configured to mate with a complementary connector, the connector being one of male and female, and the complementary connector being the other of male and female.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al, Zanati et al, and Ding et al to include a male connection member and a female connection member as taught by Yoon et al in order to electrically and physically connect between printed circuit boards and/or components mounted on the printed circuit board [0032]. Further, a person of ordinary skill in the art would have recognized that having physical and electrical connections facilitated in the device would optimize and improve the electrical functioning capability of the device (see MPEP 2143.I(D)).
The combination of Fujisawa et al, Zanati et al, Ding et al, and Yoon et al now discloses
wherein a second end (shown above in annotated Fig 3B Fujisawa et al) of the fourth interconnect cage (360-4 Fig 3B Fujisawa et al) is connected to a connector (110 and 120 Fig 6 Yoon et al) formed on the first surface of the PCB (680 Fig 6 Ding et al).
Regarding Claim 23, the combination of Fujisawa et al, Zanati et al, and Ding et al discloses the limitations of claim 19 as explained above. The combination of Fujisawa et al, Zanati et al, and Ding et al further discloses
wherein the one or more interconnect cages (wires 360-1,360-2, 360-3, 360-4, 360-5, 360-6 [0045]-[0047] Fig 3B Fujisawa et al) includes a fourth interconnect cage (360-4 Fig 3B Fujisawa et al) whose first end (shown in annotated Fig 3B Fujisawa et al) is connected to the one or more first substrate interconnects (vias 326-1 and 326-2 [0041] Fig 3B Fujisawa et al).
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The combination of Fujisawa et al, Zanati et al, and Ding et al does not directly disclose
the connector configured to mate with a complementary connector, the connector being one of male and female, and the complementary connector being the other of male and female.
Yoon et al, in the related art of semiconductor devices that include semiconductor packaging devices, discloses
the connector (female connection member 110 and male connection member 120 [0032] Fig 6) configured to mate with a complementary connector, the connector being one of male and female, and the complementary connector being the other of male and female.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al, Zanati et al, and Ding et al to include a male connection member and a female connection member as taught by Yoon et al in order to electrically and physically connect between printed circuit boards and/or components mounted on the printed circuit board [0032]. Further, a person of ordinary skill in the art would have recognized that having physical and electrical connections facilitated in the device would optimize and improve the electrical functioning capability of the device (see MPEP 2143.I(D)).
The combination of Fujisawa et al, Zanati et al, Ding et al, and Yoon et al now discloses
wherein a second end (shown above in annotated Fig 3B Fujisawa et al) of the fourth interconnect cage (360-4 Fig 3B Fujisawa et al) is connected to a connector (110 and 120 Fig 6 Yoon et al) formed on the first surface of the PCB (680 Fig 6 Ding et al).
Claims 13 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Fujisawa et al (US 2021/0066247) in view of Zanati et al (2022/0189894), and in further view of Yu et al (US 2021/0407942).
Regarding Claim 13, the combination of Fujisawa et al and Zanati et al discloses the limitations of claim 1 as explained above. The combination of Fujisawa et al and Zanati et al does not directly disclose
further comprising: a plurality of power distribution network (PDN) connections on a second inner portion of the package substrate, the second inner portion being surrounded by the second outer portion, the plurality of PDN connections being configured to carry power and/or ground to the die.
Yu et al, in the related art of semiconductor devices that include packaged semiconductor devices, discloses
further comprising: a plurality of power distribution network (PDN) connections (semi-global interconnect 100A [0044], PDN layer 100B [0061], embedded power component layer 100C [0049], semi-global interconnect 100D [0049], conductive pads 136 [0052] and 186 [0055], semi-global interconnect 160 [0053], device layer 153 [0053], TSVs 172 [0054], global interconnect 190 [0058], and external connectors 191 [0059 Fig 19A) on a second inner portion (shown in annotated Fig 19A) of the package substrate (semiconductor substrate 72 and device layer 73 [0035]), the second inner portion (shown in annotated Fig 19A) being surrounded by the second outer portion (shown in annotated Fig 19A), the plurality of PDN connections (100A-D, 136, 186, 160, 153, 172, 190, 191) being configured to carry power and/or ground to the die (top chip 55 [0060]).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al and Zanati et al to include a plurality of PDN interconnects as taught by Yu et al in order to regulate voltage to the PDN layer which may be coupled to the power component devices [0061]. Further, a person of ordinary skill in the art would have recognized that having a plurality of PDN interconnects would allow for better facilitation of electrical power to the package substrate which would optimize the electrical functional capabilities of the device (see MPEP 2143.I(D)).
Regarding Claim 27, the combination of Fujisawa et al and Zanati et al discloses the limitations of claim 15 as explained above. The combination of Fujisawa et al and Zanati et al does not directly disclose
further comprising: forming a plurality of power distribution network (PDN) connections on a second inner portion of the package substrate, the second inner portion being surrounded by the second outer portion, the plurality of PDN connections being configured to carry power and/or ground to the die.
Yu et al, in the related art of semiconductor devices that include packaged semiconductor devices, discloses
further comprising: forming a plurality of power distribution network (PDN) connections (semi-global interconnect 100A [0044], PDN layer 100B [0061], embedded power component layer 100C [0049], semi-global interconnect 100D [0049], conductive pads 136 [0052] and 186 [0055], semi-global interconnect 160 [0053], device layer 153 [0053], TSVs 172 [0054], global interconnect 190 [0058], and external connectors 191 [0059 Fig 19A) on a second inner portion (shown in annotated Fig 19A) of the package substrate (semiconductor substrate 72 and device layer 73 [0035]), the second inner portion (shown in annotated Fig 19A) being surrounded by the second outer portion (shown in annotated Fig 19A), the plurality of PDN connections (100A-D, 136, 186, 160, 153, 172, 190, 191) being configured to carry power and/or ground to the die (top chip 55 [0060]).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al and Zanati et al to include a plurality of PDN interconnects as taught by Yu et al in order to regulate voltage to the PDN layer which may be coupled to the power component devices [0061]. Further, a person of ordinary skill in the art would have recognized that having a plurality of PDN interconnects would allow for better facilitation of electrical power to the package substrate which would optimize the electrical functional capabilities of the device (see MPEP 2143.I(D)).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Fujisawa et al (US 2021/0066247) in view of Zanati et al (2022/0189894), and in further view of Ong et al (US 2021/0384133).
Regarding Claim 14, the combination of Fujisawa et al and Zanati et al discloses the limitations of claim 1 as explained above. The combination of Fujisawa et al and Zanati et al does not directly disclose
wherein the package device is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.
Ong et al, in the related art of semiconductor devices that include packaging, discloses
wherein the package device is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle (a flash memory, digital memory, graphics processor, crypto processor, chipset, antenna, display, touchscreen display, touchscreen controller, battery, audio codec, power amplifier, global positioning system, compass, Geiger counter, accelerometer, gyroscope, speaker, camera, mass storage device, DVD, and so forth [0089]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fujisawa et al and Zanati et al to include wherein the package device is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle as taught by Ong et al in order to be a certification mark for products that pass conformity and interoperability tests for the IEEE 502.16 standards [0090]. Further, a person of ordinary skill in the art would have recognized that having the package device is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. CHEAH et al (US 2021/0384116) which discloses scaling performance of high speed input output interfaces [0002], and Grober et al (US 2019/0306988) which discloses an integrated circuit substrate [0039].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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