Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 18 December, 2025 has been entered.
Response to Amendment
Claims 1-19 and 21 remain pending in the application. Examiner acknowledges Applicant’s remarks (see page 8 of document filed 18 December 2025). Claims 1-19 and 21 are rejected upon further search and consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steinmetz et al. (US 2022/0197833) (hereafter Steinmetz), in view of Sinclair (US 2016/0188206), Jung et al. (US 2024/0264957, see foreign application priority date) (hereafter Jung), Nowoczynski et al (U.S. Patent Pub. No. 2014/0108723), hereinafter referred to as Nowoczynski, and Byun (U.S. Patent Pub. No. 2020/0349071)
As per claims 1, 8 and 15, Steinmetz teaches a method for data storage, the method comprising: receiving a first request at a storage device ([0034], wherein the memory sub-system controller receives commands and converts them into instructions or appropriate commands to achieve the desired access), the first request being associated with a first protocol that is a memory protocol ([0037], lines 15-20 describing wherein the memory devices can be communicated with using the specified CXL protocols). Steinmetz also teaches a data placement scheme storing data from a first application and data from a second application in separate contiguous physical locations ([0065], lines 2-8 disclose assigning persistent memory region address ranges (e.g. a contiguous area of physical memory made up of sequential addresses, as the PMR is physical storage (see Paragraph 0064 explaining physical aspects of the PMR and preceding discussion of PMR in reference)) to different applications to benefit from specific performance parameters like increased access priority for stored data ([0065], lines 12-13)). Additionally, Steinmetz teaches causing storage requests to comply with a data placement scheme of the storage device ([0059], lines 6-11 disclose the SSD (storage device) handling errors related to data placement from the CXL side to the SSD side independently, e.g. causing requests to comply with a data placement scheme).
Steinmetz does not explicitly teach converting, by the storage device, cache-coherent address information from the first request to logical block address (LBA) information to comply with a flexible data placement scheme;
determining, by the storage device, a first group of contiguous physical block addresses associated with the first request and associated with a first application, based on the flexible data placement scheme; and
performing a first memory operation at the first group, based on the first request.
However, Sinclair teaches determining, by the storage device, a first group of contiguous physical block addresses associated with the first request and associated with a first application, based on a data placement scheme (fig. 7, 709, see [0048] relating logical blocks with physical blocks which include a plurality of pages); and
performing a first memory operation at the first group, based on the first request (fig. 7, 710).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the address conversion of Sinclair with the storage device of Steinmetz because it provides a means of assigning logical address units to physical block addresses at any die rather than assigning logical address units exclusively to a subset pf physical spaces known as banks and therefore do not accumulate waiting for a busy memory bank to become idle ([0025], lines 12-15).
The combination does not explicitly teach converting, by the storage device, cache-coherent address information from the first request to logical block address (LBA) information to comply with a flexible data placement scheme
However, Jung teaches converting address information associated with the first request to logical block address (LBA) information (see [0067] describing how protocols of CXL may integrate the PCIe storage into a cache coherent memory space; [0066]describing how PCIe storage includes NAND/SSD; [0086] describing the address conversion).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the converting of Jung with the method of the combination of Steinmetz and Sinclair because it allows for generating much larger memory pools than existing memory expansion ([0067]) and converts address information into an address an SSD controller may understand ([0086]).
While this combination does teach converting address information to LBA information and has capability for causing data to comply with a data placement scheme, it does not teach causing data to comply with a flexible data placement scheme. However, Nowoczynski teaches using flexible data placement for cache data (Paragraph 0055, lines 1-2), which includes locating application data in separate contiguous locations (Paragraph 0008, lines 16-19 objective of invention is to reduce noncontiguous physical allocation of contiguous logical data segments; Paragraph 0041, lines 15-17 requests are written contiguously; Paragraph 0055, lines 19-21 data is targeted to the same file, within an offset) and erasing individual data items without affecting other application data (Paragraph 0050, lines 13-20 data items can be individually pruned and removed) as defined in the instant specification. Additionally, Nowoczynski maps data using a hash table to logically segment data items (Paragraph 0045, lines 6-10), meaning it also converts address information to some logical information. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Nowoczynski in order to flexibly manage cache and reduce the amount of metadata required to manage cached data (Paragraph 0018, lines 1-2).
The previously cited references do not teach limitations relating to configuration requests for dividing physical storage, however Byun teaches an embodiment wherein [a] storage device is configured to receive configuration requests, from an external source, to divide a physical area of the storage device into different groups (¶ 0028, host may request division of the physical storage area) in accordance with the flexible data placement scheme (¶ 0029-0030, information on data placement is collected and utilized for space division, which would allow operation in accordance with the flexible data placement scheme of other cited references by one of ordinary skill in the art), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Byun in order to separate physical address groups of a storage device and potentially benefit from improved efficiency and speed through separate management of storage groups (¶ 0095).
As per claims 2, 9 and 16, Steinmetz teaches wherein the determining comprises checking a field of the first request, checking a bit of the first request, or checking a configuration of the storage device ([0046], lines 7-10 wherein the second interface can be used to discover capability and detect a CXL memory protocol and/or CXL.cache protocol capable memory region).
As per claims 3, 10 and 17, Steinmetz teaches wherein:
the first group is associated with a first area (of a storage device) (fig. 5, each die 510 is a separate group); and
the storage device comprises a second group associated with a second area of contiguous physical block addresses that are separated from the first group and associated with a second application (fig. 5, wherein the NAND dies in a different channel are the second group; these NAND dies have the same configuration as the NAND in the first group as described above).
As per claims 4, 11 and 18, Steinmetz teaches:
receiving a configuration request (at the storage device) ([0040]); and
dividing physical block addresses of a storage device into one or more groups of contiguous physical block addresses, the one or more groups comprising the first group ([0043], [0045] wherein the configuration command allocates space for PMR and this includes 0-15 MB to a first port and 16-32 MB to a second port).
As per claims 5, 12 and 19, the combination of Steinmetz and Sinclair teaches:
performing the first memory operation based on the LBA information (Sinclair teaches accessing memory using a LBA); and
receiving a second request associated with a second protocol that is different from the first protocol (at the storage device), the second request including information identifying a second group of contiguous physical block addresses associated with the second request and associated with a second application (Steinmetz teaches the use of CXL.io for block storage; see [0056], lines 7-11).
As per claims 6, 13 and 20, Steinmetz teaches wherein:
the first protocol is a cache-coherent protocol ([0056] wherein the first protocol of CXL.mem for cache coherent protocol); and
the second protocol is a storage protocol CXL.io for block storage; see [0056], lines 7-11).
As per claims 7 and 14, the combination of Steinmetz, Sinclair, Jung, and Nowoczynski teaches using flexible data placement for cache data (Paragraph 0055, lines 1-2) and teaches wherein the storage device is configured to:
track grouping parameters associated with the data placement configuration (Sinclair, 712 and 718 wherein the tables are used to track placement wherein the parameters are the addresses); and
receive requests in accordance with the first protocol and in accordance with a second protocol that is different from the first protocol (Steinmetz [0056], wherein the PMR can be accessible over CXL.mem and NVMe is accessible over CXL.io);
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Steinmetz in view of Sinclair, Jung, Nowoczynski, Byun and Jin et al (U.S. Patent Pub. No. 2021/0056023), hereinafter referred to as Jin.
The previously cited references teach the method of claim 1. They do not teach the remaining limitations of claim 21. However, Jin teaches deleting, by the storage device, the data from the first application; and maintaining the data from the second application (Paragraph 0113), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Jin in order to delete individual application data and implement functions of a memory controller having improved reliability (Paragraph 0006).
Response to Arguments
Applicant’s arguments (see page 8 of document filed 18 December 2025) were considered but are moot with regards to the amended claims due to the inclusion of new reference Byun. The amended independent claims include a modified limitation from claims 7 and 14 that was previously rejected using the teachings of reference Steinmetz. Applicant’s arguments (see page 10 of response) with respect to the teachings of Steinmetz in regard to the modified limitation was found persuasive. However, the modified limitation, and therefore the amended claim, have been rejected upon further search and consideration using teachings from new reference Byun as shown in the updated rejection of independent claims 1, 8, and 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/ Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139