DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 16 and 20 have been amended. Claims 2-3 and 19 remain cancelled. Claims 21-23 have been added. Claims 1, 4-18 and 20-23 remain pending and are ready for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 8th, 2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 23 objected to because of the following informalities: Claim 23 depends upon claim 2, which has been cancelled. The examiner is interpreting claim 23 as dependent upon independent claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-6, 8-9, 15-18 and 20-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Simionescu et al. (US Publication No. 2015/0286438 -- "Simionescu") in view of Liu et al. (US Publication No. 2009/0165008 – “Liu”).
Regarding claim 1, Simionescu teaches A computer system, comprising: a host; and a storage device having: a host interface in communication with the host; a controller; non-volatile storage media; and firmware containing instructions executable by the controller; (Simionescu paragraph [0058], The storage controller 200 includes one or more processors such as the processor 210, a memory element 220, host interface 230 and device interface 240. The processor 210 and the memory element 220 communicate via a bus illustrated with a two-way arrow. The memory 220 or the firmware 235 includes an I/O cache 236 for recording I/O operations or data transfers between the primary data store 260 and the host system 100) wherein the host transmits a sequence of commands to the storage device; (Simionescu paragraph [0020], A data storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands) wherein the storage device examines a subset of the commands to determine whether or not data items identified in the subset are addressed sequentially (Simionescu paragraph [0021], monitoring a stream of write commands to determine a queue depth, whether the target addresses are sequential. The write commands are determined to a specific queue depth to be sequential or not sequential. Simionescu paragraph [0049], the storage controller firmware and/or a data storage driver are modified to detect sequential command streams for a data volume. The analysis of sequential commands is performed for a specific data volume) and optimizes processing of at least a portion of the sequence of commands based on a result of a determination of whether or not data items identified in the subset are addressed sequentially (Simionescu paragraph [0043], Based on one or more characteristics associated with the type of flash-based storage elements ... I/O queue depth, and in some cases I/O sizes, a data storage driver determines when it is proper to change the mode of operation to optimize the performance of write commands issued from the host computer to the data storage controller. Based on the results of the determination, the process of executing the commands is optimized. Specifically, Simionescu paragraph [0050], A data structure for analyzing a stream of I/O commands includes a count of commands analyzed, a count of non-sequential commands and a logical block address for the last write operation. A write bypass threshold size is set to K bytes, where K is an integer. A second threshold defines a minimum number of commands to initiate a cache bypass. The system has a specified threshold value of sequential commands before the system is optimized for processing sequential commands by initializing and utilizing a cache bypass).
Simionescu does not teach wherein the storage device sorts, by the controller executing the firmware, a subset of the commands according to address.
However, Liu teaches wherein the storage device sorts, by the controller executing the firmware, a subset of the commands according to address (Liu paragraph [0034], Please refer to FIG. 2 and FIGS. 6A and 6B which depict a diagram illustrating an example of sorting the commands within a time slice consistent with the present invention. In FIG. 6A, according to the arrival time stamp, four commands are in this time slice, they are: host system 210a (H1) reading address "10", host system 210b (H2) reading address "1000", host system 210a (H1) reading address "20", and host system 210b (H2) reading address "2000". In FIG. 6B, after sorting the four commands in this time slice according to the addresses to be accessed, the commands are sorted as the following order: host system 210a (H1) reading address "10", host system 210a (H1) reading address "20", host system 210b (H2) reading address "1000", and host system 210b (H2) reading address "2000". The storage device may sort commands according to addresses of the commands, which can be done in particular command subsets (i.e., command groups) as described in Liu paragraph [0040], In step S706, sorting the commands in each command groups according to the data addresses associated with the commands).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Simionescu with those of Liu. Liu teaches specifically sorting commands in a subset according to the command address, which can allow for mor efficient command operation based on performing sequential operations grouped together in a subset (i.e., see Liu paragraph [0009], The command groups from the sorting module are stored in a command-group pool, wherein each of the command groups has at least one command. The picker unit picks one of the command groups from the command-group pool. The decoder decodes the commands within the picked command group according to the data addresses those would be accessed by the commands. The cache unit stores the data corresponding to the data addresses which are previously accessed by the previous commands. If the data being accessed by the current commands have the same addresses as the data previously accessed by the previous commands, the previously accessed data in the cache unit are transmitted to the host systems directly. If the data being accessed by the current commands have the different addresses from the data previously accessed by the commands, the command executer unit executes the current commands from the decoder and transmits the data at the addresses associated with the executed current commands to the host systems. And meanwhile, the cache unit is updated with the data at the addresses associated with the commands).
Regarding claim 4, Simionescu in view of Liu teaches The computer system of claim 2, wherein the storage device optimizes processing of commands following the subset based on the result of the determination of whether or not data items identified in the subset are addressed sequentially (Simionescu paragraph [0050], A threshold number of non-sequential requests are permitted before directing the storage controller to break or change from a cache bypass mode. The system continues to optimize processing assuming the new commands are sequential until a specific number of non-sequential commands occurs).
Regarding claim 5, Simionescu in view of Liu teaches The computer system of claim 4, wherein the processing of the commands following the subset is optimized based on the result of the determination of whether or not data items identified in the subset are addressed sequentially without determining whether or not the commands following the subset address data items sequentially (Simionescu paragraph [0050], A threshold number of non-sequential requests are permitted before directing the storage controller to break or change from a cache bypass mode. Similar to claim 4, the system continues to optimize processing assuming the new commands are sequential (or non-sequential) based on the result that occurred when analyzing the specified number of commands, as described in claims 1/2).
Regarding claim 6, Simionescu in view of Liu teaches The computer system of claim 2, wherein the storage device sorts the commands in the subset according to address to make the determination of whether or not data items identified in the subset are addressed sequentially (Simionescu paragraph [0020], the device driver compares the queue depth and under some circumstances data characteristics in the I/O commands to respective thresholds and configures the data storage controller to process the stream of I/O commands with a first path or an alternative path in the data storage controller based on a result of the comparison(s). For a logical volume supported by storage devices arranged in RAID 5, the device driver performs similar comparisons and uses the results to direct the data storage controller to use a write back or a write through mode of operation based on the result. The commands are organized by characteristics such as logical address to determine if they are sequential).
Regarding claim 8, Simionescu in view of Liu teaches The computer system of claim 1, further comprising: a communication bus coupled between the host and the storage device (Simionescu paragraph [0022], The host bus adapter is coupled to the host computer. The host bus adapter includes a data storage controller supported by a cache. The set of flash-based data storage devices are exposed to the host computer as a single or logical data volume and are managed by the data storage controller as a redundant array of inexpensive disks).
Regarding claim 9, Simionescu in view of Liu teaches The computer system of claim 8, wherein the communication bus is a peripheral component interconnect express bus (Simionescu paragraph [0059], The driver 500 and the host interface 230 communicate with each other using the PCIe communication protocol).
Regarding claim 15, Simionescu further teaches The computer system of claim 1, wherein the sequence of commands read data items from the non-volatile storage media of the storage device (Simionescu paragraph [0005], The RCBs comprise data that RAID controller 10 has frequently read from storage array 12 in response to read requests from host system 14. Caching frequently requested data is more efficient than reading the same data from storage array 12 each time host system 14 requests it. The system performs the sequence of commands for read operations).
Regarding claim 16, Simionescu further teaches A method implemented in a computer system, the method comprising: receiving, in a storage device coupled to a host, a sequence of commands submitted from the host, (Simionescu paragraph [0020], A data storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands) the storage device having: a host interface in communication with the host; a controller; non-volatile storage media; and firmware containing instructions executable by the controller; (Simionescu paragraph [0058], The storage controller 200 includes one or more processors such as the processor 210, a memory element 220, host interface 230 and device interface 240. The processor 210 and the memory element 220 communicate via a bus illustrated with a two-way arrow. The memory 220 or the firmware 235 includes an I/O cache 236 for recording I/O operations or data transfers between the primary data store 260 and the host system 100. Also see Simionescu paragraph [0060], The processor 210 is a hardware device for executing firmware and or software stored in the memory 220, which can be supported by a read-only memory element. The processor 210 can be constructed in accordance with a custom made or a commercially available integrated-circuit based processor, or can even be a standalone central processing unit (CPU); an auxiliary processor among several processors associated with PCIe compliant device; a semiconductor-based microprocessor (in the form of a microchip or chip set); or generally any device for executing software instructions stored in the memory 220) examining, by the controller executing the firmware, a subset of the commands to determine whether or not data items identified in the subset are addressed sequentially; (Simionescu paragraph [0021], monitoring a stream of write commands to determine a queue depth, whether the target addresses are sequential. The write commands are determined to a specific queue depth to be sequential or not sequential. Simionescu paragraph [0049], the storage controller firmware and/or a data storage driver are modified to detect sequential command streams for a data volume. The analysis of sequential commands is performed for a specific data volume) and optimizing, by the controller executing the firmware, processing of at least a portion of the sequence of commands based on a result of a determination of whether or not data items identified in the subset are addressed sequentially (Simionescu paragraph [0043], Based on one or more characteristics associated with the type of flash-based storage elements ... I/O queue depth, and in some cases I/O sizes, a data storage driver determines when it is proper to change the mode of operation to optimize the performance of write commands issued from the host computer to the data storage controller. Based on the results of the determination, the process of executing the commands is optimized. Specifically, Simionescu paragraph [0050], A data structure for analyzing a stream of I/O commands includes a count of commands analyzed, a count of non-sequential commands and a logical block address for the last write operation. A write bypass threshold size is set to K bytes, where K is an integer. A second threshold defines a minimum number of commands to initiate a cache bypass. The system has a specified threshold value of sequential commands before the system is optimized for processing sequential commands by initializing and utilizing a cache bypass).
Simionescu does not teach wherein the storage device sorts, by the controller executing the firmware, a subset of the commands according to address.
However, Liu teaches sorting, by the controller executing the firmware, a subset of the commands according to address (Liu paragraph [0034], Please refer to FIG. 2 and FIGS. 6A and 6B which depict a diagram illustrating an example of sorting the commands within a time slice consistent with the present invention. In FIG. 6A, according to the arrival time stamp, four commands are in this time slice, they are: host system 210a (H1) reading address "10", host system 210b (H2) reading address "1000", host system 210a (H1) reading address "20", and host system 210b (H2) reading address "2000". In FIG. 6B, after sorting the four commands in this time slice according to the addresses to be accessed, the commands are sorted as the following order: host system 210a (H1) reading address "10", host system 210a (H1) reading address "20", host system 210b (H2) reading address "1000", and host system 210b (H2) reading address "2000". The storage device may sort commands according to addresses of the commands, which can be done in particular command subsets (i.e., command groups) as described in Liu paragraph [0040], In step S706, sorting the commands in each command groups according to the data addresses associated with the commands).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Simionescu with those of Liu. Liu teaches specifically sorting commands in a subset according to the command address, which can allow for mor efficient command operation based on performing sequential operations grouped together in a subset (i.e., see Liu paragraph [0009], The command groups from the sorting module are stored in a command-group pool, wherein each of the command groups has at least one command. The picker unit picks one of the command groups from the command-group pool. The decoder decodes the commands within the picked command group according to the data addresses those would be accessed by the commands. The cache unit stores the data corresponding to the data addresses which are previously accessed by the previous commands. If the data being accessed by the current commands have the same addresses as the data previously accessed by the previous commands, the previously accessed data in the cache unit are transmitted to the host systems directly. If the data being accessed by the current commands have the different addresses from the data previously accessed by the commands, the command executer unit executes the current commands from the decoder and transmits the data at the addresses associated with the executed current commands to the host systems. And meanwhile, the cache unit is updated with the data at the addresses associated with the commands).
Claim 20 is the corresponding non-transitory computer medium claim to method claim 16. It contains the same limitations and is therefore rejected with the same references and rationale.
Regarding claim 17, Simionescu in view of Liu teaches The method of claim 16, wherein the commands in the sequence write data items into the non-volatile storage media of the storage device (Simionescu paragraph [0021], monitoring a stream of write commands to determine a queue depth, whether the target addresses are sequential, and when the alignment flag is set whether the data to be written is in alignment based on the characteristic of the set of flash-based storage elements. The commands are write commands to the non-volatile memory).
Regarding claim 18, Simionescu in view of Liu teaches The method of claim 16, wherein the commands in the sequence identify locations of data items to be stored or retrieved using logical addresses (Simionescu paragraph [0020], The data storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. The commands reference the logical volume/addresses for the operations).
Regarding claim 21, Simionescu teaches The method of claim 16, wherein whether or not data items identified in the subset are addressed sequentially is determined based on whether or not logical addresses of data items in the subset are sequential (Liu paragraphs [0034-0035], The command-executing module 216 sorts the addresses accessed by the commands on the storage unit 208 from FIG. 6A to FIG. 6B for executing the sorted commands sequentially. The addresses associated with the commands are arranged in sequence to simplify the motion of the read/write head of the storage unit 208. As a result, the virtual storage system 200 with the scheduling apparatus 202 schedules commands for scheduling commands to reduce input/output (I/O) time of the storage unit 208. In one embodiment, the addresses of the commands are addressed based on logical block addressing (LBA) or the physical addressing of the storage unit 208. It should be noted that LBA used in the storage unit 208 (e.g. hard disk drive) may be arbitrary bit number, e.g. 28-bit, 48-bit wide, or more bit wide to be suitable for storage unit 208 with more large capacity. The sorting of the commands (as seen previously in independent claim 16, Liu paragraph [0034]) can be done according to logical addresses being sequential).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Simionescu with those of Liu. Liu teaches specifically sorting commands in a subset according to the command address, which can allow for mor efficient command operation based on performing sequential operations grouped together in a subset (i.e., see Liu paragraph [0009], The command groups from the sorting module are stored in a command-group pool, wherein each of the command groups has at least one command. The picker unit picks one of the command groups from the command-group pool. The decoder decodes the commands within the picked command group according to the data addresses those would be accessed by the commands. The cache unit stores the data corresponding to the data addresses which are previously accessed by the previous commands. If the data being accessed by the current commands have the same addresses as the data previously accessed by the previous commands, the previously accessed data in the cache unit are transmitted to the host systems directly. If the data being accessed by the current commands have the different addresses from the data previously accessed by the commands, the command executer unit executes the current commands from the decoder and transmits the data at the addresses associated with the executed current commands to the host systems. And meanwhile, the cache unit is updated with the data at the addresses associated with the commands).
Regarding claim 22, Simionescu in view of Liu teaches wherein the subset of commands, examined to make the determination of whether or not data items identified in the subset are addressed sequentially, is a predetermined number of commands (Simionescu paragraph [0050], A data structure for analyzing a stream of I/O commands includes a count of commands analyzed, a count of non-sequential commands and a logical block address for the last write operation. A write bypass threshold size is set to K bytes, where K is an integer. A second threshold defines a minimum number of commands to initiate a cache bypass. The system has a specified threshold value of sequential commands before the system is optimized for sequential commands).
Regarding claim 23, Simionescu in view of Liu teaches The computer system of claim 2, wherein the storage device optimizes processing of commands in the subset based on the result of the determination of whether or not data items identified in the subset are addressed sequentially (Simionescu paragraph [0021], In an exemplary embodiment, a method for dynamic switching of write-back to write-through caching mode in a data storage controller managing a logical volume supported by flash-based storage devices exposed to a host as a redundant array of inexpensive disks (RAID) is disclosed. The method includes the steps of identifying a RAID type for a logical volume managed by a data storage controller, identifying a characteristic of a set of flash-based storage devices coupled to the data storage controller, initializing a device driver with an alignment flag and a threshold type, monitoring a stream of write commands to determine a queue depth, whether the target addresses are sequential, and when the alignment flag is set whether the data to be written is in alignment based on the characteristic of the set of flash-based storage elements, for a logical volume supported by RAID type 0, using the queue depth to direct the storage controller to use one of a first data path or an alternative data path different from the first data path in the data storage controller and for a logical volume supported by RAID type 5, using queue depth to direct the storage controller to use a write back mode or a write through mode. The processing of the determined commands can be performed based on a variety of factors, including sequential target addresses, as detailed above. Additionally, the optimization is not described to any specific level, and can be interpreted as the dynamic switching between write back or write through modes).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simionescu in view of Liu in further view of Hahn et al. (US Publication No. 2015/0134857 -- "Hahn").
Regarding claim 7, Simionescu in view of Liu teaches The computer system of claim 2, wherein the storage device continuously monitors commands of the predetermined number to determine whether or not data items identified in the commands of the predetermined number being monitored are addressed sequentially (Simionescu paragraph [0050], A data structure for analyzing a stream of I/O commands includes a count of commands analyzed, a count of non-sequential commands and a logical block address for the last write operation. A write bypass threshold size is set to K bytes, where K is an integer. A second threshold defines a minimum number of commands to initiate a cache bypass. The system has a specified threshold value of sequential commands before the system is optimized for sequential commands).
Simionescu in view of Liu does not teach The computer system of claim 2, wherein the storage device continuously monitors commands of the predetermined number to determine whether or not data items identified in the commands of the predetermined number being monitored are addressed sequentially.
However, Hahn teaches The computer system of claim 2, wherein the storage device continuously monitors commands of the predetermined number to determine whether or not data items identified in the commands of the predetermined number being monitored are addressed sequentially (Hahn paragraph [0054], the NVMe specification allows for I/O Submission Queues to be created dynamically, up to N number of queues (where N is the maximum supported by the device). Using a Vendor Specific protocol, in addition to the standard Queue creation commands, new commands can be defined to allow the host to dynamically assign characteristics to the Queue to identify to the SSD device the type characteristics of the command data to expect from the queue. The commands from the host are monitored continuously (i.e., dynamically) to determine characteristics (such as sequential, as taught in Simionescu)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Simionescu and Liu with those of Hahn. Hahn teaches monitoring the commands continuous/dynamically, which is an obvious improvement as it allows the system to respond immediately to the claim characteristics, which allows to system to more accurately optimize performance (Hahn paragraph [0054], These characteristics may result in equivalent Data Set Management attributes being assigned to the LBAs addressed in the queued commands. For example, a set of Write commands submitted to a specific queue may indicate to the device that these will be read in the future in the same sequence in which they were written. In another example, a set of Read commands submitted to a single queue may indicate that these reads form a dynamic library cache which is read frequently in a specific sequence and never modified).
Regarding claim 10, Simionescu in view of Liu in further view of Hahn teaches The computer system of claim 9, wherein the host communicates with the storage device in accordance with a non-volatile memory host controller interface specification (Hahn paragraph [0004], In an attempt to improve the host to storage module synergy, NVMe and Advanced Host Controller Interface (AHCI) specifications include Data Set Management (DSM) commands and parameters which allows a host to hint to the storage module that various logical block address (LBA) ranges that are going to be used in a certain way).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Simionescu and Liu with those of Hahn. Using the specification as taught in Hahn improves the synergy between the host and the storage drive (Hahn paragraph [0004], In an attempt to improve the host to storage module synergy, NVMe and Advanced Host Controller Interface (AHCI) specifications include Data Set Management (DSM) commands and parameters which allows a host to hint to the storage module that various logical block address (LBA) ranges that are going to be used in a certain way).
Regarding claim 11, Simionescu in view of Liu in further view of Hahn teaches The computer system of claim 10, wherein the storage device is a solid state drive (Simionescu paragraph [0056], data stored in the primary data store 260 appears as one or more logical data volumes 270 even though the data may be distributed across a set of solid-state or flash-based data storage devices).
Regarding claim 12, Simionescu in view of Liu in further view of Hahn teaches The computer system of claim 1, wherein the host places commands directed to different data streams in different input/output submission queues (Hahn paragraph [0033], The host 50 is responsible for determining which commands (e.g., from one or more core processors on the host 50) go into which of the host queues 300 and then which subset of commands from a given host queue should be placed in the corresponding submission queue (SQ). Different command streams will be allocated to corresponding submission queues).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Simionescu and Liu with those of Hahn. Separating the data streams into different queues allows the system to multitask and function at an overall more efficient level (Hahn paragraph [0033], while the storage module 100 processes commands from a certain portion of the submission queue (SQ), the host 50 can be populating other portions of the submission queue (SQ) with commands to be executed in the future).
Regarding claim 13, Simionescu in view of Liu in further view of Hahn teaches The computer system of claim 12, wherein the data streams corresponding to data access requests from different running instances of one or more applications (Hahn paragraph [0033], while the storage module 100 processes commands from a certain portion of the submission queue (SQ), the host 50 can be populating other portions of the submission queue (SQ) with commands to be executed in the future. While the commands in the host and submission queues (SQ) are typically from applications running on the host 50, the host 50 can also have an admin submission queue (ASQ), which is similar to a submission queue (SQ) but is used to submit administrative commands to the storage module 100. The data streams can be separated by the running applications corresponding to the host commands).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Simionescu and Liu with those of Hahn, as seen in claim 12.
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simionescu in view of Liu in further view of Hahn as applied to claim 12 above, and further in view of Xiong (US Publication No. 2015/0121503).
Simionescu in view of Liu in further view of Hahn teaches The computer system of claim 12, wherein the data streams corresponding to data access requests from different user accounts.
Simionescu in view of Liu in further view of Hahn does not teach The computer system of claim 12, wherein the data streams corresponding to data access requests from different user accounts.
However, Xiong teaches The computer system of claim 12, wherein the data streams corresponding to data access requests from different user accounts (Xiong paragraph [0007-0008], A method for maintaining a login state of a user account, including: acquiring a data access request corresponding to a user ID, the data access request includes a session ID corresponding to the user ID. Data streams are distinct based on a user account, which is monitored via a user ID).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Simionescu, Liu and Hahn with those of Xiong. Xiong teaches separating the data streams based on the user account associated with them, which allows the system to customize certain characteristics for multiple different users simultaneously (Xiong paragraph [0020], the session allocated to the data access request corresponds to the user ID, and the session corresponding to the user ID can be used repeatedly, such that the function of multiple user accounts maintaining login state simultaneously at the same client can be realized without the need of re-authenticating the user ID and re-creating a new session allocated to the data access request corresponding to the user ID when switching user accounts).
Response to Arguments
Applicant’s arguments, see pages 1-3 (numbered pages 1-3), filed April 9th, 2026, with respect to the rejection(s) of claim(s) 1, 4-6, 8-9, 15-18 and 20 under 35 U.S.C. 102(a)(1) and 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Simionescu et al. (US Publication No. 2015/0286438 -- "Simionescu") in view of Liu et al. (US Publication No. 2009/0165008 – “Liu”).
In response to the applicant’s amendments to independent claims 1, 16 and 20, the Liu reference has been added to more explicitly disclose the concept of sorting commands based on address information. Specifically, Liu teaches sorting a subset (I.e., command group) based on logical address information, as cited in the rejection above. In light of the newly added reference, the 35 USC 103 Rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Saxena et al. (US Publication No. 2021/0303206) discloses a similar concept to the claimed invention, describing the process of sorting commands in a subset and optimizing command processing based on sequential logical addresses (i.e., see Saxena paragraph [0080], Accordingly, the present disclosure allows for a storage device which receives sequential read commands with large MDTS (e.g. 32 MB of video data) from a host device to process multiple read requests in an IPC queue without being stalled and impacting sequential and random read performance. In this way, the storage device may also complete error handling during processing of the large sequential commands. Moreover, commands may be divided into portions which are dynamically determined based on queue utilization in different read workloads and based on different sizes of read commands, further optimizing handling of large sequential read commands. Additionally, short random commands may be processed along with large sequential reads to accommodate mixed read (e.g. sequential and random) workloads).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAH C KRIEGER whose telephone number is (571)272-3627. The examiner can normally be reached on Monday - Friday 8 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached on (571)-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.K./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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