DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over as being unpatentable over Gorbachov et al. (US 2015/0015339 A1) in view of Xie et al. (US 2013/0257543 A1).
Regarding claim 1, Gorbachov discloses a circuit for protecting a power amplifier (RF power-amplifier circuits and input-power limiter circuits … mitigating voltage and current overstress of transistors utilized in RF power amplifiers. Therefore, it is a circuit for protecting a power amplifier, §0013-§0016).
a multistage power amplifier circuit (first PA stage 20, second PA stage 22, inter-stage matching network 21, §0039-§0040, Fig. 1) with a matching/adjustment network (Provides an inter-stage adjustment network located in series between adjacent PA stages. Transistor Q3, controlled by control circuit 42, changes the inter-stage impedance and thereby adjusts gain or protects the PA from overstress—corresponds to inter-stage adjustment circuit, §0053-§0056, Fig. 5).
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Fig. 1 of Gorbachov reproduced by the examiner for ease of reference.
Gorbachov also teaches (§0043–§0049, §0054–0056 and FIG. 5 (control circuit 42, power detector 36, comparator logic: control circuit drives switch Q3 when input power detector voltage exceeds reference value: Q3 changes its impedance to reduce gain and protect the PA. This corresponds to overload detection and protection activation. Gorbachov thus discloses turning an inter-stage circuit from its nominal (ON) state to an altered (OFF or reduced-gain) state when overload protection is triggered.
Gorbachov, however, does not explicitly provide a preset delay for returning the inter stage switch to its normal ON state after the overload condition cases.
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Fig. 2 of Xie reproduced by the examiner for ease of reference.
Xie teaches a protection control circuit (202) comprising a delay network (§0031-§0034), Fig. 2 element 202, RC delay that controls a power amplifier switch (203) to remain OFF for a specified interval and reenable after a preset time is elapsed (§0072-§0088, Fig. 5).
It would have been obvious to one of ordinary skill in the art to modify Gorbachov’s control circuit 42 to include Xie’s delay feature so that its interstage switch (Q3) remains OFF for a preset period following termination of an overload condition. This substitution would be a predictable use of an old element (delay control) for its known function (improving stability and ensuring safe reenable timing) in the context of PA protection circuits. Therefore, the combination of Gorbachov and Xie renders the subject matter of claim 1 obvious.
Regarding Claim 2, Gorbachov explicitly discloses an inter-stage matching and control network disposed between successive amplifier stages, including later stages of a multi-stage power amplifier (See Gorbachov, Fig. 1, inter-stage network 21 positioned between amplifier stages 12 and 13, and Fig. 5, adjustable inter-stage network 52 between later gain stages).
Regarding Claim 3, Gorbachov teaches that each amplifier stage may be provided with its own inter-stage matching and control circuitry, enabling stage-by-stage gain and protection control (See Gorbachov, Fig. 2, showing multiple amplifier stages 12a–12c with corresponding inter-stage networks 21a–21c, and § §0046–§0048). Applying the same adjustment circuit between every adjacent stage is a predictable extension of the disclosed architecture.
Regarding Claim 4, Gorbachov discloses a power detector circuit that senses excessive power conditions and outputs a control signal to a controller (See Gorbachov, Fig. 1, power detector 36 feeding control circuit 42, and Fig. 2, overload detection block 36 coupled to controller 42). Xie further reinforces this structure by teaching overload detection circuitry outputting signals to a controller for protective action (see Xie, Fig. 3, detector 310 coupled to controller 320).
Regarding Claim 5, Gorbachov explicitly teaches reducing bias current and operating point of amplifier stages in response to overload detection (See Gorbachov, Fig. 2, control circuit 42 adjusting bias of amplifier 12, and §0049 describing quiescent current reduction. Xie further teaches turning off or disabling an amplifier during fault conditions (see Xie, Fig. 4, switch 410 disabling PA 400).
Regarding Claim 6, Xie expressly discloses comparing sensed voltage/current values against a threshold to determine overload (See Xie, Fig. 3), comparator 315 comparing sensed current Isense to reference Vref, §0036–§0038. Gorbachov similarly teaches threshold-based detection of excessive power conditions using detector 36.
Regarding Claims 7 and 8, Xie expressly teaches separate over-voltage and over-current detection circuits for amplifier protection (See Xie, Fig. 3, voltage detector 312 and current detector 311, §0037. Gorbachov’s power detector 36 inherently monitors voltage and current conditions associated with excessive RF power.
Regarding Claim 9, Gorbachov discloses hysteresis and recovery behavior, wherein the protection circuit restores normal amplifier operation once overload conditions cease (See Gorbachov, Fig. 2, hysteresis circuit 44, §0049 describing return to normal bias). Xie similarly teaches recovery after fault clearance (see Xie, §0042).
Regarding Claim 10, Gorbachov teaches the use of timing and hysteresis delays to allow amplifier stabilization before restoring full operation (See Gorbachov, Fig. 2, delay element within hysteresis circuit 44, §0049). Such timing delays are well-known and routine in amplifier protection circuits.
Regarding Claim 11, Gorbachov explicitly teaches that inter-stage networks remain fully conductive during normal operation and are modified only upon overload detection (See Gorbachov, Fig. 5, switch 53 in default closed state during non-overload conditions).
Regarding Claims 12–14, Gorbachov expressly discloses both: Switch-based inter-stage control (See Gorbachov, Fig. 5, switch 53 controlled by control circuit 42) and Adjustable attenuation networks (See Gorbachov, Fig. 7, variable attenuator 72 between amplifier stages). Claims 13 and 14 merely specify control of insertion loss and switching behavior already shown in these figures.
Claim 15 recites a method corresponding to circuit of claim 1, wherein,
Gorbachov and Xie both disclose methods of detecting overload, modifying inter-stage signal paths, and restoring normal operation (See Gorbachov, §0046–§0049 and Xie, §0035–§0043.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.