DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “ A SYSTEM ON CHIP TEMPERATURE MANANGEMENT IN A VIRTUAL ENVIRONMENT”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “third exception ” in claim 9 and 19 is used by the claim to indicate “EL0,” while the accepted meaning of third exception is “EL3” The term is indefinite because the specification does not clearly redefine the term.
Claims 9 and 16 recite “a third exception level comprises an EL0” (emphasis added). The specification does not provide for this correlation between third exception and EL0 as claim. In addition, this phrase goes against the conventional labeling of privilege and exception level and accepted meaning of ARMSv8 definition.
In addition, the specification discloses bootloader at EL3 (Exception Level 3) (par. 45 and 48) and application APP1 at EL0 (par, 75 and 77) which is in line with the definition of the exception level defined by ARMSv8 and as conventionally used.
Therefore, the term “a third exception level comprises an EL0” is indefinite because the specification does not clearly redefine the term.
Clarification/correction required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable Khodorkovsky, US 20130155073 or in the alternative in view of Rosemarine, 20240256646.
Regarding claim 1. A system on chip comprising [Fig. 1 par. 26, integrated circuit 5]:
a first core cluster configured to execute a first virtual machine loaded into a memory, the first core cluster including a plurality of first cores [Fig. 1-2, VM 1, par. 1, VM1-VMn of graphic processor cores, par. 2-3, logically partition the system hardware of the physical machine, see also par. 31, shared physical hardware resources] ; and
a second core cluster configured to execute a second virtual machine loaded into the memory, the second core cluster including a plurality of second cores, [Fig. 1-2, VM2, par. 1, 2 and 31 as discussed in VM1]
wherein a first core of the plurality of first cores is configured to execute software at the VM level to generate a first power operating temperature value request, [par. 7, each VM operate via Guest OS and includes its own graphic driver (i.e. EL1 exception level), that requests power management operating range settings based on the condition of the VM]
execute a hypervisor loaded into the memory at the hypervisor level to receive a first temperature value from temperature management circuitry, in response to the first temperature value request [par 1., Hypervisor 46 (i.e. EL level 2) provides power management unit 24 information associated with each VM 40 including power control settings requests (VM1 REQ, VM2 REQ, . . . VMn REQ. See also par. 31-33, ]; and
and execute the first virtual machine at the VM level to check the first received operating value [par. 7-9 and 28, VM runs/operates based on graphics processing core power management operating ranges provide by the PMU]
wherein a second core of the plurality of second cores is configured to execute the second virtual machine the VM level to generate a second temperature value request, [par. 7, same operation for all VM as discussed in VM1]
execute the hypervisor at the hypervisor level to receive a second temperature value from the temperature management circuitry, in response to the second temperature value request, [par. 38, same operation all VM as discussed in VM1]
and execute the second virtual machine at the VM level to check the received second temperature value [par. 7-9 and 28 VM runs/operates based on graphics processing core power management operating ranges provide by the PMU]
Though Khodorkovsky teaches that the VMs request operating parameters (voltage and frequency) to during operation [ par. 20] but does not explicitly recite that the operating parameter being temperature. However, Khodorkovsky teaches a digital power and thermal monitor is tangential to virtualization and the thermal monitor tracks temperature of the VMs [par. 39] and based the PMU monitor the power usage across multiple VMs to control the clock frequency to prevent thermal instability for the system [ par. 40]. Khodorkovsky further teaches the goal is to select operating parameters (voltage and frequency settings) to minimize energy usage and avoid thermal fault while maintain good performance level [par. 34]. Therefore, it would have been obvious to one having ordinary skill in the art to before the effective filing date to implement thermal monitoring as suggest by Khodorkovsky since power and thermal management are both use to interchangeably to minimize energy usage and avoid thermal fault while maintain good performance level.
As for the terms “exception levels”, as discussed in the rejection, the software are operated at either VM or hypervisor level based on the operation of the software components executed by the processor to run the virtual machine but does not specifically discuss EL levels. Similar to Khodorkovsky, Rosemarine teaches that that processor compliant with ARM®v8 architecture having privilege levels may therefore sometimes be referred to as “exception levels which are defined as EL0, EL1, EL2, and EL3 in order of increasing code-execution associate with the particular software model [Rosemarie, see at least Fig. 2-4, par. 19-23]. Rosemarine also discusses managing access using the privilege and exceptional scheme of program application, drivers and OS operating in a GPU virtualized environment and its benefits [par. 27-30]. It would have been obvious to one having ordinary skills in the art before the effective filing date to implement the exception levels avoid access conflicts and corruption of memory either by accident and/or by malicious intent from a rogue application [Rosemarine, par. 26-28].
Claim 2. The combination teaches the system on chip of claim 1, wherein the first virtual machine comprises a first operating system (OS), and the second virtual machine comprises a second OS different from the first OS [Khodorkovsky, par. 2 and 31 OS/Guest OS, Laplace, par. 13-14 and 19-20]
Claim 3. The combination teaches system on chip of claim 1, wherein the first core is further configured to execute the first virtual machine at the first exception level to control a clock provided to the first core cluster, in response to the received first temperature value being equal to or greater than a threshold [Khodorkovsky , par. 27-28 and 32-33 and 35 PMU sends dynamic power adjustment decisions for clock frequency setting to graphic processing core engines 14-10 which operate the VMs, a clock generator 22 which provides variable operating frequencies; Fig. 5, steps 112-108].
Claim 4. The combination teaches system on chip of claim 3, wherein the first core is further configured to execute the first virtual machine at the first exception level to change a frequency of the clock provided to the second core from a first frequency to a second frequency, in response to the received first temperature value being equal to or greater than the threshold [par. 27-28 and 32-33, PMU sends dynamic power adjustment decisions for clock frequency setting to graphic processing core engines 14-10 which operate the VMs, a clock generator 22 which provides variable operating frequencies, Fig. 5, steps 112-108]
Claim 5. The combination teaches the system on chip of claim 3, and receiving a operating setting/temperature but does not specifically teach disclose the second VM transmit a control signal to an RF circuit (RF IC). However, Khodorkovsky teaches different VMs often run different application mixes and independent of graphics rendering functions and the device can be of a computer , game unit or cell phone [par. 7 and 26, and Fig. 1, a communication link]. Therefore, it would have been obvious that the second VM can perform function such as voice transmission or display via radio frequency (i.e. transmit to RF circuit) since radio frequency is used in communication devices such as transmitter, receivers, computer, TV and mobile phone to carry out the indented function of the device.
Claim 6. The system on chip of claim 5, wherein the second core is further configured to execute the second virtual machine at the first exception level to control the RF circuit such that a communication mode of the RF circuit changes, in response to the received second temperature value being equal to or greater than the threshold [Khodorkovsky, par. 29, 34, 37 and 59, decrease frequency or maintain based on comparison with threshold]
Claim 7. The combination teaches the system on chip of claim 1, wherein the first exception level comprises an EL1 and the second exception level comprises an EL2 [Rosemarine, par. 13-14 and Fig. 2-4]
Claim 8. The combination teaches the system on chip of claim 1, but does not specify that the second core is further execute an application at a third exception level different (EL3) and at the first exception level to generate the second temperature value request in response to the third temperature value request. Rosemarine teaches software and/or firmware may have different access to system resources (i.e. EL3), and user applications, which may have a more limited ability to access system resources [Fig. 2 and par. 20]. Thus, it would have been obvious to one having ordinary skills in the art before the effective filing date to realize that depending on the type of software being run on the VM to provide the appropriate exception level. Motivation is as discussed in claim 1.
Claim 9. The combination teaches the system on chip of claim 8, wherein the third exception level comprises an EL0, and the second exception level comprises an EL2. ), Khodorkovsky [par. 2] VMs run software such as operating system or an application. Rosemarine teaches Application is EL0 and OS is EL1 [Fig. 2] and firmware [EL3] can be run on VM [par. 20-21].
Claim 10. The combination teaches the system on chip of claim 1, wherein the first core is configured to execute the first virtual machine and operate as an application processor (AP] and the second core is configured to execute the second virtual machine and operate as a communication processor (CP) [par. 7 and 26, and teaches different VMs often run different application mixes and the device can be of a computer , game unit or cell phone [par. 7 and 26, and Fig. 1, a communication link as discussed in claim 5].
Claim 11. The combination teaches the system on chip of claim 1, wherein the first core is configured to execute the first virtual machine to operate as an application processor (AP), and the second core is configured to execute the second virtual machine and operates with the AP [Khodorkovsky par. 2, VM running OS or an application]
Regarding claim 12. An electronic device comprising: a memory into which a first virtual machine, a second virtual machine, and a hypervisor are loaded [Khodorkovsky, par. 3, 27] . The rest of the claim repeats the limitation of claim 1 and rejected accordingly.
Claim 13. The combination teaches the electronic device of claim 12, and repeat the limitation of claim 5 and therefore rejected accordingly.
Claim 14. The combination teaches the electronic device of claim 12, the rest of the claims recite the limitations of claims 3-4 and reject according.
Claim 15. The combination teaches the electronic device of claim 12, the rest repeats the limitation of claim 2 and rejected on the same ground.
Claim 16. The combination teaches the electronic device of claim 12, and repeats the limitation of claim 8 and rejected on the same ground
Regarding claim 17. The combination teaches an electronic device as recited in claim 1 (without the recitation of the hypervisor) and therefore the rejection is covered by the rejection of claim 1.
Claim 18. The combination teaches the electronic device of claim 17, the rest of the claim repeats the limitation of claim 3 and is rejected on the same ground.
Claim 19. The combination teaches the electronic device of claim 18, the rest of the claim repeats the limitation of claims 4-5 and is rejected on the same ground.
Claim 20. The electronic device of claim 17 , the rest of the claim repeats the limitation of claims 3 -4 and is rejected on same ground.
Conclusion
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/KIM HUYNH/Primary Patent Examiner, Art Unit 2176