Prosecution Insights
Last updated: October 04, 2026
Application No. 18/469,479

CIRCUIT MODULE AND SUBSTRATE MODULE

Non-Final OA §102§103
Filed
Sep 18, 2023
Priority
Sep 22, 2022 — JP 2022-151463
Examiner
MILAKOVICH, NATHAN J
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
560 granted / 717 resolved
+10.1% vs TC avg
Strong +19% interview lift
Without
With
+18.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
15 currently pending
Career history
729
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
44.8%
+4.8% vs TC avg
§102
25.4%
-14.6% vs TC avg
§112
21.7%
-18.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of species A and species 1 in the reply filed on June 8, 2026, is acknowledged. Claims 9-10 and 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 8, 2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings were received on September 18, 2023. These drawings are acceptable. Claim Objections Claims 1-8 and 11-15 are objected to because of the following informalities: Claim 1 recites, “an insulating member covering the upper main surface of the circuit substrate (11b, 12a, 14)” in lines 6-7 and again in lines 7-8. Claims 2-8 and 11-15 are objected to by reason of their dependency. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2022/0167500 to Wei. Wei (FIG. 1-9, 11-18) discloses a substrate module (10) on which an electronic component (50) is mounted, the substrate module (10) comprising: a circuit substrate (11b, 12a, 14; note 11b is the darkened dielectric layer of 11 shown in FIG. 2; see also, e.g., FIG. 13-17 expressly labeling 11b) having an upper main surface and a lower main surface, an insulating member (11a; note 11a is the lighter dielectric layer of 11 shown in FIG. 2; see also, e.g., FIG. 11-17 expressly labeling 11a) covering the upper main surface of the circuit substrate (11b, 12a, 14), and a first metal pin (15) and a second metal pin (15) that pass through the insulating member (11a) parallel to a vertical axis and are electrically connected to the circuit substrate (11b, 12a, 14), the second metal pin (15) being located right of the first metal pin (15), the first metal pin (15) has a first exposed portion (at 43, see FIG. 4A), the second metal pin (15) has a second exposed portion (at 43), the first exposed portion (at 43) is exposed from the insulating member (11a) to face a right direction (see FIG. 4A), and the second exposed portion (at 43) is exposed from the insulating member (11a) to face a left direction. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-8 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of US Publication 2020/0170121 to Lecordier et al. (hereinafter Lecordier). Claim 1 Wei (FIG. 1-9, 11-18) discloses a circuit module comprising: a substrate module (10); an electronic component (50); and a first conductive joining member (55), wherein the substrate module (10) includes a circuit substrate (11b, 12a, 14; note 11b is the darkened dielectric layer of 11 shown in FIG. 2; see also, e.g., FIG. 13-17 expressly labeling 11b) having an upper main surface and a lower main surface, an insulating member (11a; note 11a is the lighter dielectric layer of 11 shown in FIG. 2; see also, e.g., FIG. 11-17 expressly labeling 11a) covering the upper main surface of the circuit substrate (11b, 12a, 14), an insulating member (see objection to claim 1, above; 11a; note 11a is the lighter dielectric layer of 11 shown in FIG. 2; see also, e.g., FIG. 11-17 expressly labeling 11a) covering the upper main surface of the circuit substrate (11b, 12a, 14), and a first metal pin (15) that passes through the insulating member (11a) parallel to a vertical axis and is electrically connected to the circuit substrate (11b, 12a, 14), the first metal pin (15) has a first exposed portion (at 43, see FIG. 4A), the first exposed portion (at 43) is exposed from the insulating member (11a) to face a right direction (see FIG. 4A), the electronic component (50) includes an electronic component body (50) having a lower surface, a left surface, and a right surface, and a first outer electrode (51) having a left portion (51) on the left surface, and the first conductive joining member (55) joins the first exposed portion (at 43) and the left portion (51) to each other, as recited in claim 1. Wei does not expressly disclose the first outer electrode having a left projecting portion projecting in a left direction from the left surface, as recited in claim 1 (see, e.g., FIG. 5). Lecordier (FIG. 2) teaches a first outer electrode (8) having a left projecting portion projecting in a left direction from a left surface. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Lecordier with Wei to incorporate a package with bottom and side electrodes as taught by Lecordier in the structure taught by Wei, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for additional packaging options, a larger area for bonding, increasing the strength of the bond, lowering contact resistance, allowing for increased current flow, and improving reliability of the circuit module. Claim 2 Wei with Lecordier teaches the circuit module according to Claim 1, further comprising: a second conductive joining member (Wei FIG. 6: 55), wherein the substrate module (10) further includes a second metal pin (15) that passes through the insulating member (11a) parallel to the vertical axis and is electrically connected to the circuit substrate (11b, 12a, 14), the second metal pin (15) being located right of the first metal pin (15; see FIG. 4A), the second metal pin (15) has a second exposed portion (at 43), the second exposed portion (at 43) being exposed from the insulating member (11a) to face the left direction (see FIG. 4A), the electronic component (Wei 50 in view of Lecordier, as above regarding claim 1) further includes a second outer electrode (Wei 51 in view of Lecordier 8, as above regarding claim 1) having a right projecting portion projecting in the right direction from the right surface (as above regarding claim 1, see Lecordier FIG. 2), and the second conductive joining member (Wei 55) joins the second exposed portion (at 43) and the right projecting portion (as above regarding claim 1: Wei 51 in view of Lecordier 8) to each other. Claim 3 Wei with Lecordier teaches the circuit module according to Claim 2, wherein the insulating member (Wei 11a) has an upper main surface, the upper main surface of the insulating member (11a) includes a recessed portion (40) having a left side surface facing the right direction, a right side surface facing the left direction, and a bottom surface (FIG. 4A), the first exposed portion (at 43) is exposed from the insulating member (11a) on the left side surface, the second exposed portion (at 43) is exposed from the insulating member (11a) on the right side surface, and the electronic component (50) is in the recessed portion as viewed in a downward direction (FIG. 5). Claim 4 Wei with Lecordier teaches the circuit module according to Claim 3, wherein the recessed portion (Wei 40) further has a front side surface facing a rear direction and a rear side surface facing a front direction (FIG. 4B), and the electronic component (50) is surrounded by the left side surface, the right side surface, the front side surface, and the rear side surface as viewed in the downward direction (FIG. 6B). Claim 5 Wei with Lecordier teaches the circuit module according to Claim 4, wherein the substrate module (Wei 10) has a rectangular shape including a first long side, a second long side, a first short side, and a second short side as viewed in the downward direction (FIG. 4B), as recited in claim 5. Wei does not expressly disclose a straight line including the front side surface (of 40) intersects a left portion of the first long side (of 10) at an angle smaller than 90 degrees as viewed in the downward direction and a straight line including the rear side surface (of 40) intersects a right portion of the second long side (of 10) at an angle smaller than 90 degrees as viewed in the downward direction, as recited in claim 5 (see FIG. 4B: apparently 90 degrees; see also and compare application FIG. 9). The mere changing of a shape (angling the cavity of Wei and electrodes relative to the outer edges of the substrate module) is a common practice which requires only ordinary skill in the art and therefore is a routine expedient, and would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, as a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed arrangement is significant, and Applicant has presented no argument which shows that the particular configuration is significant or anything more than one of numerous configurations a person of ordinary skill in the art would find obvious for the purpose of orienting components in a printed circuit board to maximize spacing and package density, especially given that not all packages are square or rectangular and a corresponding cavity thereof would not be square or rectangular. See MPEP 2144 IV.B. citing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Claim 6 Wei with Lecordier teaches the circuit module according to Claim 3, wherein the first metal pin (Wei 15) further has a third exposed portion (at 30; FIG. 4A), the second metal pin (15) further has a fourth exposed portion (at 30; FIG. 4A), the third exposed portion (at 30) is exposed from the upper main surface of the insulating member (11a), the fourth exposed portion (at 30) is exposed from the upper main surface of the insulating member (11a), the first conductive joining member (Wei 55) joins the third exposed portion (at 30) and the left projecting portion (as above regarding claim 1: Wei 51 in view of Lecordier 8) to each other (see Lecordier FIG. 2a, 2c), and the second conductive joining member (Wei 55) joins the fourth exposed portion (at 30) and the right projecting portion (as above regarding claim 1: Wei 51 in view of Lecordier 8) to each other (see Lecordier FIG. 2a, 2c). Claim 7 Wei with Lecordier teaches the circuit module according to Claim 2, wherein the insulating member (Wei 11a) has an upper main surface, the upper main surface of the insulating member (11a) includes a recessed portion (40) having a left side surface facing the right direction, a right side surface facing the left direction, and a bottom surface (FIG. 4A), the first exposed portion (at 43) is located left of the left side surface (FIG. 4A), the second exposed portion (at 43) is located right of the right side surface (FIG. 4A), and the electronic component (50) is located in the recessed portion (40) as viewed in a downward direction (FIG. 5-6B). Claim 8 Wei with Lecordier teaches the circuit module according to Claim 1, wherein the first outer electrode (Wei 51) includes a first bottom surface portion located on the lower surface and a first side surface portion located on the left surface (as above regarding claim 1: Wei 51 in view of Lecordier FIG. 2: 8), and the first side surface portion is the left projecting portion (Lecordier FIG. 2). Claim 11 Wei with Lecordier teaches the circuit module according to Claim 4, wherein the first metal pin (Wei 15) further has a third exposed portion (at 30; FIG. 4A), the second metal pin (15) further has a fourth exposed portion (at 30; FIG. 4A), the third exposed portion (at 30) is exposed from the upper main surface of the insulating member (11a), the fourth exposed portion (at 30) is exposed from the upper main surface of the insulating member (11a), the first conductive joining member (Wei 55) joins the third exposed portion (at 30) and the left projecting portion (as above regarding claim 1: Wei 51 in view of Lecordier 8) to each other (see Lecordier FIG. 2a, 2c), and the second conductive joining member (Wei 55) joins the fourth exposed portion (at 30) and the right projecting portion (as above regarding claim 1: Wei 51 in view of Lecordier 8) to each other (see Lecordier FIG. 2a, 2c). Claim 12 Wei with Lecordier teaches the circuit module according to Claim 5, wherein the first metal pin (Wei 15) further has a third exposed portion (at 30; FIG. 4A), the second metal pin (15) further has a fourth exposed portion (at 30; FIG. 4A), the third exposed portion (at 30) is exposed from the upper main surface of the insulating member (11a), the fourth exposed portion (at 30) is exposed from the upper main surface of the insulating member (11a), the first conductive joining member (Wei 55) joins the third exposed portion (at 30) and the left projecting portion (as above regarding claim 1: Wei 51 in view of Lecordier 8) to each other (see Lecordier FIG. 2a, 2c), and the second conductive joining member (Wei 55) joins the fourth exposed portion (at 30) and the right projecting portion (as above regarding claim 1: Wei 51 in view of Lecordier 8) to each other (see Lecordier FIG. 2a, 2c). Claim 13 Wei with Lecordier teaches the circuit module according to Claim 2, wherein the first outer electrode (Wei 51) includes a first bottom surface portion located on the lower surface and a first side surface portion located on the left surface (as above regarding claim 1: Wei 51 in view of Lecordier FIG. 2: 8), and the first side surface portion is the left projecting portion (Lecordier FIG. 2). Claim 14 Wei with Lecordier teaches the circuit module according to Claim 3, wherein the first outer electrode (Wei 51) includes a first bottom surface portion located on the lower surface and a first side surface portion located on the left surface (as above regarding claim 1: Wei 51 in view of Lecordier FIG. 2: 8), and the first side surface portion is the left projecting portion (Lecordier FIG. 2). Claim 15 Wei with Lecordier teaches the circuit module according to Claim 4, wherein the first outer electrode (Wei 51) includes a first bottom surface portion located on the lower surface and a first side surface portion located on the left surface (as above regarding claim 1: Wei 51 in view of Lecordier FIG. 2: 8), and the first side surface portion is the left projecting portion (Lecordier FIG. 2). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Publication 2022/0399255 (note assignee and publication date); and CN Publication 117199034 (note publication date). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571)270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHAN MILAKOVICH/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Sep 18, 2023
Application Filed
Aug 31, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
97%
With Interview (+18.9%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

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