DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10, 12-15, 17-20, 22, and 24-28 are rejected under 35 U.S.C. 103 as being unpatentable over Vellei et al. (US 20190123185 A1), in view of Chen et al. (US 20150014741 A1).
Regarding claim 1, Vellei et al. teaches:
A semiconductor device [1, paragraph [0039-0041], Fig. 1-9] comprising:
a semiconductor substrate [10, paragraph [0041-0042], Fig. 1-9] which has an upper surface and a lower surface and includes a drift region [100, paragraph [0042], Fig. 1-9] of a first conductivity type [N-type];
a base region [102, paragraph [0064], Fig. 1-9] of a second conductivity type [P-type] provided between the drift region [100, Fig. 1-9] and the upper surface of the semiconductor substrate [10, Fig. 1-9];
a plurality of trench portions [14-17, paragraph [0096-0098], Fig. 1-9] provided from the upper surface of the semiconductor substrate [10, Fig. 1-9] to below the base region [102, Fig. 1-9];
a lower end region [105, paragraph [0087], [0098], [0110], [0130], Fig. 1-9] of the second conductivity type [P-type] provided in contact with lower ends of two or more trench portions [14-17, Fig. 1-9] among the plurality of trench portions [14-17, Fig. 1-9];
a well region [109, paragraph [0147-0151], Fig. 6A, 7] of the second conductivity type [P-type] which is arranged at a position different from the lower end region [105, Fig. 6A, 7] in a top view, is provided from the upper surface of the semiconductor substrate [10, Fig. 1-9] to below the base region [102, Fig. 1-9], and has a higher doping concentration than the base region [102, paragraph [0064], [0151], Fig. 1-9].
Vellei et al. does not teach:
a high resistance region of the second conductivity type which is arranged between the lower end region and the well region in the top view and has a lower doping concentration than the lower end region.
Chen et al. teaches:
a high resistance region [38-2, paragraph [0089], [0091], [0095], [0097], Fig. 1] of the second conductivity type [P-type] which is arranged between the lower end region [38-1, paragraph [0089-0091], Fig. 1] and the well region [51, paragraph [0087], Fig. 1] in the top view and has a lower doping concentration than the lower end region [38-1, paragraph [0089-0091], [0095], Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. to include a high resistance region of the second conductivity type which is arranged between the lower end region and the well region in the top view and has a lower doping concentration than the lower end region, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 2, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
the high resistance region connects the lower end region and the well region.
Chen et al. teaches:
the high resistance region [38-2, paragraph [0087-0089], Fig. 1] connects the lower end region [38-1, Fig. 1] and the well region [51, Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include the high resistance region connects the lower end region and the well region, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 3, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
a length of the high resistance region in the top view is larger than a width of the high resistance region in a depth direction of the semiconductor substrate.
Chen et al. teaches:
a length [B(1)-B(4), paragraph [0093-0094], Fig. 1] of the high resistance region [38-2, Fig. 1-2] in the top view is larger than a width [D(1)-D(4), paragraph [0092], Fig. 2] of the high resistance region [38-2, Fig. 1-2] in a depth direction of the semiconductor substrate [1 (16), Fig. 1-2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include a length of the high resistance region in the top view is larger than a width of the high resistance region in a depth direction of the semiconductor substrate, for the purpose of intensive application of a high electric field to local portions can be suppressed.
Regarding claim 4, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
the high resistance region is in contact with lower ends of two or more of the trench portions.
Chen et al. teaches:
the high resistance region [38-2, Fig. 1] is in contact with lower ends of two or more of the trench portions [18, paragraph [0071], [0088], Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include the high resistance region is in contact with lower ends of two or more of the trench portions, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 5, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
an active portion [1-2, paragraph [0042], [0147], Fig. 1-9] enclosed by the well region [109, Fig. 1-9] in the top view [Fig. 1, 7],
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
the high resistance region is arranged at a position in contact with the well region in the active portion.
Chen et al. teaches:
the high resistance region [38-2, Fig. 1, 14] is arranged at a position in contact with the well region [51, Fig. 1, 14] in the active portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include the high resistance region is arranged at a position in contact with the well region in the active portion, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 6, Vellei et al. and Chen et al. teach the semiconductor device according to claim 5.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
the high resistance region encloses the active portion in the top view.
Chen et al. teaches:
the high resistance region [38-2, Fig. 1, 14] encloses the active portion [11, paragraph [0007], [0068], Fig. 1, 14] in the top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include the high resistance region encloses the active portion in the top view, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 7, Vellei et al. and Chen et al. teach the semiconductor device according to claim 5.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
wherein the high resistance region includes:
a first high resistance portion arranged at a corner of the active portion in the top view; and
a second high resistance portion having a lower doping concentration than the first high resistance portion.
Chen et al. teaches:
wherein the high resistance region [38-2, Fig. 1] includes:
a first high resistance portion [38-2, paragraph [0089-0090], [0095], Fig. 1, 14] arranged at a corner of the active portion [11, Fig. 1, 14] in the top view; and
a second high resistance portion [38-3, paragraph [0089], [0095], Fig. 1] having a lower doping concentration than the first high resistance portion [38-2, Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include wherein the high resistance region includes: a first high resistance portion arranged at a corner of the active portion in the top view; and a second high resistance portion having a lower doping concentration than the first high resistance portion, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 10, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
the high resistance region has a peak of a doping concentration in a direction connecting the lower end region and the well region.
Chen et al. teaches:
the high resistance region [38-2, paragraph [0095], Fig. 1] has a peak of a doping concentration in a direction connecting the lower end region [38-1, Fig. 1] and the well region [51, Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include the high resistance region has a peak of a doping concentration in a direction connecting the lower end region and the well region, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 12, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
an emitter region [101, paragraph [0005], [0061-0062], Fig. 1-9] of the first conductivity type [N-type] which is provided between the base region [102, Fig. 1-9] and the upper surface of the semiconductor substrate [10, Fig. 1-9] and has a higher doping concentration than the drift region [100, Fig. 1-9].
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
part of the emitter region and part of the high resistance region overlap each other in the top view.
Chen et al. teaches:
part of the emitter region [23, paragraph [0090], Fig. 1] and part of the high resistance region [38-2, Fig. 1] overlap each other in the top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include part of the emitter region and part of the high resistance region overlap each other in the top view, for the purpose of increasing density, and intensive application of a high electric field to local portions can be suppressed
Regarding claim 13, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
an emitter region [101, paragraph [0005], [0061-0062], Fig. 1-9] of the first conductivity type [N-type] which is provided between the base region [102, Fig. 1-9] and the upper surface of the semiconductor substrate [10, Fig. 1-9] and has a higher doping concentration than the drift region [100, Fig. 1-9],
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
the emitter region and the high resistance region are arranged away from each other in the top view.
Chen et al. teaches:
the emitter region [23, paragraph [0144], Fig. 20-24] and the high resistance region [39-2, paragraph [0141-0142], [0148-0152], Fig. 20-24] are arranged away from each other in the top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include the emitter region and the high resistance region are arranged away from each other in the top view, for the purpose of suppressing intensive application of high electric fields to local portions. In other words, high electric fields are distributed, and this increases the maximum voltage resistance. In addition, a smooth change in the electric field in the plurality of P layers 39 can reduce the edge terminal width Le when the withstand voltage is constant. Accordingly, the chip area can be reduced.
Regarding claim 14, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
the plurality of trench portions [14-17, Fig. 1-9] include one or more gate trench portions [141/142, paragraph [0060], [0066-0067], [0072], [0075-0076], [0078], [0095], Fig. 2-9; 151/152, paragraph [0066-0067], [0072], [0095] Fig. 2-9; 161/162, paragraph [0068], [0086], [0095], Fig. 2-9] 171/172, paragraph [0089-0090], [0095], Fig. 2-9].
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
the high resistance region is in contact with a lower end of at least one gate trench portion of the gate trench portions.
Chen et al. teaches:
the high resistance region [38-2, paragraph [0088-0089], Fig. 1] is in contact with a lower end of at least one gate trench portion [18, paragraph [0071], Fig. 1] of the gate trench portions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include the high resistance region is in contact with a lower end of at least one gate trench portion of the gate trench portions, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 15, Vellei et al. and Chen et al. teach the semiconductor device according to claim 14.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
wherein the high resistance region includes:
a lower end portion in contact with the lower end of the gate trench portion; and
a low concentration portion having a lower doping concentration than the lower end portion.
Chen et al. teaches:
wherein the high resistance region [38-2, Fig. 1] includes:
a lower end portion [corresponding to location where 38 is in contact with 18] in contact with the lower end of the gate trench portion [18, Fig. 1]; and
a low concentration portion [38-4, paragraph [0095], Fig. 1] having a lower doping concentration [P(4)] than the lower end portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include wherein the high resistance region includes: a lower end portion in contact with the lower end of the gate trench portion; and a low concentration portion having a lower doping concentration than the lower end portion, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 17, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
the trench portion [14-17, Fig. 1-9] has a longitudinal length in a first direction and has a lateral length in a second direction in the top view.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
a ratio between a first length of the high resistance region connecting the lower end region and the well region in the first direction and a second length of the high resistance region connecting the lower end region and the well region in the second direction is 0.9 or more and 1.1 or less.
Chen et al. teaches:
a ratio between a first length [B(2), paragraph [0093], Fig. 1, 14] of the high resistance region [38-2, Fig. 1] connecting the lower end region [38-1, Fig. 1] and the well region [51, Fig. 1] in the first direction and a second length [B(2), paragraph [0093], Fig. 1, 14] of the high resistance region [38-2, Fig. 1] connecting the lower end region [38-1, Fig. 1] and the well region [51, Fig. 1] in the second direction is 0.9 or more and 1.1 or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include a ratio between a first length of the high resistance region connecting the lower end region and the well region in the first direction and a second length of the high resistance region connecting the lower end region and the well region in the second direction is 0.9 or more and 1.1 or less, for the purpose of connecting features within the device, increasing density, promoting symmetry, improving device performance, and enhancing power efficiency. See also, MPEP 2144.04 (IV)(A) Changes in Size/Proportion.
Regarding claim 18, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
the trench portion [14-17, Fig. 2-9] has a longitudinal length in a first direction and has a lateral length in a second direction in the top view.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
a doping concentration distribution of the high resistance region in the first direction is flatter than the doping concentration distribution of the high resistance region in the second direction.
Chen et al. teaches:
a doping concentration distribution of the high resistance region [38-2, paragraph [0095], Fig. 1] in the first direction [Y-axis] is flatter than the doping concentration distribution of the high resistance region [38-2, Fig. 1] in the second direction [X-axis].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include a doping concentration distribution of the high resistance region in the first direction is flatter than the doping concentration distribution of the high resistance region in the second direction, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. As a result, a difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 19, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
an active portion [1-2, Fig. 1-9] enclosed by the well region [109, Fig. 1-7] in the top view, wherein
the lower end region [105, paragraph [0138], [0148], [0155], [0161], [0163], Fig. 1-9] is provided in a region occupying 90% or more of the active portion [1-2, Fig. 1-9] in the top view.
Regarding claim 20, Vellei et al. and Chen et al. teach the semiconductor device according to claim 5.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
the high resistance region is arranged at a corner of the active portion in the top view.
Chen et al. teaches:
the high resistance region [38-2, paragraph [0089-0090], [0095], Fig. 1, 14] is arranged at a corner of the active portion [11, Fig. 1, 14] in the top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include the high resistance region is arranged at a corner of the active portion in the top view, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. As a result, a difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 22, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
a doping concentration of the lower end region [105, paragraph [0131], Fig. 1-9] is higher than a doping concentration of the base region [102, paragraph [0062], Fig. 1-9].
Although not specifically mentioned, paragraph [0131] teaches the acceptable range of dopant concentration in lower end region [105]. Paragraph [0062] teaches the acceptable range of dopant concentration in base region [102]. These ranges overlap where lower end region [105] would have a higher dopant concentration than the dopant concentration of base region [102]. Lower doping concentrations allow for more precise control of electrical properties, maintain wider depletion regions and optimize device performance, smaller increase in free charge carriers. See also, MPEP 2144.05(I) Overlapping, Approaching, and Similar Ranges, Amounts and Proportions.
Regarding claim 24, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. further teaches:
the semiconductor substrate [10, Fig. 1-9] includes a mesa portion [18/19, paragraph [0012], [0073], [0079], [0084], [0087-0088], [0091], [0094], Fig. 2-9] which is a region sandwiched between a plurality of the trench portions [14-17, Fig. 1-9],
the drift region [100, paragraph [0073], [0112], [0123-0125], Fig. 1-9] is also provided in the mesa portion [18/19, Fig. 1-9].
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
part of the drift region provided in the mesa portion and part of the high resistance region overlap each other in the top view.
Chen et al. teaches:
part of the drift region [16, Fig. 1] provided in the mesa portion [corresponding to location between trenches 18, Fig. 1, 14] and part of the high resistance region [38-2, Fig. 1, 14] overlap each other in the top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include part of the drift region provided in the mesa portion and part of the high resistance region overlap each other in the top view, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. As a result, a difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 25, Vellei et al. teaches:
A method for manufacturing a semiconductor device [1, Fig. 1-9], the method forming:
in a semiconductor substrate [10, paragraph [0041-0042], Fig. 1-9] which has an upper surface and a lower surface and includes a drift region [100, paragraph [0042], Fig. 1-9] of a first conductivity type [N-type],
a base region [102, paragraph [0064], Fig. 1-9] of a second conductivity type [P-type] provided between the drift region [100, Fig. 1-9] and the upper surface of the semiconductor substrate [10, Fig. 1-9];
a plurality of trench portions [14-17, paragraph [0096-0098], Fig. 1-9] provided from the upper surface of the semiconductor substrate [10, Fig. 1-9] to below the base region [102, Fig. 1-9];
a lower end region [105, paragraph [0087], [0098], [0110], [0130], Fig. 1-9] of the second conductivity type [P-type] provided in contact with lower ends of two or more trench portions [14-17, Fig. 1-9] among the plurality of trench portions [14-17, Fig. 1-9];
a well region [109, paragraph [0147-0151], Fig. 6A, 7] of the second conductivity type [P-type] which is arranged at a position different from the lower end region [105, Fig. 6A, 7] in a top view, is provided from the upper surface of the semiconductor substrate [10, Fig. 1-9] to below the base region [102, Fig. 1-9], and has a higher doping concentration than the base region [102, paragraph [0064], [0151], Fig. 1-9]
Vellei et al. does not teach:
a high resistance region of the second conductivity type which is arranged between the lower end region and the well region in the top view and has a lower doping concentration than the lower end region.
Chen et al. teaches:
a high resistance region [38-2, paragraph [0089], [0091], [0095], [0097], Fig. 1] of the second conductivity type [P-type] which is arranged between the lower end region [38-1, paragraph [0089-0091], Fig. 1] and the well region [51, paragraph [0087], Fig. 1] in the top view and has a lower doping concentration than the lower end region [38-1, paragraph [0089-0091], [0095], Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. to include a high resistance region of the second conductivity type which is arranged between the lower end region and the well region in the top view and has a lower doping concentration than the lower end region, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 26, Vellei et al. and Chen et al. teach the method for manufacturing a semiconductor device according to claim 25.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
a dopant of the second conductivity type is implanted into both a region where the high resistance region is to be formed and a region where the lower end region is to be formed, and
the dopant of the second conductivity type is further implanted into the region where the lower end region is to be formed.
Chen et al. teaches:
a dopant of the second conductivity type [P-type] is implanted into both a region where the high resistance region [41-2, paragraph [0197-0198], Fig. 30] is to be formed and a region where the lower end region [41-1, Fig. 30] is to be formed, and
the dopant of the second conductivity type [P-type] is further implanted into the region where the lower end region [41-1, paragraph [0197-0198], Fig. 30] is to be formed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include a dopant of the second conductivity type is implanted into both a region where the high resistance region is to be formed and a region where the lower end region is to be formed, and the dopant of the second conductivity type is further implanted into the region where the lower end region is to be formed, for the purpose of enhancing the effect of preventing the depletion layer from extending in the longitudinal and lateral directions, inhibiting the depletion layer from extending in the longitudinal and lateral directions and reaching the first P layer. A difference in electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer becomes substantially zero. Thus, it is possible to suppress application of high electric fields to that portion of the first P layer.
Regarding claim 27, Vellei et al. and Chen et al. teach the method for manufacturing a semiconductor device according to claim 25.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
dopants of the second conductivity type having different concentrations are respectively implanted into a region where the high resistance region is to be formed and a region where the lower end region is to be formed.
Chen et al. teaches:
dopants of the second conductivity type [P-type] having different concentrations [Pmin(1), P(2), paragraph [0198], [0201], [0205], Fig. 30] are respectively implanted into a region where the high resistance region [41-2, Fig. 30] is to be formed and a region where the lower end region [41-1, Fig. 30] is to be formed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include dopants of the second conductivity type having different concentrations are respectively implanted into a region where the high resistance region is to be formed and a region where the lower end region is to be formed, for the purpose of a difference in the electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer 41-1 becomes substantially zero. Thus, it is possible to suppress the application of a high electric field to that portion of the first P layer 41-1.
Regarding claim 28, Vellei et al. and Chen et al. teach the method for manufacturing a semiconductor device according to claim 25.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
a dopant of the second conductivity type is implanted into a region away from a region where the lower end region is to be formed, in a region where the high resistance region is to be formed, and a heat treatment is performed, to diffuse the dopant toward the region where the lower end region is to be formed.
Chen et al. teaches:
a dopant of the second conductivity type [P-type] is implanted into a region away from a region where the lower end region [41-1, paragraph [0198], Fig. 30] is to be formed, in a region where the high resistance region [41-2, paragraph [0198], Fig. 30] is to be formed, and a heat treatment is performed, to diffuse the dopant toward the region where the lower end region [41-1, Fig. 30] is to be formed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include a dopant of the second conductivity type is implanted into a region away from a region where the lower end region is to be formed, in a region where the high resistance region is to be formed, and a heat treatment is performed, to diffuse the dopant toward the region where the lower end region is to be formed, for the purpose of difference in the electrostatic potential between the inside and outside of a high-curvature portion in cross-section shape of the first P layer 41-1 becomes substantially zero. Thus, it is possible to suppress the application of a high electric field to that portion of the first P layer 41-1.
Claims 8, 21, 23, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Vellei et al. (US 20190123185 A1), in view of Chen et al. (US 20150014741 A1) as applied to claims 1 and 25 above, and further in view of Matsuura (US 20180069110 A1).
Regarding claim 8, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. do not teach:
the high resistance region has a lower doping concentration than the base region.
Matsuura teaches:
the high resistance region [36, paragraph [0100], Fig. 9] has a lower doping concentration than the base region [24, paragraph [0108], Fig. 14].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Matsuura into the teachings of Vellei et al. and Chen et al. to include the high resistance region has a lower doping concentration than the base region, for the purpose of increased conductivity, improved performance, promoting the discharge of holes at the time of a turn-off.
Regarding claim 21, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. do not teach:
the high resistance region is not provided in the upper surface of the semiconductor substrate.
Matsuura teaches:
the high resistance region [36, paragraph [0100], Fig. 1, 9, 27-29, 31, 33, 35] is not provided in the upper surface of the semiconductor substrate [64, paragraph [0061], Fig. 1, 9, 27-29, 31, 33, 35].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Matsuura into the teachings of Vellei et al. and Chen et al. to include the high resistance region is not provided in the upper surface of the semiconductor substrate, for the purpose of precision control over the depth and dosage of dopants, improving performance.
Regarding claim 23, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. do not teach:
the high resistance region spreads over the plurality of trench portions.
Matsuura teaches:
the high resistance region [36, paragraph [0141-0143], [0146], [0151-0152], Fig. 29, 31, 33] spreads over the plurality of trench portions [60, G1, G2, E1-E6, paragraph [0141-0143], [0146], [0151-0152], Fig. 29, 31, 33].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Matsuura into the teachings of Vellei et al. and Chen et al. to include the high resistance region spreads over the plurality of trench portions, for the purpose of serving as an exit for the holes supplied from the collector electrode layer, a high level of pattern precision is not required, making it easier to manufacture the device, freedom of arrangement thereof in a plane of the semiconductor substrate increases, in the on state of the IGBT element, the supply of electrons from the N+ type emitter region is not prevented.
Regarding claim 29, Vellei et al. and Chen et al. teach the method for manufacturing a semiconductor device according to claim 25.
Vellei et al. and Chen et al. do not teach:
in the forming the high resistance region, a mask masks a region other than the plurality of trench portions, and a dopant is implanted into the semiconductor substrate via the plurality of trench portions.
Matsuura teaches:
in the forming the high resistance region [36, paragraph [0100], Fig. 9], a mask [42, paragraph [0100], Fig. 9] masks a region other than the plurality of trench portions [60, paragraph [0100], Fig. 9], and a dopant is implanted into the semiconductor substrate [64, paragraph [0061], Fig. 9] via the plurality of trench portions [60, Fig. 9].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Matsuura into the teachings of Vellei et al. and Chen et al. to include in the forming the high resistance region, a mask masks a region other than the plurality of trench portions, and a dopant is implanted into the semiconductor substrate via the plurality of trench portions, for the purpose of a mask protects features underneath from subsequent processes, improving precision control over the depth and dosage of dopants, improving performance.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Vellei et al. (US 20190123185 A1), in view of Chen et al. (US 20150014741 A1) as applied to claim 1 above, and further in view of Ma et al. (US 20190006507 A1).
Regarding claim 9, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
a doping concentration of the high resistance region is equal to or lower than a doping concentration of the lower end region.
Chen et al. teaches:
a doping concentration of the high resistance region [38-2, paragraph [0095], Fig. 1] is equal to or lower than a doping concentration of the lower end region [38-1, Fig. 1].
Vellei et al. and Chen et al. do not teach:
a doping concentration of the high resistance region is equal to or lower than 10% of a doping concentration of the lower end region.
Ma et al. teaches:
a doping concentration of the high resistance region [65, paragraph [0044], Fig. 13] is equal to or lower than 10% of a doping concentration of the lower end region [69, paragraph [0044], Fig. 13].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ma et al. into the teachings of Vellei et al. and Chen et al. to include a doping concentration of the high resistance region is equal to or lower than 10% of a doping concentration of the lower end region, for the purpose of lower doping concentrations allow for more precise control of electrical properties, maintain wider depletion regions and optimize device performance, smaller increase in free charge carriers. See also, MPEP 2144.05(I) Overlapping, Approaching, and Similar Ranges, Amounts and Proportions.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Vellei et al. (US 20190123185 A1), in view of Chen et al. (US 20150014741 A1) as applied to claim 10 above, and further in view of Naito (JP 2019161168 A). Naito (JP 2019161168 A) will hereby be referred to as Naito ‘168.
Regarding claim 11, Vellei et al. and Chen et al. teach the semiconductor device according to claim 10.
Vellei et al. and Chen et al. do not teach:
a doping concentration at the peak in the high resistance region is equal to or higher than 0.5 times and equal to or lower than 1.5 times a doping concentration of the lower end region.
Naito ‘168 teaches:
a doping concentration at the peak in the high resistance region [22, paragraph [0114], Fig. 2b-3] is equal to or higher than 0.5 times and equal to or lower than 1.5 times a doping concentration of the lower end region [27, paragraph [0114], Fig. 2b-3].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Naito ‘168 into the teachings of Vellei et al. and Chen et al. to include a doping concentration at the peak in the high resistance region is equal to or higher than 0.5 times and equal to or lower than 1.5 times a doping concentration of the lower end region, for the purpose of lower doping concentrations allow for more precise control of electrical properties, maintain wider depletion regions and optimize device performance, smaller increase in free charge carriers. See also, MPEP 2144.05(I) Overlapping, Approaching, and Similar Ranges, Amounts and Proportions.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Vellei et al. (US 20190123185 A1), in view of Chen et al. (US 20150014741 A1) as applied to claim 1 above, and further in view of Naito (CN 111418068 A). Naito (CN 111418068 A) will hereby be referred to as Naito ‘068.
Regarding claim 16, Vellei et al. and Chen et al. teach the semiconductor device according to claim 1.
Vellei et al. and Chen et al. disclose the above claimed subject matter.
However, Vellei et al. does not teach:
an accumulation region which is provided between the base region and the drift region.
part of the accumulation region and part of the high resistance region overlap each other in the top view.
Chen et al. teaches:
an accumulation region [20, paragraph [0071-0072], [0075], Fig. 1] which is provided between the base region [19, paragraph [0071-0072], [0075], Fig. 1] and the drift region [16, paragraph [0072], [0075], Fig.1]
part of the accumulation region [20, Fig. 1] and part of the high resistance region [38-2, Fig. 1] overlap each other in the top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Vellei et al. and Chen et al. to include an accumulation region which is provided between the base region and the drift region, part of the accumulation region and part of the high resistance region overlap each other in the top view, for the purpose of storing and modulating charge, and improves control of device.
Vellei et al. and Chen et al. do not teach:
an accumulation region which is provided between the base region and the drift region and has a higher doping concentration than the drift region.
Naito ‘068 teaches:
an accumulation region [16, paragraph [0098], Fig. 2] which is provided between the base region [14, Fig. 2] and the drift region [18, Fig. 2] and has a higher doping concentration than the drift region [18, Fig. 2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Naito ‘068 into the teachings of Vellei et al. and Chen et al. to include an accumulation region which is provided between the base region and the drift region and has a higher doping concentration than the drift region, for the purpose of improving carrier injection promotion effect (IE effect), thereby reducing the turn-on voltage.
Conclusion
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/D.M.H./ Examiner, Art Unit 2815 03/13/2026
/MONICA D HARRISON/ Primary Examiner, Art Unit 2815