DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: A Semiconductor Device Comprising a Transistor Portion and a Diode Portion with Regions that have Different Doping Concentrations.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 2, 5-7, 10-11, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi (US 2018/0308839).
Regarding Claim 1, Takahashi discloses a semiconductor device (IGBT and a diode [0070] Fig 4) comprising: a semiconductor substrate (semiconductor substrate SB [0069]) which has an upper surface (shown in annotated Fig 4) and a lower surface (shown in annotated Fig 4) and is provided with a drift region (n-drift region DRI [0091]) of a first conductivity type (n-type);
a transistor portion (area where gate electrode GE [0081] is located, shown in annotated Fig 4) which is provided on the semiconductor substrate (SB); and
a diode portion (area where the gate electrode is not present, shown in annotated Fig 4) which is provided on the semiconductor substrate (SB), wherein each of the transistor portion (area where gate electrode GE [0081] is located, shown in annotated Fig 4) and the diode portion (area where the gate electrode is not present, shown in annotated Fig 4) has one or more trench contact portions (shown in annotated Fig 4) provided from the upper surface (shown in annotated Fig 4) of the semiconductor substrate (SB) in a depth direction (vertical direction) of the semiconductor substrate (SB) and extending on the upper surface (shown in annotated Fig 4) of the semiconductor substrate (SB) in an extending direction (into the page direction),
the transistor portion (area where gate electrode GE [0081] is located, shown in annotated Fig 4) has a first bottom region (shown in annotated Fig 4) of a second conductivity type (p-type [0111]) provided in contact with a bottom of any one of the one or more trench contact portions (shown in annotated Fig 4),
the diode portion (area where the gate electrode is not present, shown in annotated Fig 4) has a second bottom region (shown in annotated Fig 4) of the second conductivity type (p-type [0111]) provided in contact with a bottom of any one of the one or more trench contact portions (shown in annotated Fig 4), and
a length of the first bottom region (shown in annotated Fig 4) in the extending direction (into the page direction) is larger (shown in annotated Fig 37) than a length of the second bottom region (shown in annotated Fig 4) in the extending direction (into the page direction).
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Regarding Claim 2, Takahashi discloses the limitations of claim 1 as explained above. Takahashi further discloses
wherein a plurality of the second bottom regions (shown above in annotated Fig 4) is discretely arranged in the diode portion (area where the gate electrode is not present, shown above in annotated Fig 4, and further demonstrated in plan views Fig 29/Fig 33/37 that have multiple CR regions which have the second bottom portions below them) along the extending direction (into the page direction Fig 4).
Regarding Claim 5, Takahashi discloses the limitations of claim 1 as explained above. Takahashi further discloses
wherein the transistor portion (area where gate electrode GE [0081] is located, shown in annotated Fig 4) includes: one or more emitter regions (n-type emitter regions EM [0085]) of the first conductivity type (n-type) which are provided in contact with the upper surface (shown in annotated Fig 4) of the semiconductor substrate (SB) and have a higher doping concentration (drift region has n- and EM has n concentrations shown in Fig 4) than the drift region (n-drift region DRI [0091]);
one or more base regions (p-type body region BO [0093]) of the second conductivity type (p-type) which are provided between the emitter regions (EM) and the drift region (DRI);
one or more contact regions (p-type body contact region BC [0106]) of the second conductivity type (p-type) which are provided in contact with the upper surface (shown in annotated Fig 4) of the semiconductor substrate (SB), are connected to the one or more base regions (BO) and have a higher doping concentration (BC has p+ concentration [0106] and BO has p concentration shown in Fig 4) than the one or more base regions (BO); and
one or more gate trench portions (trench where gate electrodes GE and gate groove GTR [0081] are located) which are in contact with the one or more emitter regions (EM) and the one or more base regions (BO) and are provided from the upper surface (shown in annotated Fig 4) toward the lower surface (shown in annotated Fig 4), and the extending direction is a longitudinal direction (into the page direction Fig 4/y direction Fig 37) in which the one or more gate trench portions (trench where gate electrodes GE and gate groove GTR [0081] are located) extend.
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Regarding Claim 6, Takahashi discloses the limitations of claim 5 as explained above. Takahashi et al further discloses
wherein the one or more contact regions (BC) are arranged (shown in annotated Fig 37) with the one or more emitter regions (EM) in the extending direction (into the page direction Fig 4/y direction Fig 37), and the first bottom region (shown above in annotated Fig 4/corresponding to CR Fig 37) connects (electrically connects) two of the one or more contact regions (BC) arranged away from each other in the extending direction (into the page direction Fig 4/y direction Fig 37).
wherein the one or more contact regions (BC) are arranged alternately with the one or more emitter regions (EM) in the extending direction (into the page direction Fig 4/y direction Fig 37), and the first bottom region (shown above in annotated Fig 4) connects (electrically connects) two of the one or more contact regions (BC) arranged away from each other in the extending direction (into the page direction Fig 4/y direction Fig 37).
Regarding Claim 7, Takahashi discloses the limitations of claim 6 as explained above. Takahashi further discloses
wherein a partial region of the first bottom region (shown above in annotated Fig 4) is provided on a side of the upper surface of the semiconductor substrate (shown above in annotated Fig 4) relative to a lower end of each of the one or more contact regions (BC).
Regarding Claim 10, Takahashi discloses the limitation of claim 5 as explained above. Takahashi further discloses
wherein a lower end of each of the one or more trench contact portions (BC) is arranged on a side of the upper surface (shown above in annotated Fig 4) of the semiconductor substrate (SB) relative to a lower end of each of the one or more emitter regions (EM).
Regarding Claim 11, Takahashi discloses the limitations of claim 1 as explained above. Takahashi further discloses
wherein the one or more trench contact portions (shown in annotated Fig 4) of the diode portion (area where the gate electrode is not present, shown in annotated Fig 4) are provided up to below the one or more trench contact portions (shown in annotated Fig 4) of the transistor portion (area where gate electrode GE [0081] is located, shown in annotated Fig 4).
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Regarding Claim 16, Takahashi discloses the limitations of claim 5 as explained above. Takahashi further discloses
wherein the transistor portion (shown in annotated Fig 4) further has a plurality of accumulation regions (n-type hole barrier region HB [0138] Fig 4) which is provided in the depth direction (vertical direction Fig 4) between the one or more base regions (BO) and the drift region (n-drift region DRI [0091]) and which has a higher doping concentration (n is higher than n-) than the drift region (DRI).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-4, 8-9, 13-14, and 17-23 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2018/0308839) in view of Naito (US 2017/0047319).
Regarding Claim 3, Takahashi discloses the limitations of claim 1 as explained above. Takahashi does not disclose
further comprising: a boundary portion which is provided between the transistor portion and the diode portion and includes the one or more trench contact portions,
wherein the boundary portion has a third bottom region of the second conductivity type provided in contact with a bottom of any one of the one or more trench contact portions, and
the length of the first bottom region in the extending direction is larger than a length of the third bottom region in the extending direction.
Naito’319, in the related art of semiconductor devices that include IGBT devices, discloses
further comprising: a boundary portion (boundary portion 12 [0027] Fig 2) which is provided between the transistor portion (IGBT section 20 [0027]) and the diode portion SJ-MOSFET section 10 functions as a diode [0036]) and includes the one or more trench contact portions (shown in annotated Fig 2),
wherein the boundary portion (12) has a third bottom region (shown in annotated Fig 2) of the second conductivity type (p++ Fig 2) provided in contact (electrical contact) with a bottom of any one of the one or more trench contact portions (shown in annotated Fig 2).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi to include a boundary portion as taught by Naito’319 in order to avoid sudden changes that cause break down and damage [0049]. Further, a person of ordinary skill in the art would have recognized that avoiding break down and damage would be advantageous in optimizing the electrical function capabilities while maintained reliability of the device (see MPEP 2143.I(D)).
The combination of Takahashi and Naito’319 now discloses
the length of the first bottom region (shown in annotated Fig 4 Takahashi/shown in annotated Fig 2 Naito’319) in the extending direction (into the page direction shown in annotated Fig 4 Takahashi/vertical direction shown in annotated Fig 37 Takahashi/into the page direction shown in annotated Fig 2 Naito’319) is larger than a length of the third bottom region (shown in annotated Fig 2 Naito’319) in the extending direction (into the page direction shown in annotated Fig 4 Takahashi/vertical direction shown in annotated Fig 37 Takahashi/into the page direction shown in annotated Fig 2 Naito’319).
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Regarding Claim 4, the combination of Takahashi and Naito’319 discloses the limitations of claim 3 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the length of the second bottom region (shown in annotated Fig 4 and Fig 37 Takahashi/shown in annotated Fig 2 Naito’319) in the extending direction (into the page direction shown in annotated Fig 4 Takahashi/vertical direction shown in annotated Fig 37 Takahashi/into the page direction shown in annotated Fig 2 Naito’319) is the same as the length of the third bottom region (shown in annotated Fig 3 Takahashi/shown in annotated Fig 2 Naito’319) in the extending direction (into the page direction shown in annotated Fig 4 Takahashi/vertical direction shown in annotated Fig 37 Takahashi/into the page direction shown in annotated Fig 2 Naito’319).
Regarding Claim 8, Takahashi discloses the limitations of claim 7 as explained above. Takahashi does not disclose
wherein a doping concentration of the first bottom region is higher than a doping concentration of the one or more contact regions.
Naito’319, in the related art of semiconductor devices that include IGBT devices, discloses
a doping concentration (p++ Fig 2 Naito’319) of the first bottom region (shown in annotated Fig 2 Naito’319).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi to include a doping concentration of the first bottom region is higher than a doping concentration of the contact region as taught by Naito’319 in order to optimize the electrical conductivity of the device. Further, a person of ordinary skill in the art would have recognized that optimizing the electrical conductivity of the device can optimize electrical functioning while minimize the risk of damage which would improve the reliability of the device (see MPEP 2143.I(D)).
The combination of Takahashi and Naito’319 now discloses
a doping concentration (p++ Fig 2 Naito’319) of the first bottom region (shown above in annotated Fig 2 Naito’319) is higher than a doping concentration (p-type Fig 4 Takahashi) of the contact region (BC Fig 4 Takahashi).
Regarding Claim 9, the combination of Takahashi and Naito’319 discloses the limitations of claim 8 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the first bottom region (shown above in annotated Fig 4 Takahashi/shown above in annotated Fig 2 Naito’319) has a first concentration peak of a doping concentration (p++ Naito’319) in a depth direction (vertical direction Fig 4 Takahashi/Fig 2 Naito’319),
the contact region (BC Takahashi) has a second concentration peak (p+ Takahashi) of the doping concentration in the depth direction (vertical direction Fig 4 Takahashi/Fig 2 Naito’319), and
a half width at half maximum of the first concentration peak (p++ Naito’319) is smaller than a half width at half maximum of the second concentration peak (p+ Takahashi) (the examiner notes that this is because of p++ being significantly greater than p+ such that it meets the limitations of the claim).
Regarding Claim 13, the combination of Takahashi and Naito’319 discloses the limitations of claim 3 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the one or more trench contact portions (shown in annotated Fig 2 Naito’319) of the boundary portion (12 Naito’319) are provided up to below both the one or more trench contact portions (shown in annotated Fig 2 Naito’319) of the diode portion (10 Naito’319) and the one or more trench contact portions (shown in annotated Fig 2 Naito’319) of the transistor portion (20 Naito’319).
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Regarding Claim 14, the combination of Takahashi and Naito’319 discloses the limitations of claim 3 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the one or more trench contact portions (shown in annotated Fig 2 Naito’319) of the boundary portion (12 Naito’319) have a smaller width (shown in annotated Fig 2 Naito’319) on the upper surface of the semiconductor substrate (semiconductor substrate 100 [0025] Naito’319) than both the one or more trench contact portions (shown in annotated Fig 2 Naito’319) of the diode portion (10 Naito’319) and the one or more trench contact portions (shown in annotated Fig 2 Naito’319) of the transistor portion (20 Naito’319).
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Regarding Claim 17, Takahashi (US 2018/0308839) discloses a semiconductor device (IGBT and a diode [0070] Fig 4) comprising: a semiconductor substrate (semiconductor substrate SB [0069]) which has an upper surface (shown in annotated Fig 4) and a lower surface (shown in annotated Fig 4) and is provided with a drift region (n-drift region DRI [0091]) of a first conductivity type (n-type); and
a transistor portion (area where gate electrode GE [0081] is located, shown in annotated Fig 4) which is provided on the semiconductor substrate (SB),
wherein the transistor portion (area where gate electrode GE [0081] is located, shown in annotated Fig 4) includes: one or more trench contact portions (shown in annotated Fig 4) which are provided from the upper surface (shown in annotated Fig 4) of the semiconductor substrate (SB) in a depth direction (vertical direction) of the semiconductor substrate (SB);
a first bottom region (shown in annotated Fig 4) of a second conductivity type (p-type [0111]) which is provided in contact with a bottom of any one of the one or more trench contact portions (shown in annotated Fig 4);
an emitter region (n-type emitter regions EM [0085]) of the first conductivity type (n-type) which is provided in contact with the upper surface (shown in annotated Fig 4) of the semiconductor substrate (SB) and has a higher doping concentration (drift region has n- and EM has n concentrations shown in Fig 4) than the drift region (n-drift region DRI [0091]);
a base region (p-type body region BO [0093]) of the second conductivity type (p-type) which is provided between the emitter region (EM) and the drift region (DRI); and
a contact region (p-type body contact region BC [0106]) of the second conductivity type (p-type) which is provided in contact with the upper surface (shown in annotated Fig 4) of the semiconductor substrate (SB), is connected to the base region (BO) and has a higher doping concentration (BC has p+ concentration [0106] and BO has p concentration shown in Fig 4) than the base region (BO).
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Takahashi does not disclose
a doping concentration of the first bottom region is higher than a doping concentration of the contact region.
Naito’319, in the related art of semiconductor devices that include IGBT devices, discloses
a doping concentration (p++ Fig 2 Naito’319) of the first bottom region (shown in annotated Fig 2 Naito’319).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi to include a doping concentration of the first bottom region is higher than a doping concentration of the contact region as taught by Naito’319 in order to optimize the electrical conductivity of the device. Further, a person of ordinary skill in the art would have recognized that optimizing the electrical conductivity of the device can optimize electrical functioning while minimize the risk of damage which would improve the reliability of the device (see MPEP 2143.I(D)).
The combination of Takahashi and Naito’319 now discloses
a doping concentration (p++ Fig 2 Naito’319) of the first bottom region (shown above in annotated Fig 2 Naito’319) is higher than a doping concentration (p-type Fig 4 Takahashi) of the contact region (BC Fig 4 Takahashi).
Regarding Claim 18, the combination of Takahashi and Naito’319 discloses the limitations of claim 17 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the first bottom region (shown above in annotated Fig 4 Takahashi/shown above in annotated Fig 2 Naito’319) has a first concentration peak of a doping concentration (p++ Naito’319) in a depth direction (vertical direction Fig 4 Takahashi/Fig 2 Naito’319),
the contact region (BC Takahashi) has a second concentration peak (p+ Takahashi) of the doping concentration in the depth direction (vertical direction Fig 4 Takahashi/Fig 2 Naito’319), and
a half width at half maximum of the first concentration peak (p++ Naito’319) is smaller than a half width at half maximum of the second concentration peak (p+ Takahashi) (the examiner notes that this is because of p++ being significantly greater than p+ such that it meets the limitations of the claim).
Regarding Claim 19, the combination of Takahashi and Naito’319 discloses the limitations of claim 17 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the one or more trench contact portions (shown above in annotated Fig 4 Takahashi/shown above in annotated Fig 2 Naito’319) extend on the upper surface of the semiconductor substrate (shown above in annotated Fig 4 Takahashi) in an extending direction (into the page direction Fig 4 Takahashi/vertical direction Fig 37 Takahashi/into the page direction Fig2 Naito’319), and
wherein a plurality of the first bottom regions (shown above in annotated Fig 4 Takahashi/shown above in annotated Fig 2 Naito’319) is discretely arranged along the extending direction (into the page direction Fig 4 Takahashi/vertical direction Fig 37 Takahashi/into the page direction Fig 2 Naito’319).
Regarding Claim 20, the combination of Takahashi and Naito’319 discloses the limitations of claim 17 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the bottom of each of the one or more trench contact portions (shown above in annotated Fig 4 Takahashi) is arranged on a side of the upper surface of the semiconductor substrate (shown above in annotated Fig 4 Takahashi) relative to both a lower end of the emitter region (EM Takahashi) and a lower end of the contact region (BC Takahashi).
Regarding Claim 21, the combination of Takahashi and Naito’319 discloses the limitations of claim 17 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the bottom of each of the one or more trench contact portions (shown above in annotated Fig 4 Takahashi) is arranged on a side of the upper surface of the semiconductor substrate (shown above in annotated Fig 4 Takahashi) relative to a lower end of the emitter region (EM Takahashi), and a lower end of the first bottom region (shown above in the annotated Fig 4 Takahashi) is arranged on a side of the lower surface of the semiconductor substrate (shown above in annotated Fig 4 Takahashi) relative to the lower end of the emitter region (EM Takahashi).
Regarding Claim 22, the combination of Takahashi and Naito’319 discloses the limitations of claim 17 as explained above. The combination of Takahashi and Naito’319 further discloses
wherein the one or more trench contact portions (shown above in annotated Fig 4 Takahashi) extend on the upper surface of the semiconductor substrate (shown above in annotated Fig 4 Takahashi) in an extending direction (into the page direction Fig 4 Takahashi/vertical direction Fig 37 Takahashi/into the page direction Fig2 Naito’319), and a length of the first bottom region (shown above in annotated Fig 4 Takahashi) in the extending direction (into the page direction Fig 4 Takahashi/vertical direction Fig 37 Takahashi/into the page direction Fig2 Naito’319) is smaller than a length of the one or more trench contact portions (shown above in annotated Fig 4 Takahashi) in the extending direction (into the page direction Fig 4 Takahashi/vertical direction Fig 37 Takahashi/into the page direction Fig2 Naito’319).
Regarding Claim 23, the combination of Takahashi and Naito’319 discloses the limitations of claim 17 as explained above. The combination of Takahashi and Naito’319 further discloses
further comprising: a diode portion (shown above in annotated Fig 4 Takahashi) which is provided on the semiconductor substrate (SB Takahashi), wherein each of the transistor portion (shown above in annotated Fig 4 Takahashi) and the diode portion (shown above in annotated Fig 4 Takahashi) has one or more trench contact portions (shown above in annotated Fig 4 Takahashi) provided from the upper surface (shown above in annotated Fig 4 Takahashi) of the semiconductor substrate (SB Takahashi) in a depth direction (vertical direction Fig 4 Takahashi) of the semiconductor substrate (SB Takahashi) and extending on the upper surface (shown above in annotated Fig 4 Takahashi) of the semiconductor substrate (SB Takahashi) in an extending direction (into the page direction Fig 4 Takahashi/vertical direction Fig 37 Takahashi/into the page direction Fig2 Naito’319),
the diode portion (shown above in annotated Fig 4 Takahashi) has a second bottom region (shown above in annotated Fig 4 Takahashi) of the second conductivity type (p-type Takahashi) provided in contact with a bottom of any one of the one or more trench contact portions (shown above in annotated Fig 4 Takahashi), and a length of the first bottom region (shown above in annotated Fig 4 Takahashi) in the extending direction (into the page direction Fig 4 Takahashi/vertical direction Fig 37 Takahashi/into the page direction Fig2 Naito’319 )is smaller than a length of the second bottom region (shown above in annotated Fig 4 Takahashi) in the extending direction (into the page direction Fig 4 Takahashi/vertical direction Fig 37 Takahashi/into the page direction Fig2 Naito’319).
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2018/0308839) in view of Naito’099 (WO 2018/052099).
Regarding Claim 12, Takahashi discloses the limitations of claim 1 as explained above. Takahashi does not disclose
wherein the one or more trench contact portions of the diode portion have a smaller width on the upper surface of the semiconductor substrate than the one or more trench contact portions of the transistor portion.
Naito’099, in the related art of semiconductor devices that include IGBT devices, discloses
wherein the one or more trench contact portions (contact trench 27 [page 14, lines 26-46] Fig 11) of the diode portion (diode portion 80 [page 14, lines 26-46] Fig 11) have a smaller width on the upper surface of the semiconductor substrate (shown in annotated Fig 11) than the one or more trench contact portions (27) of the transistor portion (transistor portion 70 [page 14, lines 26-46] Fig 11)).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi to include wherein the one or more trench contact portions of the diode portion have a smaller width on the upper surface of the semiconductor substrate than the one or more trench contact portions of the transistor portion as taught by Naito’099 in order to suppress latch-up by pulling out holes in the transistor portion which is not necessary in the diode portion [page 14, lines 26-46]) and because it would have been an obvious matter of design choice to optimize the width of the trench contact portions since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that suppressing latch up would be advantageous in that it would help optimize the electrical function of the device while preventing unwanted damage from undesirable electrical effects (see MPEP 2143.I(D)).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2018/0308839) in view of Nemati et al (US 6703646).
Regarding Claim 15, Takahashi discloses the limitation of claim 5 as explained above. Takahashi further discloses
wherein the diode portion (shown in annotated Fig 4) has an anode region (AN1 [0106] and AN2 [0112]) of the second conductivity type (p-type) provided between the drift region (n-drift region DRI [0091]) and the upper surface (shown in annotated Fig 4) of the semiconductor substrate (SB), and a doping concentration of the anode region (AN1 and AN2) is the same as a doping concentration of the one or more base regions (BO), and
a doping concentration of the anode region (AN1 and AN2 comprise BO (p-type), (LA p+ type), and BC (p+ type)) is the same or greater than a doping concentration of the one or more base regions (BO).
Takahashi does not disclose
a doping concentration of the anode region is lower than a doping concentration of the one or more base regions.
Nemati et al, in the related art of semiconductor devices that include transistors, discloses
a doping concentration of the anode region (anode emitter region portion 211 [column 5, lines 25-45] Fig 2) is lower (lesser dopant concentration [column 5, lines 25-45]) than a doping concentration of the one or more base regions (adjacent N-base region 214 [column 5, lines 25-45] Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi to include wherein a doping concentration of the anode region is lower than a doping concentration of the one or more base regions as taught by Nemati et al in order to increase the current density [column 5, lines 25-45], and to have the type of dopant be p-type to meet the requirements of Takahashi, since changing from n-type to p-type or vice versa is well within the scope of one of ordinary skill in the art. Further, a person of ordinary skill in the art would have recognized that increasing the current density would improve the performance, speed, and efficiency of the device (see MPEP 2143.I(D)).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Naito (US 2018/0350961) which discloses an IGBT device [0078], and Okumura et al (US 2013/0069146) which discloses a power MOSFET device [0003].
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812