CTFR 18/469,601 CTFR 97482 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendments Applicant’s amendments filed on 5/11/2026 have been entered. Response to Arguments Applicant’s arguments filed on 5/11/2026 regarding Claims 5-6 have been fully considered and are persuasive, therefore the prior art rejections of Claims 5-6 have been withdrawn. Applicant’s arguments filed on 5/11/2026 regarding Claims 1-4 have been fully considered. However, they are not persuasive, therefore the prior art rejections of Claims 1-4 will be maintained. Regarding Claim 1 , Applicant argues that the prior art reference Hanaoka et al does not disclose a configuration in which a conductive layer (70) and an electrode (14) are electrically connected to a via hole (50). The examiner disagrees in that the conductive layer (70) extends through the via hole (50) and is on the top and bottom of the device shown in Fig 9, and although the electrode (14) physically connects to the conductive layer (70) in the top area of the device, the conductive layer (70) and electrode (14) are electrically connected in the broadest reasonable interpretation in that electrically current can flow through the top portion of the conductive layer (70), portion of (70) in the via hole (50), and the bottom portion of conductive layer (70) together as a whole structure shown in annotated Fig 9). PNG media_image1.png 644 1279 media_image1.png Greyscale Further, regarding Claim 1 , Applicant argues that the reference Hanaoka et al does not disclose any configuration that corresponds to the insulating layer. The examiner disagrees in that Hanaoka et al meets the claim limitation forming an insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60]) arranged at least a layer above the opening (opening of the via hole 50) in the second main surface (shown in annotated Fig 9) in the broadest reasonable interpretation. PNG media_image2.png 529 1414 media_image2.png Greyscale Additionally, regarding Claim 1 , Applicant argues that the combination of Hanaoka et al and Inoto et al does not disclose forming a solder layer in a layer above the rear-side electrode and the insulating layer since the solder layer is formed directly above 40 and the insulating layer 38 is not formed between the solder layer and the electrode path 40. The examiner disagrees in that Inoto et al discloses a solder layer (connection members 12 [0017] Fig 2) arranged on the rear-side electrode (pad 40 [0023]) and the insulating layer (insulating film 38 [0023]) and is considered meeting the claim limitation in the broadest reasonable interpretation as the claim language is written since it is only required to be on (above) the rear-side electrode and the insulating layer and is not required to be physically touching the insulating layer. PNG media_image3.png 742 926 media_image3.png Greyscale In the interest of compact prosecution, the examiner notes that further description of how the solder layer is prevented from entering the void as described in [0020] Fig 4 of the instant application would be helpful in overcoming the prior art of record. Further, the examiner also notes that further description of how the solder layer is arranged on the insulating layer L3 as shown in Fig 4 of the instant application would be helpful in overcoming the prior art of record. The examiner is available for an interview at Applicant’s convenience. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka et al (US 6852621) in view of Inoto et al (US 2019/0088612) . Regarding Claim 1, Hanaoka et al discloses a manufacturing method (method [column 1, lines 35-67]) of a semiconductor apparatus (semiconductor device [column 4, lines 50-55] Fig 9), comprising: forming an electrode (electrode 14 [column 6, lines 1-12]) on a first main surface (shown in annotated Fig 9) of a semiconductor substrate (semiconductor chip 10 [column 5, lines 10-25]) and insulation film 12 [column 5, lines 12-25]) made from a compound semiconductor (oxidized film of the silicon that is the basic material of the semiconductor chip [column 5, lines 10-25]); forming, at a location where the electrode (14) is formed, a via hole (through hole 50 [column 6, lines 1-12]) that penetrates the first main surface (shown in annotated Fig 9) and a second main surface (shown in annotated Fig 9) of the semiconductor substrate (10 and 12), wherein a ratio of a thickness of the semiconductor substrate (10 and 12) to a maximum value of a width of an opening (opening of the via hole 50) in the second main surface (shown in annotated Fig 9) is greater than 1 (although not drawn to scale, the examiner notes that the thickness of the semiconductor substrate (10) is significantly greater than the width of the via hole (50) and would meet this limitation); forming a rear-side electrode (electrical connection portion 72 and conductive layer 70 [column 10, lines 1-15]) on a second main surface (shown in annotated Fig 9) of the semiconductor substrate (10 and 12) in such a manner that the rear-side electrode (70 and 72) is electrically coupled to the electrode (14) in the via hole (50); forming an insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60]) arranged at least a layer above the opening (opening of the via hole 50) in the second main surface (shown in annotated Fig 9). PNG media_image2.png 529 1414 media_image2.png Greyscale Hanaoka et al does not disclose forming a solder layer in a layer above the rear-side electrode and the insulating layer. Inoto et al, in the related art of semiconductor devices that include integrated circuit devices and semiconductor chips, discloses a solder layer (connection members 12 [0017] Fig 2) arranged on the rear-side electrode (pad 40 [0023]) and the insulating layer (insulating film 38 [0023]); and a void (shown in annotated Fig 2) surrounded at least by the solder layer (12) and the insulating layer (38) in the via hole (shown in annotated Fig 2). PNG media_image3.png 742 926 media_image3.png Greyscale It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Hanaoka et al to include a solder layer as taught by Inoto et al in order to establish an electrical connection (bridge configuration [0025]) between two electrode/pads [0025] on the top portion of the device. Further, a person of ordinary skill in the art would have recognized that using solder as a material to facilitate electrical connections would be a simple substitution of one know element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate). Regarding Claim 4, the combination of Hanaoka et al and Inoto et al discloses the limitations of claim 1 as explained above. The combination of Hanaoka et al and Inoto et al further discloses wherein the forming the insulating layer (30 and 52 Fig 9 Hanaoka et al) includes: forming an insulating film (30 and 52 Hanaoka et al) on the rear-side electrode (70 and 72 Hanaoka et al), forming a resist pattern (patterned resist layer 54 [column 8, lines 20-25] Fig 6B Hanaoka et al) that covers a part of the insulating film (30 and 52 Hanaoka et al) formed in the via hole (50 Hanaoka et al) and in the vicinity of the opening (opening where via hole 50 is located, Hanaoka et al), removing the insulating film (30 and 52 Hanaoka et al) exposed from the resist pattern (54 Hanaoka et al) by etching (etching of 52 [column 8, lines 20-25] Hanaoka et al), and removing the resist pattern (54 Hanaoka et al) . 07-21-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka et al (US 6852621) in view of Inoto et al (US 2019/0088612), and in further view of Basker et al (US 2018/0076202) . Regarding Claim 2, the combination of Hanaoka et al and Inoto et al discloses the limitations of claim 1 as explained above. The combination of Hanaoka et al and Inoto et al further discloses wherein the forming the insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60] Fig 9 Hanaoka et al) includes: forming an insulating film (30 and 52 Fig 9 Hanaoka et al) on the rear-side electrode (70 and 72 Fig 9 Hanaoka et al). The combination of Hanaoka et al and Inoto et al does not directly disclose performing anisotropic etching on the insulating film in a thickness direction of the semiconductor substrate. Basker et al, in the related art of semiconductor devices that include semiconductor chips, discloses performing anisotropic etching (anisotropic etching [0024]) on the insulating film (conformal insulating layer [0024]) in a thickness direction (vertical direction [0024]) of the semiconductor substrate (silicon substrate 101). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Hanaoka and Inoto et al to include an anisotropic etching process on the insulating film in a thickness direction of the semiconductor substrate as taught by Basker et al in order to leave insulating material along the vertical sidewalls of structures [0024]. Further, a person of ordinary skill in the art would have recognized that using an anisotropic etching process on the insulating film would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate) . 07-21-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka et al (US 6852621) in view of Inoto et al (US 2019/0088612), and in further view of Yoo et al (US 2008/0081460) . Regarding Claim 3, the combination of Hanaoka et al and Inoto et al discloses the limitations of claim 1 as explained above. The combination of Hanaoka et al and Inoto et al further discloses wherein the forming the insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60] Fig 9 Hanaoka et al) includes: forming an insulating film (30 and 52 Fig 9 Hanaoka et al) on the rear-side electrode (70 and 72 Fig 9 Hanaoka et al). The combination of Hanaoka et al and Inoto et al does not directly disclose polishing the insulating film arranged on a layer above the second main surface of the semiconductor substrate. Yoo et al, in the related art of semiconductor devices that include semiconductor chips, discloses polishing the insulating film (insulating layer pattern 145 [0047] Fig 3) arranged on a layer (insulating interlayer 120 [0045]) above the second main surface (shown in annotated Fig 3) of the semiconductor substrate (substrate 100 [0038]). PNG media_image4.png 744 1257 media_image4.png Greyscale It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Hanaoka et al and Inoto et al to include forming the insulating layer by chemical mechanical polishing CMP as taught by Yoo et al in order to efficiently obtain a minimized thickness of the resulting/planarized insulating layer which may improve the quality and function of the device [0049]. Further, a person of ordinary skill in the art would have recognized that forming an insulating layer by chemical mechanical polishing CMP would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate) . Allowable Subject Matter Claims 5-6 are allowable. Regarding Claim 5, Hanaoka et al (US 6852621) discloses a semiconductor apparatus (semiconductor device [column 4, lines 50-55] Fig 9) further comprising: a semiconductor substrate (semiconductor chip 10 [column 5, lines10-25]) having a via hole (through hole 50 [column 6, lines 1-12]) penetrating a first main surface (shown in annotated Fig 9) and a second main surface (shown in annotated Fig 9); an electrode (electrode 14 [column 6, lines 1-12]) arranged above a via hole (50) on the first main surface (shown in annotated Fig 9) of the semiconductor substrate (10); a rear-side electrode (electrical connection portion 72 and conductive layer 70 [column 10, lines 1-15]) arranged on the second main surface (shown in annotated Fig 9) of the semiconductor substrate (10) and electrically coupled to the electrode (14) in the via hole (50); and an insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60]) arranged on the rear-side electrode (70 and 72) in at least part of the via hole (50), wherein a ratio of a thickness of the semiconductor substrate (10) to a maximum value of a width of an opening of the via hole (50) is greater than 1 (although not drawn to scale, the examiner notes that the thickness of the semiconductor substrate (10) is significantly greater than the width of the via hole (50) and would meet this limitation). PNG media_image5.png 669 1402 media_image5.png Greyscale The reason for the indication of allowability of Claim 5 is the inclusion of wherein the rear-side electrode is arranged between the semiconductor substrate and the Insulating layer. Specifically , the prior art of record discloses the insulating layer (30 and 52 Fig 9 Hanaoka et al) is arranged between the rear-side electrode (70 and 72 Fig 9 Hanaoka et al) and the substrate (10 and 12) and does not meet the claim limitation wherein the rear-side electrode is arranged between the semiconductor substrate and the Insulating layer. Further, should a new prior art be found that discloses this feature, it would not be obvious to a person of ordinary skill in the art to combine the references to meet the claim limitation. It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art. 13-03 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Related Cited Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Umemoto et al (US 2006/0024966) which discloses a semiconductor device with an insulating film formed on a surface of the via hole [0051], and Lin et al (US 2012/0133049) which discloses a semiconductor device with an insulating layer that uses an anisotropic etching process to form an opening via [0009] . Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.P.S./Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/469,601 Page 2 Art Unit: 2812 Application/Control Number: 18/469,601 Page 3 Art Unit: 2812 Application/Control Number: 18/469,601 Page 4 Art Unit: 2812 Application/Control Number: 18/469,601 Page 6 Art Unit: 2812 Application/Control Number: 18/469,601 Page 7 Art Unit: 2812 Application/Control Number: 18/469,601 Page 8 Art Unit: 2812 Application/Control Number: 18/469,601 Page 9 Art Unit: 2812 Application/Control Number: 18/469,601 Page 10 Art Unit: 2812 Application/Control Number: 18/469,601 Page 11 Art Unit: 2812
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