DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Apparatus with a Via Hole and a Rear-Side Electrode and Method of Manufacturing the Same.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 5 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hanaoka et al (US 6852621).
Regarding Claim 5, Hanaoka et al discloses a semiconductor apparatus (semiconductor device [column 4, lines 50-55] Fig 9) further comprising: a semiconductor substrate (semiconductor chip 10 [column 5, lines10-25]) having a via hole (through hole 50 [column 6, lines 1-12]) penetrating a first main surface (shown in annotated Fig 9) and a second main surface (shown in annotated Fig 9);
an electrode (electrode 14 [column 6, lines 1-12]) arranged above a via hole (50) on the first main surface (shown in annotated Fig 9) of the semiconductor substrate (10);
a rear-side electrode (electrical connection portion 72 and conductive layer 70 [column 10, lines 1-15]) arranged on the second main surface (shown in annotated Fig 9) of the semiconductor substrate (10) and electrically coupled to the electrode (14) in the via hole (50); and
an insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60]) arranged on the rear-side electrode (70 and 72) in at least part of the via hole (50),
wherein a ratio of a thickness of the semiconductor substrate (10) to a maximum value of a width of an opening of the via hole (50) is greater than 1 (although not drawn to scale, the examiner notes that the thickness of the semiconductor substrate (10) is significantly greater than the width of the via hole (50) and would meet this limitation).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka et al (US 6852621) in view of Inoto et al (US 2019/0088612).
Regarding Claim 1, Hanaoka et al discloses a manufacturing method (method [column 1, lines 35-67]) of a semiconductor apparatus (semiconductor device [column 4, lines 50-55] Fig 9), comprising:
forming an electrode (electrode 14 [column 6, lines 1-12]) on a first main surface (shown in annotated Fig 9) of a semiconductor substrate (semiconductor chip 10 [column 5, lines 10-25]) and insulation film 12 [column 5, lines 12-25]) made from a compound semiconductor (oxidized film of the silicon that is the basic material of the semiconductor chip [column 5, lines 10-25]);
forming, at a location where the electrode (14) is formed, a via hole (through hole 50 [column 6, lines 1-12]) that penetrates the first main surface (shown in annotated Fig 9) and a second main surface (shown in annotated Fig 9) of the semiconductor substrate (10 and 12),
wherein a ratio of a thickness of the semiconductor substrate (10 and 12) to a maximum value of a width of an opening (opening of the via hole 50) in the second main surface (shown in annotated Fig 9) is greater than 1 (although not drawn to scale, the examiner notes that the thickness of the semiconductor substrate (10) is significantly greater than the width of the via hole (50) and would meet this limitation);
forming a rear-side electrode (electrical connection portion 72 and conductive layer 70 [column 10, lines 1-15]) on a second main surface (shown in annotated Fig 9) of the semiconductor substrate (10 and 12) in such a manner that the rear-side electrode (70 and 72) is electrically coupled to the electrode (14) in the via hole (50);
forming an insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60]) arranged at least a layer above the opening (opening of the via hole 50).
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Hanaoka et al does not disclose
forming a solder layer in a layer above the rear-side electrode and the insulating layer.
Inoto et al, in the related art of semiconductor devices that include integrated circuit devices and semiconductor chips, discloses
a solder layer (connection members 12 [0017] Fig 2) arranged on the rear-side electrode (pad 40 [0023]) and the insulating layer (insulating film 38 [0023]); and
a void (shown in annotated Fig 2) surrounded at least by the solder layer (12) and the insulating layer (38) in the via hole (shown in annotated Fig 2).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Hanaoka et al to include a solder layer as taught by Inoto et al in order to establish an electrical connection (bridge configuration [0025]) between two electrode/pads [0025] on the top portion of the device. Further, a person of ordinary skill in the art would have recognized that using solder as a material to facilitate electrical connections would be a simple substitution of one know element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Regarding Claim 4, the combination of Hanaoka et al and Inoto et al discloses the limitations of claim 1 as explained above. The combination of Hanaoka et al and Inoto et al further discloses
wherein the forming the insulating layer (30 and 52 Fig 9 Hanaoka et al) includes: forming an insulating film (30 and 52 Hanaoka et al) on the rear-side electrode (70 and 72 Hanaoka et al), forming a resist pattern (patterned resist layer 54 [column 8, lines 20-25] Fig 6B Hanaoka et al) that covers a part of the insulating film (30 and 52 Hanaoka et al) formed in the via hole (50 Hanaoka et al) and in the vicinity of the opening (opening where via hole 50 is located, Hanaoka et al), removing the insulating film (30 and 52 Hanaoka et al) exposed from the resist pattern (54 Hanaoka et al) by etching (etching of 52 [column 8, lines 20-25] Hanaoka et al), and removing the resist pattern (54 Hanaoka et al).
Regarding Claim 6, Hanaoka et al discloses
further comprising: a solder layer arranged on the rear-side electrode and the insulating layer; and a void surrounded at least by the solder layer and the insulating layer in the via hole.
Inoto et al, in the related art of semiconductor devices that include integrated circuit devices and semiconductor chips, discloses
a solder layer (connection members 12 [0017] Fig 2) arranged on the rear-side electrode (pad 40 [0023]) and the insulating layer (insulating film 38 [0023]); and
a void (shown in annotated Fig 2) surrounded at least by the solder layer (12) and the insulating layer (38) in the via hole (shown in annotated Fig 2).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Hanaoka et al to include a solder layer as taught by Inoto et al in order to establish an electrical connection (bridge configuration [0025]) between two electrode/pads [0025] on the top portion of the device. Further, a person of ordinary skill in the art would have recognized that using solder as a material to facilitate electrical connections would be a simple substitution of one know element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka et al (US 6852621) in view of Inoto et al (US 2019/0088612), and in further view of Basker et al (US 2018/0076202).
Regarding Claim 2, the combination of Hanaoka et al and Inoto et al discloses the limitations of claim 1 as explained above. The combination of Hanaoka et al and Inoto et al further discloses
wherein the forming the insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60] Fig 9 Hanaoka et al) includes: forming an insulating film (30 and 52 Fig 9 Hanaoka et al) on the rear-side electrode (70 and 72 Fig 9 Hanaoka et al).
The combination of Hanaoka et al and Inoto et al does not directly disclose
performing anisotropic etching on the insulating film in a thickness direction of the semiconductor substrate.
Basker et al, in the related art of semiconductor devices that include semiconductor chips, discloses
performing anisotropic etching (anisotropic etching [0024]) on the insulating film (conformal insulating layer [0024]) in a thickness direction (vertical direction [0024]) of the semiconductor substrate (silicon substrate 101).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Hanaoka and Inoto et al to include an anisotropic etching process on the insulating film in a thickness direction of the semiconductor substrate as taught by Basker et al in order to leave insulating material along the vertical sidewalls of structures [0024]. Further, a person of ordinary skill in the art would have recognized that using an anisotropic etching process on the insulating film would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka et al (US 6852621) in view of Inoto et al (US 2019/0088612), and in further view of Yoo et al (US 2008/0081460).
Regarding Claim 3, the combination of Hanaoka et al and Inoto et al discloses the limitations of claim 1 as explained above. The combination of Hanaoka et al and Inoto et al further discloses
wherein the forming the insulating layer (insulation film 30 [column 6, lines 13-25] and 52 [column 7, lines 50-60] Fig 9 Hanaoka et al) includes: forming an insulating film (30 and 52 Fig 9 Hanaoka et al) on the rear-side electrode (70 and 72 Fig 9 Hanaoka et al).
The combination of Hanaoka et al and Inoto et al does not directly disclose
polishing the insulating film arranged on a layer above the second main surface of the semiconductor substrate.
Yoo et al, in the related art of semiconductor devices that include semiconductor chips, discloses
polishing the insulating film (insulating layer pattern 145 [0047] Fig 3) arranged on a layer (insulating interlayer 120 [0045]) above the second main surface (shown in annotated Fig 3) of the semiconductor substrate (substrate 100 [0038]).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Hanaoka et al and Inoto et al to include forming the insulating layer by chemical mechanical polishing CMP as taught by Yoo et al in order to efficiently obtain a minimized thickness of the resulting/planarized insulating layer which may improve the quality and function of the device [0049]. Further, a person of ordinary skill in the art would have recognized that forming an insulating layer by chemical mechanical polishing CMP would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Umemoto et al (US 2006/0024966) which discloses a semiconductor device with an insulating film formed on a surface of the via hole [0051], and Lin et al (US 2012/0133049) which discloses a semiconductor device with an insulating layer that uses an anisotropic etching process to form an opening via [0009].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812