DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-35 are pending.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
“means for determining” in claim 13,
“means for receiving” in claim 13,
“means for determining” in claim 13,
“means for performing” in claim 13.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-35 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 13, 14, and 25 recite “without changing a frequency of the synchronous core cluster and without changing a voltage of the synchronous core cluster”. Throttling in electronic systems is used to reduce temperature and/or power consumption and is done by reducing either a frequency or voltage in the device. It is unclear how a system can “throttle” and not reduce either frequency or voltage. For examination purposes, references cited will use NOPs to throttle the devices, as mentioned in the specification. As mentioned in the Advisory Action of 11/24/2025, inserting NOP’s into the operation of the cores effectively slows the cores’ operation thereby reducing the frequency of operation of the core, as US 11694940 recites “power can be immediately reduced by power gating, clock gating, reducing frequency by adjusting output of a clock source, clock stretching, inserting no-operations (NoOPs), etc.”, col. 33, lines, 21-24.
Claims 2-12, 15-18, 21-24, and 26-35 are also rejected as incorporating the deficiencies of the claims that they are dependent upon.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8, 13-16, 21, 25-27, and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Man et al. (US 20140068293)
Regarding claim 1, Kumar teaches
A processor device, comprising:
a synchronous core cluster comprising: (Fig. 2, [0062], “portable multicore systems provide a single CPU frequency plane across all cores of that system. In other words, cores executing in parallel execute at the same frequency.”)
a plurality of processor cores; (Fig. 2 (202A-202D))
a throttling selection circuit; and (Fig. 1, (CPU scheduler - 116))
a throttling circuit; (Fig. 1, (CPU management module – 114))
the throttling selection circuit configured to:
determine a performance state of a processor core of the plurality of processor cores; (Figs. 9 and 11, [0060], “Processes 900 sets the CPU core executing frequency ceiling based on the QoS of scheduled tasks, thermal level thresholds for the QoS class and thermal level of device at block 906. In one embodiment, each of the CPU core executes at a CPU frequency.” And [0062], “ In one embodiment, process 1100 is performed by a thermal daemon to manage CPU throttling … the higher threshold is a threshold that indicates that the device can have greater CPU throttling by reducing a CPU core frequency so as to mitigate the thermal load that is on the device”
receive, from the processor core, a Quality-of-Service (QoS) level associated with a workload scheduled for execution by the processor core; ([0040], “ the device assigns each thread or task a quality-of-service (QoS) class. The class can be explicitly advertised by the thread or task, or be implicitly inferred by the operating system. Inference is performed based on focality (foreground status) of the application in question, whether the application has been “app napped”, energy consumption history across the CPU, GPU, and input-output (IO) devices and other criteria.”)
determine a throttling level for the processor core based on the QoS level and the performance state; and ([0045], “By selectively throttling the lower QoS task CPU executions, the CPU execution for the higher QoS tasks are not throttled, but the overall CPU usage decreases, thus decreasing the power consumption of the storage system for the device 100, and decreasing the heat generated by the device, and reducing the thermal load on the device 100. If the thermal load on the device 100 continues to increase, thermald 110 can either further throttle the lower QoS tasks and/or start to throttle the higher QoS tasks.” And [0062-63], “At block 1104, process 1100 determines if the thermal level is greater than a higher threshold. In one embodiment, the higher threshold is a threshold that indicates that the device can have greater CPU throttling by reducing a CPU core frequency so as to mitigate the thermal load that is on the device. … process 1100 adjusts the selective forced idling for different task QoSes to increase the CPU throttling by reducing a CPU core frequency ceiling at block 1108. … At block 1104, process 1100 determines if the thermal level is greater than a higher threshold. In one embodiment, the higher threshold is a threshold that indicates that the device can have greater CPU throttling by reducing a CPU core frequency so as to mitigate the thermal load that is on the device.”)
provide the throttling level to the throttling circuit; and ([0062-63], “At block 1104, process 1100 determines if the thermal level is greater than a higher threshold. In one embodiment, the higher threshold is a threshold that indicates that the device can have greater CPU throttling by reducing a CPU core frequency so as to mitigate the thermal load that is on the device. … process 1100 adjusts the selective forced idling for different task QoSes to increase the CPU throttling by reducing a CPU core frequency ceiling at block 1108. … At block 1104, process 1100 determines if the thermal level is greater than a higher threshold. In one embodiment, the higher threshold is a threshold that indicates that the device can have greater CPU throttling by reducing a CPU core frequency so as to mitigate the thermal load that is on the device.”)
the throttling circuit configured to:
receive the throttling level; and perform microarchitectural throttling of the processor core based on the throttling level. (Figs. 3-4, and 10, [0048-49], “ In these embodiments, each of the low QoS tasks a selectively forced idle is scheduled to reduce the thermal load on the device. … a low QoS task can be selectively forced idle for part (or possibly all) of an execution window in order to mitigate a thermal load on a device. Alternatively, if the thermal load is high enough, a high QoS task can be selectively forced idled as well. A selectively force idle for a task idles the CPU processing core for a period of time during an execution window of a task. By idling the processing core, less power is consumed by the device and less heat is produced.” And [0061], “the selective forced idle time values either are derived from task QoS”)
Kumar teaches a forced idle but does not specifically teach not changing the frequency or voltage of the core cluster.
Man teaches
without changing a frequency of the synchronous core cluster and without changing a voltage of the synchronous core cluster. ([0022], “a signal can be sent to an internal throttling state machine 168 which may take corrective action within PCH 160 to cause a reduction in temperature. In an embodiment, this state machine may perform various thermal throttling activities to enable the temperature reduction. Throttling may be achieved by reducing activity within the PCH, e.g., by inserting null operations (nops) into a stream of instructions”)
Kumar and Man are analogous art. Man is cited to teach a similar concept of power management of processor/core clusters. Kumar teaches using the QOS level to determine the amount of throttling and forced idle sequences to control power/performance with core clusters. Man teaches determining reducing power consumption/temperature by inserting NOPs into the instruction stream, thereby not changing the clock speed or the voltage of the processor cores. Based on Garg, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kumar to use NOPs to lower the power consumption and temperature of the processor/cores. Furthermore, being able to use NOPs improves on Kumar by being able to lower the power consumption and temperature of the processor/cores. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “a processor having multiple independent domains can be controlled to prevent a temperature of any of the domains from exceeding a maximum junction temperature”, [0012] and thereby prevent damage to the system.
Regarding claim 2, Kumar teaches wherein the throttling selection circuit is configured to determine the throttling level and provide the throttling level to the throttling circuit at periodic intervals. (Figs. 7 and 11, teach repeatedly adjusting frequency (i.e. throttling levels))
Regarding claim 3, Kumar teaches
wherein: the throttling selection circuit is further configured to determine an energy performance preference (EPP) level corresponding to the QoS level; and
the throttling selection circuit is configured to determine the throttling level for the processor core based on the QoS level and the performance state by being configured to determine the throttling level for the processor core based on the EPP level and the performance state. (Fig. 12, (1204A-1204C), [0063-65], “In one embodiment, process 1100 throttles a QoS by decreasing the CPU processing frequency ceiling of that QoS. For example in one embodiment, process 1100 can throttle a QoS by decreasing a CPU processing frequency ceiling from 100% to 90% as described in FIG. 12 below. … Three different CPU throttling conditions are illustrated in FIG. 12. In one embodiment, for the no CPU throttling condition 1204A, there is no reduction in the percent CPU percent frequency ceiling. In this embodiment, this means that each of the tasks is executed normally during the execution window. This condition represents a device with little or no thermal load. In this embodiment, each of the tasks will be scheduled for CPU execution and processed normally with no CPU throttling on the CPU processing core frequency. As the thermal load for the device increases, the device starts to throttle the lower QoS tasks. In one embodiment, this is illustrated the column 1204B where there is some CPU throttling for the lower QoS tasks. For example in one embodiment, QoS 0 and 1 execute normally with no reduction of the CPU processing core frequency. QoS 2 and N will have the CPU processing core frequency ceiling reduced to 90% and 75%, respectively.”, where the energy performance preference is set by the frequency ceiling determinations based on the QoS and the level of CPU throttling)
Regarding claim 8, Man teaches wherein the throttling circuit is configured to perform the microarchitectural throttling of the processor core by being configured to insert no-operation (NOP) instructions for execution by the processor core. ([0022], “a signal can be sent to an internal throttling state machine 168 which may take corrective action within PCH 160 to cause a reduction in temperature. In an embodiment, this state machine may perform various thermal throttling activities to enable the temperature reduction. Throttling may be achieved by reducing activity within the PCH, e.g., by inserting null operations (nops) into a stream of instructions”)
Regarding claim 12, Kumar teaches integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter. ([0042], “In one embodiment, the device 100 can be a personal computer, laptop, server, mobile device (e.g., smartphone, laptop, personal digital assistant, music playing device, gaming device, etc.), network element (e.g., router, switch, gateway, etc.), and/or any device capable of executing multiple applications”)
As to claims 13-14 and 25, Kumar teaches these claims according to the reasoning provided in claim 1.
As to claims 15 and 26, Kumar teaches these claims according to the reasoning provided in claim 2.
As to claims 16 and 27, Kumar teaches these claims according to the reasoning provided in claim 3.
As to claims 21 and 32, Kumar and Shah teaches these claims according to the reasoning provided in claim 8.
Claim(s) 4-5, 9, 17-18, 22, 28-29, and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar and Man further in view of Garg et al. (US 20220100247).
Regarding claim 4, Kumar teaches the relation QOS and EPP levels to performance settings but does not specifically teach a mapping register to store the information
Garg teaches wherein: the throttling selection circuit comprises a mapping register that maps the QoS level to the EPP level; and the throttling selection circuit is configured to determine the EPP level based on the mapping register. ([0315], “enabled operating system and/or virtual machine monitor will maintain an association of processing threads to a CLOS. Typically, when a software thread is swapped onto a given logical processor, a model specific register (MSR) such as IA32_PQR_ASSOC MSR (for an Intel Corporation Xeon® processor, for example) is updated to reflect the CLOS of the thread. MBA bandwidth limits per-CLOS are specified as a value in the range of zero to a maximum supported level of throttling for the platform (available via CPUID), typically up to 90% throttling, and typically in 10% steps. These steps are approximate, and represent a calibrated value mapped to a known bandwidth-intense series of applications to provide bandwidth control. The resulting bandwidth for these calibration points provided may vary across system configurations, generations and memory configurations, so the MBA throttling delay values should be regarded as a hint from software to hardware about how much throttling should be applied.” And [0582], “pCode may set frequencies and appropriate voltages for the processor. Part of the pCode are accessible via OS 5552. In various embodiments, mechanisms and methods are provided that dynamically change an Energy Performance Preference (EPP) value based on workloads, user behavior, and/or system conditions. There may be a well-defined interface between OS 5552 and the pCode. The interface may allow or facilitate the software configuration of several parameters and/or may provide hints to the pCode.”)
Kumar, Man, and Garg are analogous art. Garg is cited to teach a similar concept of power management of processor/core clusters. Kumar teaches using the QOS level to determine the amount of throttling and forced idle sequences to control power/performance with core clusters. Garg teaches determining an energy performance preference to provide hints to the operating levels of the processor/cores and clusters. Garg, additionally, teaches that the information to map these settings may be stored in registers for use in the determining. Based on Garg, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kumar and Man to use registers to map information to determine the optimal power/performance settings of the processors/cores/clusters. Furthermore, being able to mapping registers to determine the operating points (pCodes) of the processors/cores/clusters improves on Kumar and Man by being able to improve overall performance and control power usage. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “pCode improves the performance of the SoC in battery mode. In some embodiments, pCode allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. In some embodiments, pCode implements power throttling and is part of Intel's Dynamic Tuning Technology (DTT).”, [0584]
Regarding claim 5, Kumar does not teach but Garg teaches wherein the throttling selection circuit is configured to determine the EPP level by being configured to map the QoS level to the EPP level based on the performance state of the processor core. ([0582-583], “ In various embodiments, mechanisms and methods are provided that dynamically change an Energy Performance Preference (EPP) value based on workloads, user behavior, and/or system conditions. There may be a well-defined interface between OS 5552 and the pCode. The interface may allow or facilitate the software configuration of several parameters and/or may provide hints to the pCode. As an example, an EPP parameter may inform a pCode algorithm as to whether performance or battery life is more important. … This support may be done as well by the OS 5552 by including machine-learning support as part of OS 5552 and either tuning the EPP value that the OS hints to the hardware (e.g., various components of SCO 5501) by machine-learning prediction, or by delivering the machine-learning prediction to the pCode in a manner similar to that done by a Dynamic Tuning Technology (DTT) driver” And [0391], “ In one such embodiment, a given CLOS group k corresponds to one or more performance parameters according to which any given core i of that CLOS group k is to operate. By way of illustration and not limitation, such one or more one or more performance parameters include a minimum frequency f.sub.min,k, and a maximum frequency f.sub.max,k. Such a CLOS group k is also assigned a value—e.g., such as a weight w.sub.k—indicating how that CLOS group k is to be prioritized, ordered or otherwise ranked relative to one or more others of the CLOS groups.” And [0487], “one or more such pCode algorithms adjust a processor workload to prevent violation of a corresponding TDP and/or other performance limitation.” Where CLOS groups represent QOS levels)
Kumar, Man, and Garg are analogous art. Garg is cited to teach a similar concept of power management of processor/core clusters. Kumar teaches using the QOS level to determine the amount of throttling, forced idle sequences and frequency ceilings to control power/performance with core clusters. Garg teaches determining an energy performance preference to provide hints to the operating levels of the processor/cores and clusters. Garg, additionally, sets the voltage and frequency operating points for the cluster using EPP hints. Based on Garg, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kumar and Man to EPP hints to determine the optimal power/performance settings of the clusters. Furthermore, being able to mapping registers to determine the operating points (pCodes) of the processors/cores/clusters improves on Kumar and Man by being able to improve overall performance and control power usage. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “pCode improves the performance of the SoC in battery mode. In some embodiments, pCode allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. In some embodiments, pCode implements power throttling and is part of Intel's Dynamic Tuning Technology (DTT).”, [0584]
Regarding claim 7, Kumar teaches using lookup tables for a throttling level but does not specifically teach using an average frequency related to the EPP level used to set an the performance state.
Garg teaches
using an average frequency related to the EPP level used to set an the performance state wherein the throttling selection circuit is further configured to populate each throttling level LUT of the plurality of throttling level LUTs by being configured to: for each EPP level of the plurality of EPP levels: calculate an average core frequency corresponding to the EPP level; and for each throttling level of the plurality of throttling levels, calculate a corresponding performance state for the processor core that requires the throttling level to achieve at least the average core frequency. ([0583], “This support may be done as well by the OS 5552 by including machine-learning support as part of OS 5552 and either tuning the EPP value that the OS hints to the hardware (e.g., various components of SCO 5501) by machine-learning prediction, or by delivering the machine-learning prediction to the pCode in a manner similar to that done by a Dynamic Tuning Technology (DTT) driver. In this model, OS 5552 may have visibility to the same set of telemetries as are available to a DTT. As a result of a DTT machine-learning hint setting, pCode may tune its internal algorithms to achieve optimal power and performance results following the machine-learning prediction of activation type. The pCode as example may increase the responsibility for the processor utilization change to enable fast response for user activity, or may increase the bias for energy saving either by reducing the responsibility for the processor utilization or by saving more power and increasing the performance lost by tuning the energy saving optimization.”, and [0388], “closed loop controller 4014—such as a PID controller—outputs another signal 4016 which (for example) indicates a per-core average frequency budget—e.g., wherein signal 4016 identifies a p-state which corresponds to said frequency budget. In various embodiments, closed loop controller 4014 is implemented as firmware (e.g., pCode)”)
Kumar, Man, and Garg are analogous art. Garg is cited to teach a similar concept of power management of processor/core clusters. Kumar teaches using the QOS level to determine the amount of throttling, forced idle sequences and frequency ceilings to control power/performance with core clusters. Garg teaches determining an energy performance preference to provide hints to the operating levels of the processor/cores and clusters. Garg, additionally, sets the voltage and frequency operating points for the cluster using EPP hints. Based on Garg, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kumar and Man to EPP hints to determine the optimal power/performance settings of the clusters. Furthermore, being able to mapping registers to determine the operating points (pCodes) of the processors/cores/clusters improves on Kumar and Man by being able to improve overall performance and control power usage. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “pCode improves the performance of the SoC in battery mode. In some embodiments, pCode allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. In some embodiments, pCode implements power throttling and is part of Intel's Dynamic Tuning Technology (DTT).”, [0584]
Regarding claim 9, Kumar and Man do not teach but Garg teaches wherein the synchronous core cluster further comprises:
a dynamic voltage and frequency scaling (DVFS) aggregator circuit; and ([0094], “each instance of p-unit is capable of autonomously managing local dedicated resources and contains structures to aggregate data and communicate between instances to enable shared resource management by the instance configured as the shared resource supervisor.”)
a DVFS circuit; ([0217], “hierarchical fabric management allows for DVFS to maximize the SoC performance within a power budget. The voltage and frequency settings dynamically change due to the change in workload behavior at runtime.”)
the DVFS aggregator circuit configured to:
receive, from the plurality of processor cores, a corresponding plurality of EPP hints; ([0582], “In various embodiments, mechanisms and methods are provided that dynamically change an Energy Performance Preference (EPP) value based on workloads, user behavior, and/or system conditions. There may be a well-defined interface between OS 5552 and the pCode. The interface may allow or facilitate the software configuration of several parameters and/or may provide hints to the pCode. As an example, an EPP parameter may inform a pCode algorithm as to whether performance or battery life is more important.”)
select a cluster performance state for the synchronous core cluster based on the plurality of EPP hints; and transmit, to the DVFS circuit, the cluster performance state; and ([0583-584], “As a result of a DTT machine-learning hint setting, pCode may tune its internal algorithms to achieve optimal power and performance results following the machine-learning prediction of activation type. The pCode as example may increase the responsibility for the processor utilization change to enable fast response for user activity, or may increase the bias for energy saving either by reducing the responsibility for the processor utilization or by saving more power and increasing the performance lost by tuning the energy saving optimization. … pCode improves the performance of the SoC in battery mode. In some embodiments, pCode allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. In some embodiments, pCode implements power throttling and is part of Intel's Dynamic Tuning Technology (DTT). In various embodiments, the peak power limit is referred to PL4.”)
the DVFS circuit configured to:
receive the cluster performance state from the DVFS aggregator circuit; and set a frequency and a voltage for the synchronous core cluster based on the cluster performance state. ([0584], “In some embodiments, pCode provides a scheme to dynamically calculate the throttling level (P.sub.soc,th) based on the available battery power (which changes slowly) and set the SoC throttling peak power (P.sub.soc,th). In some embodiments, pCode decides the frequencies and voltages based on P.sub.soc,th.”)
Kumar, Man, and Garg are analogous art. Garg is cited to teach a similar concept of power management of processor/core clusters. Kumar teaches using the QOS level to determine the amount of throttling, forced idle sequences and frequency ceilings to control power/performance with core clusters. Garg teaches determining an energy performance preference to provide hints to the operating levels of the processor/cores and clusters. Garg, additionally, sets the voltage and frequency operating points for the cluster using EPP hints. Based on Garg, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kumar and Man to EPP hints to determine the optimal power/performance settings of the clusters. Furthermore, being able to mapping registers to determine the operating points (pCodes) of the processors/cores/clusters improves on Kumar and Man by being able to improve overall performance and control power usage. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “pCode improves the performance of the SoC in battery mode. In some embodiments, pCode allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. In some embodiments, pCode implements power throttling and is part of Intel's Dynamic Tuning Technology (DTT).”, [0584]
As to claims 17 and 28, Kumar, Man, and Garg teach these claims according to the reasoning provided in claim 4.
As to claims 18 and 29, Kumar, Man, and Garg teach these claims according to the reasoning provided in claim 5.
As to claims 22 and 33, Kumar, Man, and Garg teach these claims according to the reasoning provided in claim 9.
Claim(s) 10-11, 23-24, and 34-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar, Man, and Garg further in view of Rotem et al. (US 20210018971)
Regarding claim 10, Kumar, Man, and Garg teach controlling power/performance in a processor system by setting operating levels but do not teach using look-up tables to aid in setting the levels.
Rotem teaches wherein: the synchronous core cluster further comprises a plurality of mapping look-up tables (LUTs) corresponding to the plurality of processor cores; each mapping LUT of the plurality of mapping LUTs maps an EPP hint of the plurality of EPP hints to a corresponding performance state; and the DVFS aggregator circuit selects the cluster performance state based on the plurality of mapping LUTs. ([0035], “ An operating point may be selected to prioritize power efficiency or performance depending on a value of the EPP parameter. Frequency selection may be software controlled by writing to one or more CPU registers.” [0057], “The microcontroller 432 outputs results of its workload analysis to the work point registers 454 such that a predetermined set of operating frequencies and corresponding voltage settings are selectable by the work point arbiter depending on the local performance limit 460. Thus, the local power control arbiter 430 may transition the processing unit 410 between a plurality of different states, each state having a different operating frequency and operating voltage, using the state machine 458 and depending on selection of operating parameters based on local algorithmic analysis by the Lcode executing on the microcontroller 432n the work point register 454. A lookup table of frequencies and voltages may be used by the Lcode to make an operating point selection. The work point arbiter 456 prevents selection of an operating frequency inconsistent with the local performance limit 460 set by the global power controller 420. The microcontroller 432 may in some embodiments adjust and/or control throttling intervals related to compliance with one or more power limits for the processing unit 410.”)
Kumar, Man, Garg, and Rotem are analogous art. Rotem is cited to teach a similar concept of power management of processor/core clusters. Kumar teaches using the QOS level to determine the amount of throttling and forced idle sequences to control power/performance with core clusters. Garg teaches determining an energy performance preference to provide hints to the operating levels of the processor/cores and clusters. Rotem teaches using lookup tables to set the voltage and frequency operating points for the cluster using EPP hints. Based on Rotem, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kumar, Man, and Garg to use lookup tables with EPP hints to determine the optimal power/performance settings of the clusters. Furthermore, being able use lookup tables with EPP hints improves on Kumar, Man, and Garg by being able to improve overall performance and control power usage. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to “thus improves overall efficiency and effectiveness of power management.”, [0053]
Regarding claim 11, Kumar, Man, and Garg teach controlling power/performance in a processor system by setting operating levels but do not teach using look-up tables to aid in setting the levels.
Rotem teaches wherein the DVFS aggregator circuit is configured to select the cluster performance state based on the plurality of mapping LUTs by ([0057], “A lookup table of frequencies and voltages may be used by the Lcode to make an operating point selection.”
Garg teaches being configured to select a highest performance state indicated by the plurality of mapping LUTs. ([0393], “balancer 4026 supports an Ordered With Priority (OP) frequency allocation scheme wherein, for each core of a highest priority CLOS group, each core of that CLOS group is assigned a highest possible frequency (up to the respective maximum frequencies which that core can support).”)
Kumar, Man, Garg, and Rotem are analogous art. Rotem is cited to teach a similar concept of power management of processor/core clusters. Kumar teaches using the QOS level to determine the amount of throttling and forced idle sequences to control power/performance with core clusters. Garg teaches determining an energy performance preference to provide hints to the operating levels of the processor/cores and clusters. Rotem teaches using lookup tables to set the voltage and frequency operating points for the cluster using EPP hints. Based on Rotem, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kumar, Man, and Garg to use lookup tables with EPP hints to determine the optimal power/performance settings of the clusters. Furthermore, being able use lookup tables with EPP hints improves on Kumar, Man, and Garg by being able to improve overall performance and control power usage. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to “thus improves overall efficiency and effectiveness of power management.”, [0053]
As to claims 23 and 34, Kumar, Man, Garg, and Rotem teach these claims according to the reasoning provided in claim 10.
As to claims 24 and 35, Kumar, Man, Garg, and Rotem teach these claims according to the reasoning provided in claim 11.
Allowable Subject Matter
Claims 6-7, 19-20, and 30-31 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 13-14, and 25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see pgs. 16-17, filed 12/17/2025, with respect to claims 6, 19, and 30 have been fully considered and are persuasive. The rejection of claims 6, 19,and 30 has been withdrawn.
Conclusion
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/CHERI L HARRINGTON/Examiner, Art Unit 2176 December 30, 2025
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176