Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group I identified as claims 1-10 with traverse in the reply filed on 1/10/2026 is acknowledged.
REMARKS
1. On pages 7-8 of the remark Applicant argues restriction is not proper and further argues that search and examination of the original claims of the application would not place a serious burden on the office.
In response:
The examiner respectfully disagrees. Search and examination of the original claims of the application would place a serious burden on the office because of the following reasons.
Claims 1 10 are directed to a communication device including a component that counts a number based on the MDI signal and compare the counted number with threshold and if the counted number is greater than the threshold, the component outputs a wakeup signal as described in Applicant’s own Figure 3, [0041] in the pre-grant publication. Claims 11-16 are directed to a communication device including a component that provide a wakeup signal based on MDI signal as described in Applicant’s own Figure 4, [0042] in the pre-grant publication. Applicant is claiming two different devices wherein the function of the component of the devices are different. In the first device the component of the device provides wake up signal based on the threshold value wherein in the second device the component of the device provides wake up signal based on MDI signal. Claims 17-20 are directed to a method wherein a power downed crystal oscillator is powered up from power downed so that it can provide clock for operation of the communication device which are different from the claims 1-10 and 11-16.
For the above reasons, examiner thinks restriction of claims 1-20 were proper.
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No US 2012/0314738 to Kashima et al. (hereinafter Kashima) in view of CN 1236531 to Khullar et al. (hereinafter Khullar)
As to claim 1, Kashima discloses a communication device, comprising:
a crystal oscillator, providing a clock for operation of the communication device in a second mode (Kashima; [0077]; [0109] discloses the oscillator 12 is designed using a quartz crystal oscillator, and therefore is capable of generating these clock signals with stable frequencies. The signal processor 10 is configured to operate in either the wakeup mode or sleep mode, and supply, to the transceiver 20, a mode signal MD indicative of the present operation mode of the corresponding node);
an auxiliary circuit, comprising:
an accumulator, counting a number according to an MDI (Medium Dependent Interface) signal (Kashima; [0109]; [0081] discloses the timing generator 21 is configured to activate the oscillator 21a to generate the counting clock CCK in accordance with instructions supplied from the mode controller 25 if the operation mode of the corresponding node (master 3a) is the wakeup mode, and disable the timing generator 21 if the mode signal MD represents the sleep mode. The simple oscillator 21a is configured to generate a counting clock CCK. The timing generator 21 is configured to divide the counting clock CCK to generate various timing signals each synchronized with the internal clock CK supplied from the signal processor 10); and
a control circuit, switching from the second mode to a first mode in response to a control signal, and switching from the first mode to the second mode in response to the wakeup signal (Kashima; [0087]; The mode controller 25 is configured to output a control signal to each of the timing generator 21 and the encoder/decoder 22 to enable each of the timing generator 21 and the encoder/decoder 22 if the mode signal MD represents the wakeup mode, and to disable the timing generator 21 from generating the timing signals if the mode signal MD represents the sleep mode [0077]; the oscillator 12 is designed using a quartz crystal oscillator, and therefore is capable of generating these clock signals with stable frequencies. The signal processor 10 is configured to operate in either the wakeup mode or sleep mode, and supply, to the transceiver 20, a mode signal MD indicative of the present operation mode of the corresponding node [0109] discloses the timing generator 21 is configured to activate the oscillator 21a to generate the counting clock CCK in accordance with instructions supplied from the mode controller 25 if the operation mode of the corresponding node (master 3a) is the wakeup mode, and disable the timing generator 21 if the mode signal MD represents the sleep mode);
wherein in the first mode, the control circuit disables the crystal oscillator and enables the auxiliary circuit (Kashima; [0087]; The mode controller 25 is configured to output a control signal to each of the timing generator 21 and the encoder/decoder 22 to enable each of the timing generator 21 and the encoder/decoder 22 if the mode signal MD represents the wakeup mode, and to disable the timing generator 21 from generating the timing signals if the mode signal MD represents the sleep mode [0077]; the oscillator 12 is designed using a quartz crystal oscillator, and therefore is capable of generating these clock signals with stable frequencies. The signal processor 10 is configured to operate in either the wakeup mode or sleep mode, and supply, to the transceiver 20, a mode signal MD indicative of the present operation mode of the corresponding node [0109] discloses the timing generator 21 is configured to activate the oscillator 21a to generate the counting clock CCK in accordance with instructions supplied from the mode controller 25 if the operation mode of the corresponding node (master 3a) is the wakeup mode, and disable the timing generator 21 if the mode signal MD represents the sleep mode);
wherein in the second mode, the control circuit enables the crystal oscillator (Kashima; [0087]; The mode controller 25 is configured to output a control signal to each of the timing generator 21 and the encoder/decoder 22 to enable each of the timing generator 21 and the encoder/decoder 22 if the mode signal MD represents the wakeup mode, and to disable the timing generator 21 from generating the timing signals if the mode signal MD represents the sleep mode [0077]; the oscillator 12 is designed using a quartz crystal oscillator, and therefore is capable of generating these clock signals with stable frequencies. The signal processor 10 is configured to operate in either the wakeup mode or sleep mode, and supply, to the transceiver 20, a mode signal MD indicative of the present operation mode of the corresponding node [0109] discloses the timing generator 21 is configured to activate the oscillator 21a to generate the counting clock CCK in accordance with instructions supplied from the mode controller 25 if the operation mode of the corresponding node (master 3a) is the wakeup mode, and disable the timing generator 21 if the mode signal MD represents the sleep mode)
Kashima discloses of counting a number of clock signal, but fails to disclose a comparator, comparing the number with a threshold, wherein if the number is greater than or equal to the threshold, the comparator outputs a wakeup signal. However, Khullar discloses
a comparator, comparing the number with a threshold, wherein if the number is greater than or equal to the threshold, the comparator outputs a wakeup signal (Khullar; Page 3, last paragraph; Page 4, first paragraph; Page7; Claim 1 discloses terminal unit operating in an idle mode to alternately wake-up and to enter a sleep mode, the remote unit comprising: a processing unit for controlling said remote unit, generating the input to the processing units of the system timing signal of the clock signal generating system, the clock signal generating system comprising: generating a first clock pulse of the first clock pulse generating unit, calculating the first clock pulse, and when the count value of the first clock pulse exceeds a first predetermined threshold to output the first counter of one of the system timing signal; generating a second clock pulse of the second clock pulse generating unit, counting the second clock pulse, and when the count value of the second clock pulses exceeds a second predetermined threshold outputs a second counter of one of the system timing signal, a device the output timing signal of the system to the processing unit from the first counter for receiving said system timing signals from the first and second counters, and when the processing unit awakens and outputting system timing signals from said second counter when said processing unit is in a sleep mode)
It is obvious for a person of ordinary skilled in the art to combine the teachings before the effective filing date of the invention. One would be motivated to combine the teachings in order to wake a device from the sleep mode and rhus use the limited resources in an effective way.
As to claim 3, the rejection of claim 1 as listed above is incorporated herein. In addition, Kashima-Khullar discloses wherein in response to the wakeup signal with a high logic level, the control circuit leaves the first mode and enters the second mode (Kashima; [0087]; The mode controller 25 is configured to output a control signal to each of the timing generator 21 and the encoder/decoder 22 to enable each of the timing generator 21 and the encoder/decoder 22 if the mode signal MD represents the wakeup mode, and to disable the timing generator 21 from generating the timing signals if the mode signal MD represents the sleep mode)
As to claim 4, the rejection of claim 1 as listed above is incorporated herein. In addition, Kashima-Khullar discloses wherein in the second mode, the control circuit disables the auxiliary circuit (Kashima; [0087]; The mode controller 25 is configured to output a control signal to each of the timing generator 21 and the encoder/decoder 22 to enable each of the timing generator 21 and the encoder/decoder 22 if the mode signal MD represents the wakeup mode, and to disable the timing generator 21 from generating the timing signals if the mode signal MD represents the sleep mode)
As to claim 7, the rejection of claim 1 as listed above is incorporated herein. In addition, Kashima-Khullar discloses wherein the MDI signal is an NLP (Normal Link Pulse) signal or an NRZ (Non-Return-to-Zero) signal (Kashima; [0074]; The transceiver 20 is connected with the communication bus 5, and configured to: encode transmission data TXD based on an NRZ (Non-Return to Zero) code, which is supplied from the signal processor 10 with being asynchronous to the internal clock CK of the transceiver 20, into transmission data TX based on PWM code; and output the transmission data TX to the communication bus 5. Here Kashima is applied for the 2nd alternative)
As to claim 9, the rejection of claim 1 as listed above is incorporated herein. In addition, Kashima-Khullar discloses wherein the threshold is adjustable (Kashima; [0086]; the receive buffer 24 is designed as a common comparator, and configured to output the high signal level if the level on the communication bus 5 is higher than a preset threshold level, and the low signal level if the level on the communication bus 5 is lower than the preset threshold level)
Allowable Subject Matter
Claims 2, 5, 6, 8 and 10 are objected, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
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/FAISAL CHOUDHURY/Primary Examiner, Art Unit 2478