Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The following NON-FINAL Office Action is in response to application 18/469,974
filed on 09/19/2023. This communication is the first action on the merits.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/16/2023 has been considered by the examiner.
Drawings
The drawings were received on 09/19/2023. These drawings are acceptable.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more. A subject matter eligibility analysis is set forth below. See MPEP 2106.
Specifically, representative Claim 1 recites:
A signal processing circuit, comprising: an input interface and an
analysis circuit,
wherein the input interface is configured to receive a measurement signal and a reference signal, wherein the input interface is configured to forward the measurement signal and the reference signal to the analysis circuit,
wherein the measurement signal and the reference signal comprise a symbol sequence, respectively,
wherein the analysis circuit is configured to:
synchronize the measurement signal with the reference signal;
determine error vectors based on the synchronized measurement signal and reference signal;
determine symbol points of the symbol sequence and decision boundaries for the symbol points; and
determine whether the determined error vectors exceed the decision boundaries determined.
The claim limitations in the abstract idea have been highlighted in bold above; the remaining limitations are “additional elements.”
Similar limitations comprise the abstract idea of Method Claim 12.
Under Step 1 of the analysis, claim 1 belongs to a statutory category, namely it is a system claim. Likewise, claim 12 is a method claim.
Under Step 2A, prong 1: This part of the eligibility analysis evaluates whether the claim recites a judicial exception. As explained in MPEP 2106.04, subsection II, a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim.
In the instant case, claim 1 is found to recite at least one judicial exception (i.e. abstract idea), that being a Mental Process and a Mathematical Concept. This can be seen in the claim limitations of “the measurement signal and the reference signal comprise a symbol sequence”, “synchronize the measurement signal with the reference signal”, “determine error vectors based on the synchronized measurement signal and reference signal”, “determine symbol points of the symbol sequence and decision boundaries for the symbol points”, and “determine whether the determined error vectors exceed the decision boundaries determined” which is the judicial exception of a mental process because these limitations are merely data observations, evaluations, and/or judgements in order to process and evaluate the information contained in the measurement and reference signals for example by determining symbol sequences, synchronizing the signals, calculating error vectors, identifying symbol points, and comparing those values to decision boundaries. These operations amount to data analysis and mathematical evaluation and is capable of being performed mentally and/or with the aid of pen and paper. Additionally, the aforementioned limitations recite mathematical calculations, e.g. see Spec. [0080]-[0085] as the specification explains that determine decision boundaries, evaluating error vectors, and computing a symbol error rate involve mathematical relationships and computations applied to the measurement and reference signals.
Similar limitations comprise the abstract ideas of Claim 12.
Step 2A, prong 2 of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception(s) into a practical application of the exception. This evaluation is performed by (a) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (b) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application.
In addition to the abstract ideas recited in claim 1, the claimed system recites
additional elements including “A signal processing circuit, comprising: an input interface and an analysis circuit”, “wherein the input interface is configured to receive a measurement signal and a reference signal, wherein the input interface is configured to forward the measurement signal and the reference signal to the analysis circuit” however these elements are found to be data gathering and output steps, which are recited at a high level of generality, and thus merely amount to “insignificant extra-solution” activity(ies). See MPEP 2106.05(g) “Insignificant Extra-Solution Activity,”. Furthermore, the claim recites that the steps, e.g., “determining”, and “synchronizing” are performed by the analysis circuit or processing components and however this is found to be equivalent to adding the words “apply it” and mere instructions to apply a judicial exception on a general purpose computer does not integrate the abstract idea into a practical application. See MPEP 2106.05(f).
The generic data gathering, processing, and output steps, are recited at such a high level of generality (e.g. using generic ”circuit” and “interface”) that it represents no more than mere instructions to apply the judicial exceptions on a computer. It can also be viewed as nothing more than an attempt to generally link the use of the judicial exceptions to the technological environment of a computer. Noting MPEP 2106.04(d)(I): “It is notable that mere physicality or tangibility of an additional element or elements is not a relevant consideration in Step 2A Prong Two. As the Supreme Court explained in Alice Corp., mere physical or tangible implementation of an exception does not guarantee eligibility. Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573 U.S. 208, 224, 110 USPQ2d 1976, 1983-84 (2014) ("The fact that a computer ‘necessarily exist[s] in the physical, rather than purely conceptual, realm,’ is beside the point")”.
Thus, under Step 2A, prong 2 of the analysis, even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception. No specific practical application is associated with the claimed system. For instance, nothing is done with the result of determining symbol points, decision boundaries, and error vectors beyond using these values for data analysis, which merely reflects the abstract calculations themselves rather than any practical application or technological improvement.
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, as described above with respect to Step 2A Prong 2, merely amount to a general purpose computer system that attempts to apply the abstract idea in a technological environment, limiting the abstract idea to a particular field of use, and/or merely performs insignificant extra-solution activit(ies) (claims 1 and 12). Such insignificant extra-solution activity, e.g. data gathering and output, when re-evaluated under Step 2B is further found to be well-understood, routine, and conventional as evidenced by MPEP 2106.05(d)(II) (describing conventional activities that include transmitting and receiving data over a network, electronic recordkeeping, storing and retrieving information from memory, and electronically scanning or extracting data from a physical document).
Therefore, similarly the combination and arrangement of the above identified additional elements when analyzed under Step 2B also fails to necessitate a conclusion that claim 1, as well as claim 12, amount to significantly more than the abstract idea.
With regards to the dependent claims, claims 2-11 and 13-20, merely further expand upon the algorithm/abstract idea and do not set forth further additional elements that integrate the recited abstract idea into a practical application or amount to significantly more. Therefore, these claims are found ineligible for the reasons described for claims 1 and 11. Specifically:
With respect to dependent claims 2,3,13 and 14, specifically, the claims further recite determining the number of error vectors and determining a symbol error rate (SER) based on those error vectors. These limitations merely perform additional mathematical calculations and evaluations on the already received data. Such steps are directed to mathematical relationships and numerical analysis, which fall within the judicial exception of a mathematical concept. These limitations do not improve the functioning of the signal processing circuit nor do they effect any transformation of a physical article. Instead, they constitute insignificant extra solution activity and mere post processing of data which does not amount to significantly more. See MPEP 2106.05(g)(f).
With respect to dependent claims 4, 5, 15, and 16 specifically, the claims further recite determining a modulation scheme and determining decision boundaries based on the modulation scheme. These limitations merely specify parameters or conditions used during the abstract calculations and do not modify the underlying operation of the circuity. Such recitations represent field of use limitations or refinement of the abstract idea itself, which do not integrate the exception into a practical application. See MPEP 2106.05(h)(g).
With respect to dependent claims 6, 7, 17, and 18 specifically, the claims recite transforming the decision boundaries to an origin of a constellation plane and specifying that the plane is an IQ plane. These limitations merely recite mathematical normalization which are abstract data processing steps. They do not provide an improvement to a technological process nor do they impose meaningful limits on the judicial exception. Instead, these recitations merely manipulate the data within the abstract mental process and constitute insignificant extra-solution activity. See MPEP 2106.05(g).
With respect to dependent claims 8, 9, 10, 11, 19, and 20, specifically, the claims recite the type of the measurement signal and further recite that the signal processing circuit may be included within a measurement instrument. These limitations merely specify the environment in which the abstract idea is performed or the type of data being analyzed. Generic measurement instruments and general purpose environments are considered insignificant extra solution activity and do not integrate the abstract idea into a practical application. See MPEP 2106.05(h)(g)(f).
Accordingly, for the reasons above and those discussed in relation to independent claim 1 and 12, the dependent claims are insufficient to integrate the claimed abstract ideas into a practical application or significant more.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-12, and 19-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 6246717 B1, Chen et al (hereinafter Chen).
Regarding Claim 1 and 12, Chen disclose a signal processing circuit, comprising: an input interface and an analysis circuit (Chen, [Col. 4 Line 25-31] The transmission system receiver 10 includes a hardware front end 12 receiving a digitally modulated RF input signal 14. The RF signal 14 is down converted to a digitally modulated intermediate frequency (IF) signal by RF hardware down converter circuitry 16 that generally includes one or more mixers in the IF signal path),
wherein the input interface is configured to receive a measurement signal and a reference signal (Chen, [Col. 4 Line 15-17] the invention is described using baseband filtered, unfiltered and reference signal samples that have been processed through linear equalization processes), wherein the input interface is configured to forward the measurement signal and the reference signal to the analysis circuit (Chen, [Col. 7 Line 26-43] the filtered signal samples from memory 20 are input to the reference signal sample generator 52 with the unfiltered signal samples being filtered by the low pass filter 50 and the coupled to the phase error detector 54 via the delay 56. The reference signal sample generator 52 produces reference signal samples representing the estimated symbol values that were transmitted at the transmitter of the transmission system with the estimated symbol values in the same state as the signal samples at the output of lowpass filter 50),
wherein the measurement signal and the reference signal comprise a symbol sequence (Chen, [Col. 2 Line 29-37] which are 8-VSB symbols in the preferred embodiment but may be other digital formats, are estimated for the purpose of generating reference signal samples representing the transmitted symbols. This is performed by applying the receiver filter to the unfiltered signal samples, dynamically estimating constellation decision levels from the filtered samples, and then slicing the signal samples accordingly. Reference signal samples are generated from the estimated digital symbols), respectively,
wherein the analysis circuit is configured to:
synchronize (Chen, [Col. 10 Line 15-22] the unfiltered signal samples {r.sub.i (n)}, {r.sub.q (n)} and the reference signal samples {c.sub.i (n)}, {c.sub.q (n)} are synchronized with each other in the preferred embodiment by means of a delay 56) the measurement signal with the reference signal (Chen, [Col. 5 Line 62-66] the received signal samples are also time aligned, scaled and linearly equalized by the improved demodulator 34, although equalization may not be necessary if no significant linear distortions are present);
determine error vectors (Chen, [Col. 5 Line 49-52] This is represented in FIG. 2 by line 44 for vectors representing received signal samples 82, 84, and 86 of transmitted data having nonlinear magnitude, phase errors and intersymbol interference) based on the synchronized measurement signal and reference signal (Chen, [Col. 10 Line 35-43] the following is performed by applying the phase error values .theta.(n) derived from the reference and unfiltered signal samples in the phase error estimator 54 and the reference magnitude values M(n) from the magnitude computer 58 to the nonlinear phase error estimator 60 containing an outlier remover 100, a least-squares polynomial curve fitter 102 and a nonlinear phase error evaluator 104);
determine symbol points of the symbol sequence (Chen, [Col. 7 Line 61 - Col. 8 Line 2] unfiltered signal samples are first filtered by the transmission system's receiver filter 68 (a complex root raised cosine (RRC) filter in the preferred embodiment) and down sampled to symbol times by down sampler 70 before a multi-region dynamic slicer 72 determines the transmitted symbols. The multi-region dynamic slicer 72 produces signal samples representing symbols denoted as {x.sub.i (n), x.sub.q (n)} from the unfiltered signal samples that have passed through the RRC filter 68) and decision boundaries for the symbol points (Chen, [Col. 8 Line 5-10] Since large nonlinear distortion may cause constellation curvature, to perform an accurate symbol estimate, the constellation space having I and Q-dimensions is divided by the multi-region slicer 72 into several regions along the quadrature-dimension (Q-dimension) as shown in FIG. 6); and
determine whether the determined error vectors (Chen, [Col. 10 Line 43-49] the outlier remover 100 establishes boundaries or thresholds in phase error versus magnitude space for removing largely deviated phase error values that affect the accuracy of estimating a phase nonlinear function. The signal magnitude range, derived from the reference signal samples, is divided into several subranges R.sub.M (k) (k=0, 1, . . . K) in the outlier remover 100) exceed the decision boundaries determined (Chen, [Col. 11 Line 10-15] the decision boundaries or thresholds for detecting outliers in the large magnitude regions may be implemented in the following manner for large magnitude regions. The decision boundaries are based on the mean and variance of the phase error in the respective large magnitude subranges).
Regarding Claim 8 and 19, Chen disclose the signal processing circuit of claim 1, wherein the measurement signal is a digital file or a digital data stream (Chen, [Col. 4 Line 32-35] an analog-to-digital (A/D) converter 18 receives the digitally modulated IF signal and converts the signal to digital data values that are stored in memory 20).
Regarding Claim 9 and 20, Chen disclose the signal processing circuit of claim 1, wherein the measurement signal is a radio frequency signal obtained by a measurement, or wherein the reference signal is a radio frequency signal obtained by a measurement (Chen, [Col. 3 Line 64 – Col. 4 Line 4] modulation of a RF carrier in a digital transmission system occurs in the analog domain with the modulation waveform on the RF carrier being based on the digital content and will be referred hereafter as a digitally modulated radio frequency signal. The preferred embodiment of the present invention will be described in relation to one of these digital transmission systems, specifically an 8-VSB digital television transmission system).
Regarding Claim 10, Chen disclose a measurement instrument, comprising a signal processing circuit according to claim 1 (Chen, [Col. 3 Line 45-52] quantities take the form of electrical, magnetic, or optical signals capable of being stored, transferred, combined and otherwise manipulated through mechanical and electrical components of the computer system; and the term computer system includes general purpose as well as special purpose data processing machines, systems, and the like, that are stand alone, adjunct or embedded).
Regarding Claim 11, Chen disclose the measurement instrument of claim 10, wherein the measurement instrument is a signal analyzer, a spectrum analyzer, an oscilloscope, or a vector network analyzer (Chen, [Col. 7 Line 52-56] A spectrum analyzer 67 function receives the resultant carrier phase noise from the additive phase noise suppressor 66 and generates power spectrum values of the phase noise, which is coupled to the display 26).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7 and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 6246717 B1, Chen et al (hereinafter Chen) in view of US 20150163015 A1, Katayama et al. (hereinafter Katayama).
Regarding Claim 2 and 13, Chen in view of Katayama teaches the signal processing circuit of claim 1, wherein the analysis circuit is configured to determine the number of error vectors (Katayama, [0066] A symbol error rate can be roughly calculated for each symbol decision region from a region S.sub.error which is protruding part of the black circle originally located in the adjacent decision region and a region S.sub.correct which is part of the black circle originally located in the decision region when a distribution of the signal point of a symbol represented by the black circle is phase-rotated at a certain rotation angle with respect to the origin of the complex plane) exceeding the decision boundaries (Katayama, [0057] The symbol decision is performed by deciding a symbol decision region in which the signal point is located. The symbol decision regions are defined by decision boundaries of the I-component and the Q-component on the complex plane. From the symbol decision result, an error (error vector) can be determined as a difference between a position of a signal point at which the symbol of the corrected baseband signal is measured and a position of an ideal signal point based on the symbol decision value).
Before the effective filing date of the claimed invention, It would have been obvious to one of ordinary skill in the art would combine Chen and Katayama’s teaching because Chen already teaches generating symbol decision points, determining error vectors, and establishing decision boundaries for evaluating symbol accuracy, but does not disclose determining the number of error vectors that exceed those boundaries. Katayama, however teaches calculating a symbol error rate by identifying when a received symbol falls outside its correct decision region and exceeds the defined boundaries. A person of ordinary skill would have been motivated to incorporate Katayama’s error counting technique into Chen’s framework since both references address improving symbol decision accuracy in systems, and Katayama’s method would provide Chen with a improvement in quantifying symbol detection and boundary selection.
Regarding Claim 3 and 14, Chen in view of Katayama teaches the signal processing circuit of claim 2, wherein the analysis circuit is configured to determine a symbol error rate (SER) (Katayama, [0069] Note that the aforementioned symbol error rate may be calculated on the assumption of a uniform probability distribution with a small diameter described above or of a Gaussian distribution) based on the determined number of error vectors exceeding the decision boundaries (Katayama, [0069] the margins of error may be compared using an angle at which the edge of a black circle representing a signal point in a decision region reaches its adjacent decision region or an angle (allowable range) at which a black circle in a decision region starts to run over to the adjacent decision region; and weighting may be performed based on the comparison. Note that the specific weight value need not be set in proportion to the symbol error rate or the margin of error).
Before the effective filing date of the claimed invention, It would have been obvious to one of ordinary skill in the art would combine Chen and Katayama’s teaching because Chen already determines symbol decision points, generating error vectors and evaluates decision boundaries but does not convert the error determinations into a symbol error rate metric. Katayama teaches calculating symbol error rate based on the number of symbol points that exceed decision boundaries and provide multiple methods for comparing margins of error. A person of ordinary skill would have been motivated to incorporate Katayama’s SER computation into Chen’s system because both references address improving symbol detection accuracy in communication receivers, and applying Katayama’s known SER technique to Chen’s techniques to enhance evaluation without altering Chen’s architecture.
Regarding Claim 4 and 15, Chen in view of Katayama teaches the signal processing circuit of claim 1, wherein the analysis circuit is configured to determine a modulation scheme of the measurement signal based on the measurement signal and/or based on the reference signal (Katayama, [0043] The transmission circuit 192 modulates transmission data input from the protocol stack 190 in accordance with an adopted modulation scheme to generate a transmission baseband signal, and outputs the transmission baseband signal to the transmission circuit 196 of the RF unit 184 via the DACs 194. The reception circuit 122 receives a reception baseband signal demodulated by the reception circuit 126 of the RF unit 114 via the ADCs 124, restores reception data in accordance with the modulation scheme, and outputs the reception data to the protocol stack 120).
Before the effective filing date of the claimed invention, It would have been obvious to one of ordinary skill in the art would combine Chen and Katayama’s teaching because Chen already demodulates the received signal and produces reference and measurement symbol sequences but does not expressly identify or classify the modulation scheme used for those signals. Katayama teaches determining or operating according to the modulation scheme during both transmission and reception. A person of ordinary skill would’ve been motivated to incorporate Katayama’s modulation scheme determination into Chen’s system because Chen already processes symbol sequences and applying Katayama’s known technique would improve Chen’s ability to classify and analyze incoming signals without requiring structural modification.
Regarding Claim 5 and 16, Chen in view of Katayama teaches the signal processing circuit of claim 4, wherein the decision boundaries are determined based on the determined modulation scheme (Katayama, [0065] FIG. 6 is a diagram that explains margins of error of individual symbol decision regions in the case of 16QAM, for example. As illustrated in FIG. 6, in the case of 16QAM, there are 16 symbol decision regions in the constellation diagram).
Before the effective filing date of the claimed invention, It would have been obvious to one of ordinary skill in the art would combine Chen and Katayama’s teaching because Chen already determines symbol points and performs error vector analysis related to decision boundaries but does not disclose adapting those decision boundaries based on the specific modulation scheme being used. Katayama however teaches that the arrangement and regions depend on the adopted modulation format and that margins of error and boundary locations are determined based on the modulation scheme. A person of ordinary skill in the art would have been motivated to incorporate Katayama’s modulation structure into Chen’s system because Chen’s existing methods operate on symbol constellations whose boundaries vary based on the modulation type.
Regarding Claim 6 and 17, Chen in view of Katayama teaches the signal processing circuit of claim 1, wherein the signal processing circuit is configured to transform the determined decision boundaries to an origin of a constellation plane (Katayama, [0066] A symbol error rate can be roughly calculated for each symbol decision region from a region S.sub.error which is protruding part of the black circle originally located in the adjacent decision region and a region S.sub.correct which is part of the black circle originally located in the decision region when a distribution of the signal point of a symbol represented by the black circle is phase-rotated at a certain rotation angle with respect to the origin of the complex plane).
Before the effective filing date of the claimed invention, It would have been obvious to one of ordinary skill in the art would combine Chen and Katayama’s teaching because Chen already evaluates symbol errors relative to decision boundaries but does not describe transforming those boundaries on a constellation plane. Katayama teaches analyzing symbol decision regions by requiring mapping or transforming decision boundaries with respect to the origin. A person of ordinary skill in the art would have been motivated to incorporate Katayama’s analysis into Chen’s system as it would improve the ability to compare symbol errors across modulation schemes and would not require altering Chen’s architecture.
Regarding Claim 7 and 18, Chen in view of Katayama teaches all of the elements of parent claims 6 and 17 respectively, Chen further discloses wherein the constellation plane is an IQ plane (Chen, [Col. 8 Lines 7-10] the constellation space having I and Q-dimensions is divided by the multi-region slicer 72 into several regions along the quadrature-dimension (Q-dimension) as shown in FIG. 6).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclose:
-US 7352832 B1, describing technique for reducing signal distortion in digital communication systems. The reference discusses a symbol detector configured to establish decision boundaries, symbol decisions, and determine an error rate associated with those decisions. The reference further explains adjusting or reshaping the decision boundaries based on generated parameters to improve symbol detection accuracy in modulation schemes.
-US 6671334 B1, describing a receiver architecture that processes filtered and unfiltered signal samples through demodulation and compensation paths. The reference teaches generating compensated, time aligned, and scaled signals for symbol detection and analysis. The teachings relate to correcting distortions in received modulation signals by applying equalization, resampling, and boundary decisions techniques to improve accuracy in determining symbol information.
-US 20030198288 A1, describing modems and communication systems that utilize error signals to select an appropriate data rate. The reference teaches determining an error difference between a received signal and an equalized signal in order to adjust decoder thresholds and improve symbol reliability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM NAGI SHOHATEE whose telephone number is (571)272-6612. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby Turner can be reached at (571) 272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IBRAHIM NAGI SHOHATEE/Examiner, Art Unit 2857
/SHELBY A TURNER/Supervisory Patent Examiner, Art Unit 2857
Prosecution Insights