DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 01/15/2025 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-6, 8-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimamoto (U.S. 12,199,573).
Regarding claim 1, Shimamoto (hereinafter, Ref~573) discloses (please see Fig. 1 and/or Fig. 15 for details) an apparatus (see apparatus of Fig. 1) comprising:
an amplifier circuit (centered by 201/202 of Fig. 2) including an input port (101 of Fig. 1) and an output port (102 of Fig. 1), the amplifier circuit comprising:
a driver amplifier (201 of Fig. 1) including a driver amplifier output (RF1 of Fig. 1) and a transistor (please note that the generic amplifier/driver circuit 201 of Fig. 1 inherently required at least one or mor transistor(s) in order to operate), the driver amplifier coupled between the input port and the output port;
a power amplifier (centered by 202 of Fig. 1) including a power amplifier input (203 of Fig. 1), the power amplifier coupled between the driver amplifier output and the output port as seen; and
a Darlington circuit (302 of Figs. 1-2) coupled to the driver amplifier via a node (304 of Fig. 2) that is coupled between the input port and the power amplifier input, meeting claim 1.
Regarding claim 2, Ref~573 discloses the apparatus of claim 1, further comprising:
an integrated circuit die (please note the circuit may be integrated as described in col. 1, between lines 25-30) that comprises the amplifier circuit, wherein the Darlington circuit is configured to provide electrostatic discharge (ESD) protection (due to diodes 301 of Fig. 2 configured to detect and suppress voltage fluctuations as described in col. 8) for the integrated circuit die, meeting claim 2.
Regarding claim 4, Ref~573 discloses the apparatus of claim 1, wherein the Darlington circuit is coupled to a power distribution node (203 of Fig. 1 can be read as the claimed node) for the transistor of the driver amplifier, meeting claim 4.
Regarding claim 5, Ref~573 discloses the apparatus of claim 4, wherein the power distribution node comprises a supply voltage node, since said node is connected to power supply, meeting claim 5.
Regarding claim 6, Ref~573 discloses the apparatus of claim 1, wherein the Darlington circuit is coupled to a channel terminal (collector or drain terminal) of the transistor of the driver amplifier as seen, meeting claim 6.
Regarding claim 8, Ref~573 discloses the apparatus of claim 1, wherein: the node is coupled between a driver amplifier input of the driver amplifier and the power amplifier input as seen in Fig. 1; and
the node corresponds to: a channel terminal (collector) of the transistor of the driver amplifier; and a supply voltage node (Vcc1 of Fig. 1) for the transistor of the driver amplifier, meeting claim 8.
Regarding claim 9, Ref~573 discloses the apparatus of claim 1, wherein the Darlington circuit comprises: two or more transistors (3021/3022 of Fig. 2) coupled together in a Darlington transistor arrangement, the Darlington transistor arrangement coupled between the node and a power distribution node (ground), meeting claim 9.
Regarding claim 10, Ref~573 discloses the apparatus of claim 9, wherein the Darlington circuit comprises: at least one diode (diodes from 301 of Fig. 2), wherein the Darlington transistor arrangement and the at least one diode are coupled together in series between the node and the power distribution node as seen from Fig. 2, meeting claim 10.
Regarding claim 11, Ref~573 discloses the apparatus of claim 9, wherein: the two or more transistors comprise a first transistor (3022 of Fig. 2) and a second transistor (3021 of Fig. 2); and
a channel terminal (emitter of 3022 of Fig. 2) of the first transistor is coupled to a control terminal (base of 3021 of Fig. 2) of the second transistor, meeting claim 11.
Regarding claim 12, Ref~573 discloses the apparatus of claim 11, wherein the Darlington circuit comprises: multiple diodes (3011:3016 of Fig. 2) coupled together in series between the node and a control terminal (base of 3022 of Fig. 2) of the first transistor of the two or more transistors, meeting claim 12.
Regarding claim 13, Ref~573 supports the claimed “wherein the Darlington circuit is configured to clamp a voltage at the node responsive to a voltage level that is based, at least partly, on a quantity of diodes of the multiple diodes” as described throughout the disclosure, meeting claim 13.
Regarding claim 14, Ref~573 supports the claimed “wherein the Darlington circuit is configured to increase a clamping action on a voltage at the node as the voltage at the node increases”, it is configured in the same manner compared to the claimed one, meeting claim 14.
Regarding claim 16, Ref~573 discloses the apparatus of claim 15, wherein the Darlington circuit comprises: at least one resistor (3011 of Fig. 2) coupled in series with the at least one diode (3012:3016 of Fig. 2) between the control terminal of the first transistor and the power distribution node, meeting claim 16.
Regarding claim 17, Ref~573 discloses the apparatus of claim 1, further comprising: a radio-frequency front-end (mobile devices mentioned, thus the PA would be configured to drive antenna load) comprising the amplifier circuit as broadly descried in the background/col. 1 of the present invention, meeting claim 17.
As to claims 18-20, these claims are merely the method and means to operate the circuit having structure recited in claims 1-17. Since Ref~573 teaches the structure, the method and means to operate such a circuit is inherently disclosed, meeting claims 18-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shimamoto (U.S. 12,199,573).
Regarding claim 3, Ref~573 supports the apparatus of claim 1, further comprising:
an integrated circuit die (please note the circuit of Ref~573 may be integrated as broadly described in col. 1, between lines 25-30. In addition, these are normal design parameters/features in the field depending on custom specifications) that comprises the amplifier circuit, wherein the Darlington circuit is configured to provide power clamping for the integrated circuit die with respect to power that is supplied to the driver amplifier, meeting claim 3.
Regarding claim 7, Ref~573 supports the claimed “wherein: the transistor of the driver amplifier comprises a heterojunction bipolar transistor (HBT); and the channel terminal comprises a collector terminal”, since it appears that BJT or the like would be used for the invention as shown in Fig. 2. In addition, these are normal design features in the field depending on custom specifications. Specifically, HBT would offers low noise, higher gain and better efficiency at high speed for RF applications, meeting claim 7.
Regarding claim 15, Ref~573 discloses the apparatus of claim 11, wherein the Darlington circuit comprises: at least one diode (diode 3011:3016 of Fig. 2) coupled between a control terminal (base terminal and assuming that the generic driver 2011 employed with a feedback network as widely-used in the field to at least provide stability for the system) of the first transistor and the power distribution node, meeting claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843