DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 13, 14, 20, 24 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Wu et al (Fig. 1); 11,063,355].
Regarding claims 1 and 24, Wu et al discloses an amplifier circuit comprising an input matching network (110, 120), a vector modulator (111, 112, 113, 114) connected to the input matching network (110, 120), the vector modulator (111, 112, 113, 114) configured to alter an amplitude of signals provided by the input matching network (110, 120), bias networks (V TXO, V RXO) coupled to outputs (outputs of the 111, 112, 113, 114) of the vector modulator (111, 112, 113, 114), and a combining circuit (130) connected to the outputs (outputs of the 111, 112, 113, 114) of the vector modulator (111, 112, 113, 114) and the combining circuit (130) configured to generate a first phase signal from the outputs (outputs of the 111, 112, 113, 114) of the vector modulator (111, 112, 113, 114).
Regarding claim 2, wherein the vector modulator (111, 112, 113, 114) is an active device (transistors in the 111, 112, 113, 114).
Regarding claim 3, wherein the combining circuit (130) is a quadrature all pass filter.
Regarding claim 4, wherein the quadrature all pass filter is a passive device.
Regarding claim 5, wherein the vector modulator (111, 112, 113, 114) comprises an in phase variable gain amplifier and a quadrature variable gain amplifier which is well known in the amplifier art.
Regarding claims 13 and 20, Wu et al discloses the method steps of dividing (101) an input signal (FIRST IQ) into a first portion (I) and a second portion (Q) and adjusting (111-114) an amplitude of the first portion (I) and a second portion (Q), biasing (V TXO, V RXO) the amplitude adjusted first portion (outputs of 111 and 112) and the amplitude adjusted second portion (outputs of 111 and 112), and passively combining (130) the amplitude adjusted first portion (outputs of 111 and 112) and the amplitude adjusted second portion (outputs of 111 and 112) to generate a first phase signal (SECOND IQ).
Regarding claim 14, wherein adjusting an amplitude of the first and second portions comprises actively adjusting (111-114) an amplitude of the first and second portions using active variable gain amplifiers (111-114).
Regarding claim 30, the limitation recited in claim 30 is intended use of the invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 25, 26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over [Wu et al (Fig. 1); 11,063,355] in view of [Ezzeddine et al (Fig. 1); 8,427,241].
Regarding claim 25, Wu et al discloses all the limitations in claim 25 except for that the QAF is coupled to drains of transistors in the variable gain amplifier having a cascode configuration. Ezzeddine et al discloses an amplifier circuit comprising the transistors being connected in a cascode configuration. It would have been obvious to substitute Ezzeddine et al’s amplifier (four transistors in Fig. 1 of Ezzeddine et al) in place of Wu et al’s transistors (111-114 in Fig. 1 of Wu et al) since Wu et al discloses the generic transistors thereby suggesting that any equivalent transistors would have been usable in Wu et al’s reference.
Regarding claim 26, Wu et al further comprising a plurality of variable gain amplifiers (111-1114) which are coupled to the output (output of 110, output of 120) of the input matching network (110, 120) and wherein each of the plurality of variable gain amplifiers (111-1114) comprising an output coupled to the QAF (130).
Regarding claim 28, Wu et al discloses all the limitations in claim 25 except for that the variable gain amplifier comprises a second transistor having a drain and a gate and a source and the source of the second transistor coupled to a drain of the amplification transistor and the drain of the second transistor coupled to a supply voltage, and the gate of the second transistor coupled to a control signal. Ezzeddine et al discloses an amplifier circuit comprising a second transistor (FET2) having a drain (drain of FET2) and a gate (gate of FET2) and a source (source of FET2) and the source (source of FET2) of the second transistor (FET2) coupled to a drain (drain of FET1) of the amplification transistor (FET1) and the drain (drain of FET2) of the second transistor (FET2) coupled to a supply voltage (Vdd), and the gate (gate of FET2) of the second transistor (FET2) coupled to a control signal (the signal applying to the gate terminal of FET2). Therefore, it would have been obvious to substitute Ezzeddine et al’s amplifier (FET1 and FET2 transistors in Fig. 1 of Ezzeddine et al) in place of Wu et al’s transistors (111-114 in Fig. 1 of Wu et al) since Wu et al discloses the generic transistors thereby suggesting that any equivalent transistors would have been usable in Wu et al’s reference.
Allowable Subject Matter
Claims 6-12, 15-19, 21-23, 27 and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HENRY CHOE/ Primary Examiner, Art Unit 2843
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