Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no case, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Claim Objections
Claim 1 is objected to because of the following informalities: claim 1 in its current amended form recites on line 10, (first line of the last paragraph), “a Darlington circuit located within the amplifier circuit to limit a signal E”, where it is not understood what the letter “E” indicates? The reference designation in Figs. 6-1 and 6-2 to indicate reference points on the circuit have been identified as A through D, however, there is no E in any of the drawings. Furthermore, applicants must be aware of avoiding mention of reference designators (of figures of the embodiment) in claims (MPEP § 2173.05(s)1).
Appropriate correction is required.
Response to Arguments
After careful consideration examiner doesn’t consider Applicant's arguments filed on 04/29/2026 are persuasive.
Among other arguments, most importantly applicant argues that “As depicted in Yintat's FIG. 1, Yintat's "ESD Protection Circuits" (which are different from the "ESD Protection Diode" at the base of the first transistor) are located on bias circuit pads or voltage supply line pads (see VREF1, VCC1, VC1, VREF2, VCC2 in FIG. 1) or after a trailing transistor in Yintat's "Second Stage" as annotated by the Office (see ESD Protection Circuit at collector of final transistor, connected to VC2 supply voltage in FIG. 1) where no ESD Protection Circuit described by Yintat could "limit a signal at the power amplifier input that propagated from the driver amplifier output to the power amplifier input downstream of the driver amplifier output" as similarly recited in Applicant's independent claims 1 and 20”.
Examiner disagrees, please see Fig.1 of Yintat annotated by the examiner for ease of reference. Once the forward voltages of series diode chain D2 (Fig. 6b) is reached along with adequate base voltage to turn on Q2 and Q3 with the voltage drop in Dr+R1, the Darlington pair would provide low impedance path for the signal at the node between the driver and power amplifier (page 225, par. left and right). Structurally applicant’s limiting circuit is identical to Yintat’s protection circuit.
[AltContent: textbox (RF )][AltContent: arrow][AltContent: oval][AltContent: textbox (N1)]
PNG
media_image1.png
388
780
media_image1.png
Greyscale
Fig. 1 of Yintat annotated by the examiner for ease of reference.
See side by side by comparison of Yintat’s protection circuit versus applicant’s protection circuit. Identical circuits placed at identical locations in a similar circuit should behave similarly, it is common knowledge in the art.
PNG
media_image2.png
388
702
media_image2.png
Greyscale
Fig. 6(a) of Yintat (left) versus Fig. 4-2 of the applicant (right).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 - 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yintat (ESD Protection Design Considerations for InGaP/GaAs HBT RF Power Amplifiers. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005).
Regarding Independent Claim 1, Yintat teaches,
An apparatus (See Fig. 1) comprising:
an amplifier circuit (Fig. 1, amplifier of MMIC) including an input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT), the amplifier circuit comprising:
a driver amplifier (Fig. 1, first stage of MMIC. See page 226, right-hand side column, “The schematic of this PA is shown in Fig. 1. It consists of two stages, i.e., the driver and output stages”) including a driver amplifier output (Fig. 1, collector of transistor in the driver stage), the driver amplifier coupled between the input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT);
a power amplifier (Fig. 1, second stage of MMIC) including a power amplifier input (Fig. 1, base of transistor in the second stage), the power amplifier coupled between the driver amplifier output and the output port (Fig. 1, second stage of MMIC is between the first stage of the MMIC and the output port);
an interstage matching network (Fig. 1, T-matching circuit comprising two capacitors and a transmission line) coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage); and
a Darlington circuit (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2. See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”) coupled to the interstage matching network via a node (N1) that is coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage). A Darlington circuit (Q2-Q3 in Fig. 6(a) of Yintat) located within the amplifier circuit to limit a signal at the RF node between driver amplifier output and the power amplifier input.
PNG
media_image3.png
410
754
media_image3.png
Greyscale
Fig. 1 of Yintat annotated by examiner for ease of examination
Regarding claim 2,
The apparatus of claim 1, further comprising:
an integrated circuit die (See page 221, right-hand side column, “Furthermore, a novel compact ESD protection circuit for PAs will be introduced, which does not add more PA chip area.”) that comprises the amplifier circuit.
Regarding claim 3,
The apparatus of claim 1, wherein the node is coupled between a channel terminal of a transistor of the driver amplifier (Fig. 1, first stage of MMIC) and a control terminal of a transistor of the power amplifier (Fig. 1, second stage of MMIC).
Regarding claim 4,
The apparatus of claim 1, wherein the interstage matching network comprises a T-network (Fig. 1, T-matching circuit).
Regarding claim 5,
The apparatus of claim 4, wherein the T-network comprises:
a first capacitor (Fig. 1, first capacitor in the T-matching circuit) coupled between the driver amplifier output and the power amplifier input;
a second capacitor (Fig. 1, second capacitor in the T-matching circuit) coupled between the driver amplifier output and the power amplifier input; and
an inductor (Fig. 1, transmission line in the T-matching circuit) coupled between an interstage matching network node and a power distribution node, the interstage matching network node coupled between the first capacitor and the second capacitor.
Regarding claim 6,
The apparatus of claim 1, wherein the interstage matching network comprises a Pi-network (Fig. 1, T-matching circuit).
Regarding claim 7,
The apparatus of claim 1, wherein the Darlington circuit (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2) is coupled between the node and a power distribution node (See Fig. 6 (b)).
Regarding claim 8,
The apparatus of claim 7, wherein the power distribution node comprises a ground node (Fig. 6 (b), ground).
Regarding claim 9,
The apparatus of claim 1, wherein:
the Darlington circuit (See Fig. 6 (b)) comprises:
two or more transistors (Fig. 6 (b), Q2 and Q3) coupled together in a Darlington transistor arrangement, the Darlington transistor arrangement comprising a control terminal and a first channel terminal (Fig. 6 (b), terminals of Q2 and Q3); and
one or more diodes (Fig. 6 (b), D2) coupled between the control terminal and the first channel terminal; and
the first channel terminal (Fig. 6 (b), terminal of Q2 and Q3) is coupled to the node.
Regarding claim 10,
The apparatus of claim 9, wherein:
the two or more transistors comprise a first transistor (Fig. 6 (b), Q2) and a second transistor (Fig. 6 (b), Q3);
a channel terminal of the first transistor (Fig. 6 (b), channel terminal of Q2) is coupled to a control terminal of the second transistor (Fig. 6 (b), control terminal of Q3);
a control terminal of the first transistor (Fig. 6 (b), control terminal of Q2) corresponds to the control terminal of the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3);
a first channel terminal of the second transistor (Fig. 6 (b), first channel terminal of Q3) corresponds to the first channel terminal of the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3); and
a second channel terminal of the second transistor (Fig. 6 (b), second channel terminal of Q3) corresponds to a second channel terminal of the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3).
Regarding claim 11,
The apparatus of claim 9, wherein:
the one or more diodes (Fig. 6 (b), D2) comprise multiple diodes coupled together in series between the control terminal and the first channel terminal (Fig. 6 (b), D2 is comprised of multiple diodes connected in series); and
the Darlington circuit is configured to clamp a voltage at the node responsive to a voltage level that is based, at least partly, on a quantity of diodes of the multiple diodes (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Regarding claim 12,
The apparatus of claim 11, wherein the Darlington circuit is configured to increase a clamping action on the voltage at the node as the voltage at the node increases (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Regarding claim 13,
The apparatus of claim 9, wherein:
the Darlington circuit (Fig. 6 (b)) comprises a first Darlington circuit of the amplifier circuit (Fig. 6 (b), Q2), and the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3) comprises a first Darlington transistor arrangement (Fig. 6 (b), arrangement of Q2);
the amplifier circuit comprises a second Darlington circuit (Fig. 6 (b), Q3);
the second Darlington circuit (Fig. 6 (b), Q3) comprises:
two or more transistors coupled together in a second Darlington transistor arrangement (Fig. 6 (b), arrangement of Q3), the second Darlington transistor arrangement comprising a control terminal, a first channel terminal, and second channel terminal (Fig. 6 (b), terminals of Q3); and
one or more diodes (Fig. 6 (b), D2) coupled between the control terminal of the second Darlington transistor arrangement (Fig. 6 (b), control terminal of arrangement of Q3) and the first channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), first channel terminal of arrangement of Q3); and
the second channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), second channel terminal of arrangement of Q3) is coupled to the node.
Regarding claim 14,
The apparatus of claim 13, wherein:
the first Darlington transistor arrangement (Fig. 6 (b), arrangement of Q2) comprises a second channel terminal (Fig. 6 (b), second channel terminal of arrangement of Q2);
the second channel terminal of the first Darlington transistor arrangement (Fig. 6 (b), second channel terminal of arrangement of Q2) is coupled to a power distribution node; and
the first channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), first channel terminal of arrangement of Q2) is coupled to the power distribution node.
Regarding claim 15,
The apparatus of claim 14, wherein the power distribution node comprises a ground node (Fig. 6 (b), ground).
Regarding claim 16,
The apparatus of claim 13, wherein:
the first Darlington transistor arrangement comprises a second channel terminal (Fig. 6 (b), second channel terminal of arrangement of Q2);
the second channel terminal of the first Darlington transistor arrangement (Fig. 6 (b), second channel terminal of arrangement of Q2) is coupled to the first channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), first channel terminal of arrangement of Q3); and
the first channel terminal of the first Darlington transistor arrangement (Fig. 6 (b), first channel terminal of arrangement of Q2) is coupled to the second channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), second channel terminal of arrangement of Q3).
Regarding claim 17,
The apparatus of claim 16, wherein:
the power amplifier (Fig. 1, second stage of the MMIC) comprises a differential power amplifier including a plus transistor and a minus transistor (Fig. 1, transistor in the second stage of the MMIC);
the first channel terminal of the first Darlington transistor arrangement and the second channel terminal of the second Darlington transistor arrangement correspond to a plus interstage matching network node that is coupled to the plus transistor (Fig. 1, the Darlington transistor arrangements correspond to the terminals of the transistor in the second stage of the MMIC); and
the second channel terminal of the first Darlington transistor arrangement and the first channel terminal of the second Darlington transistor arrangement correspond to a minus interstage matching network node that is coupled to the minus transistor (Fig. 1, the Darlington transistor arrangements correspond to the terminals of the transistor in the second stage of the MMIC).
Regarding claim 18,
The apparatus of claim 16, wherein:
the control terminal of the first Darlington transistor arrangement is coupled to a power distribution node (Fig. 1, the Darlington transistor arrangements are coupled to the power distribution node of the MMIC); and
the control terminal of the second Darlington transistor arrangement is coupled to the power distribution node (Fig. 1, the Darlington transistor arrangements are coupled to the power distribution node of the MMIC).
Regarding claim 19,
The apparatus of claim 16, wherein:
the control terminal of the first Darlington transistor arrangement is coupled to the second channel terminal of the first Darlington transistor arrangement (Fig. 1, the Darlington transistor arrangements are coupled to each other via the active bias circuit); and
the control terminal of the second Darlington transistor arrangement is coupled to the second channel terminal of the second Darlington transistor arrangement (Fig. 1, the Darlington transistor arrangements are coupled to each other via the active bias circuit).
Regarding claim 20,
The apparatus of claim 1, further comprising:
a radio-frequency front-end (See page 221, right-hand side column, “Furthermore, a novel compact ESD protection circuit for PAs will be introduced, which does not add more PA chip area. It is based on a low-power conducting diode string to trigger turn on of a high current conducting switch, i.e., a Darlington pair. With proper sizing of the components (diode, transistor, and resistor), the main amplifier and the ESD protection circuit can be designed to meet ESD requirements without degrading RF and output power performance as demonstrated in the 5.4–6.0-GHz PA”) comprising the amplifier circuit.
Regarding Independent claim 21,
An apparatus (See Fig. 1) comprising:
an amplifier circuit (Fig. 1, amplifier of MMIC) including an input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT), the amplifier circuit comprising:
a driver amplifier (Fig. 1, first stage of MMIC. See page 226, right-hand side column, “The schematic of this PA is shown in Fig. 1. It consists of two stages, i.e., the driver and output stages”) including a driver amplifier input and a driver amplifier output, the driver amplifier input coupled to the input port (Fig. 1, port delivering RF OUT);
a power amplifier (Fig. 1, second stage of MMIC) including a power amplifier input and a power amplifier output, the power amplifier output coupled to the output port (Fig. 1, port delivering RF OUT);
an interstage matching network (Fig. 1, T-matching circuit comprising two capacitors and a transmission line) coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage); and
means for limiting a signal at the power amplifier input (RF node as shown in annotated Fig. 1 of Yintat above) that propagated from the driver amplifier output (First stage output) to the power amplifier input (second stage input) downstream of the driver amplifier output, the means for limiting located within the amplifier circuit and coupled to the interstage matching network (T-matching) at a node (RF node) between the driver amplifier output and the power amplifier input (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2. See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Conclusion
The prior art, SRINIDHI EMBAR et al. (US 2025/0211171 A1) and HONG GUAN-MING (TW 202606193 A) made of record and not relied upon is considered pertinent to applicant's disclosure. Both of these prior arts teaches Darlington pair used in between the driver amplifier and power stages..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
1 Claims should be complete in themselves, and incorporation by reference to a specific figure or table is allowed only in exceptional circumstances where it is impractical to define the invention in words and where it is more concise to incorporate by reference than to duplicate the drawing or table in the claim.
Prosecution Insights