Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/15/2025 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 - 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yintat (ESD Protection Design Considerations for InGaP/GaAs HBT RF Power Amplifiers. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005).
Regarding Independent Claim 1, Yintat teaches,
An apparatus (See Fig. 1) comprising:
an amplifier circuit (Fig. 1, amplifier of MMIC) including an input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT), the amplifier circuit comprising:
a driver amplifier (Fig. 1, first stage of MMIC. See page 226, right-hand side column, “The schematic of this PA is shown in Fig. 1. It consists of two stages, i.e., the driver and output stages”) including a driver amplifier output (Fig. 1, collector of transistor in the driver stage), the driver amplifier coupled between the input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT);
a power amplifier (Fig. 1, second stage of MMIC) including a power amplifier input (Fig. 1, base of transistor in the second stage), the power amplifier coupled between the driver amplifier output and the output port (Fig. 1, second stage of MMIC is between the first stage of the MMIC and the output port);
an interstage matching network (Fig. 1, T-matching circuit comprising two capacitors and a transmission line) coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage); and
a Darlington circuit (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2. See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”) coupled to the interstage matching network via a node that is coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage).
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Fig. 1 of Yintat annotated by examiner for ease of examination
Regarding claim 2,
The apparatus of claim 1, further comprising:
an integrated circuit die (See page 221, right-hand side column, “Furthermore, a novel compact ESD protection circuit for PAs will be introduced, which does not add more PA chip area.”) that comprises the amplifier circuit, wherein the Darlington circuit is configured to provide power clamping for a signal that propagates from the driver amplifier output to the power amplifier input.
Regarding claim 3,
The apparatus of claim 1, wherein the node is coupled between a channel terminal of a transistor of the driver amplifier (Fig. 1, first stage of MMIC) and a control terminal of a transistor of the power amplifier (Fig. 1, second stage of MMIC).
Regarding claim 4,
The apparatus of claim 1, wherein the interstage matching network comprises a T-network (Fig. 1, T-matching circuit).
Regarding claim 5,
The apparatus of claim 4, wherein the T-network comprises:
a first capacitor (Fig. 1, first capacitor in the T-matching circuit) coupled between the driver amplifier output and the power amplifier input;
a second capacitor (Fig. 1, second capacitor in the T-matching circuit) coupled between the driver amplifier output and the power amplifier input; and
an inductor (Fig. 1, transmission line in the T-matching circuit) coupled between an interstage matching network node and a power distribution node, the interstage matching network node coupled between the first capacitor and the second capacitor.
Regarding claim 6,
The apparatus of claim 1, wherein the interstage matching network comprises a Pi-network (Fig. 1, T-matching circuit).
Regarding claim 7,
The apparatus of claim 1, wherein the Darlington circuit (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2) is coupled between the node and a power distribution node (See Fig. 6 (b)).
Regarding claim 8,
The apparatus of claim 7, wherein the power distribution node comprises a ground node (Fig. 6 (b), ground).
Regarding claim 9,
The apparatus of claim 1, wherein:
the Darlington circuit (See Fig. 6 (b)) comprises:
two or more transistors (Fig. 6 (b), Q2 and Q3) coupled together in a Darlington transistor arrangement, the Darlington transistor arrangement comprising a control terminal and a first channel terminal (Fig. 6 (b), terminals of Q2 and Q3); and
one or more diodes (Fig. 6 (b), D2) coupled between the control terminal and the first channel terminal; and
the first channel terminal (Fig. 6 (b), terminal of Q2 and Q3) is coupled to the node.
Regarding claim 10,
The apparatus of claim 9, wherein:
the two or more transistors comprise a first transistor (Fig. 6 (b), Q2) and a second transistor (Fig. 6 (b), Q3);
a channel terminal of the first transistor (Fig. 6 (b), channel terminal of Q2) is coupled to a control terminal of the second transistor (Fig. 6 (b), control terminal of Q3);
a control terminal of the first transistor (Fig. 6 (b), control terminal of Q2) corresponds to the control terminal of the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3);
a first channel terminal of the second transistor (Fig. 6 (b), first channel terminal of Q3) corresponds to the first channel terminal of the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3); and
a second channel terminal of the second transistor (Fig. 6 (b), second channel terminal of Q3) corresponds to a second channel terminal of the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3).
Regarding claim 11,
The apparatus of claim 9, wherein:
the one or more diodes (Fig. 6 (b), D2) comprise multiple diodes coupled together in series between the control terminal and the first channel terminal (Fig. 6 (b), D2 is comprised of multiple diodes connected in series); and
the Darlington circuit is configured to clamp a voltage at the node responsive to a voltage level that is based, at least partly, on a quantity of diodes of the multiple diodes (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Regarding claim 12,
The apparatus of claim 11, wherein the Darlington circuit is configured to increase a clamping action on the voltage at the node as the voltage at the node increases (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Regarding claim 13,
The apparatus of claim 9, wherein:
the Darlington circuit (Fig. 6 (b)) comprises a first Darlington circuit of the amplifier circuit (Fig. 6 (b), Q2), and the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3) comprises a first Darlington transistor arrangement (Fig. 6 (b), arrangement of Q2);
the amplifier circuit comprises a second Darlington circuit (Fig. 6 (b), Q3);
the second Darlington circuit (Fig. 6 (b), Q3) comprises:
two or more transistors coupled together in a second Darlington transistor arrangement (Fig. 6 (b), arrangement of Q3), the second Darlington transistor arrangement comprising a control terminal, a first channel terminal, and second channel terminal (Fig. 6 (b), terminals of Q3); and
one or more diodes (Fig. 6 (b), D2) coupled between the control terminal of the second Darlington transistor arrangement (Fig. 6 (b), control terminal of arrangement of Q3) and the first channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), first channel terminal of arrangement of Q3); and
the second channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), second channel terminal of arrangement of Q3) is coupled to the node.
Regarding claim 14,
The apparatus of claim 13, wherein:
the first Darlington transistor arrangement (Fig. 6 (b), arrangement of Q2) comprises a second channel terminal (Fig. 6 (b), second channel terminal of arrangement of Q2);
the second channel terminal of the first Darlington transistor arrangement (Fig. 6 (b), second channel terminal of arrangement of Q2) is coupled to a power distribution node; and
the first channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), first channel terminal of arrangement of Q2) is coupled to the power distribution node.
Regarding claim 15,
The apparatus of claim 14, wherein the power distribution node comprises a ground node (Fig. 6 (b), ground).
Regarding claim 16,
The apparatus of claim 13, wherein:
the first Darlington transistor arrangement comprises a second channel terminal (Fig. 6 (b), second channel terminal of arrangement of Q2);
the second channel terminal of the first Darlington transistor arrangement (Fig. 6 (b), second channel terminal of arrangement of Q2) is coupled to the first channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), first channel terminal of arrangement of Q3); and
the first channel terminal of the first Darlington transistor arrangement (Fig. 6 (b), first channel terminal of arrangement of Q2) is coupled to the second channel terminal of the second Darlington transistor arrangement (Fig. 6 (b), second channel terminal of arrangement of Q3).
Regarding claim 17,
The apparatus of claim 16, wherein:
the power amplifier (Fig. 1, second stage of the MMIC) comprises a differential power amplifier including a plus transistor and a minus transistor (Fig. 1, transistor in the second stage of the MMIC);
the first channel terminal of the first Darlington transistor arrangement and the second channel terminal of the second Darlington transistor arrangement correspond to a plus interstage matching network node that is coupled to the plus transistor (Fig. 1, the Darlington transistor arrangements correspond to the terminals of the transistor in the second stage of the MMIC); and
the second channel terminal of the first Darlington transistor arrangement and the first channel terminal of the second Darlington transistor arrangement correspond to a minus interstage matching network node that is coupled to the minus transistor (Fig. 1, the Darlington transistor arrangements correspond to the terminals of the transistor in the second stage of the MMIC).
Regarding claim 18,
The apparatus of claim 16, wherein:
the control terminal of the first Darlington transistor arrangement is coupled to a power distribution node (Fig. 1, the Darlington transistor arrangements are coupled to the power distribution node of the MMIC); and
the control terminal of the second Darlington transistor arrangement is coupled to the power distribution node (Fig. 1, the Darlington transistor arrangements are coupled to the power distribution node of the MMIC).
Regarding claim 19,
The apparatus of claim 16, wherein:
the control terminal of the first Darlington transistor arrangement is coupled to the second channel terminal of the first Darlington transistor arrangement (Fig. 1, the Darlington transistor arrangements are coupled to each other via the active bias circuit); and
the control terminal of the second Darlington transistor arrangement is coupled to the second channel terminal of the second Darlington transistor arrangement (Fig. 1, the Darlington transistor arrangements are coupled to each other via the active bias circuit).
Regarding claim 20,
The apparatus of claim 1, further comprising:
a radio-frequency front-end (See page 221, right-hand side column, “Furthermore, a novel compact ESD protection circuit for PAs will be introduced, which does not add more PA chip area. It is based on a low-power conducting diode string to trigger turn on of a high current conducting switch, i.e., a Darlington pair. With proper sizing of the components (diode, transistor, and resistor), the main amplifier and the ESD protection circuit can be designed to meet ESD requirements without degrading RF and output power performance as demonstrated in the 5.4–6.0-GHz PA”) comprising the amplifier circuit.
Regarding Independent claim 21,
An apparatus (See Fig. 1) comprising:
an amplifier circuit (Fig. 1, amplifier of MMIC) including an input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT), the amplifier circuit comprising:
a driver amplifier (Fig. 1, first stage of MMIC. See page 226, right-hand side column, “The schematic of this PA is shown in Fig. 1. It consists of two stages, i.e., the driver and output stages”) including a driver amplifier input and a driver amplifier output, the driver amplifier input coupled to the input port (Fig. 1, port delivering RF OUT);
a power amplifier (Fig. 1, second stage of MMIC) including a power amplifier input and a power amplifier output, the power amplifier output coupled to the output port (Fig. 1, port delivering RF OUT);
an interstage matching network (Fig. 1, T-matching circuit comprising two capacitors and a transmission line) coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage); and
means for clamping a power (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2. See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”) of a signal flowing through the interstage matching network between the driver amplifier and the power amplifier.
Regarding Independent claim 22,
A method comprising:
amplifying, using a driver amplifier (Fig. 1, first stage of MMIC. See page 226, right-hand side column, “The schematic of this PA is shown in Fig. 1. It consists of two stages, i.e., the driver and output stages”), a signal to produce a first amplified signal (Fig. 1, signal from the first stage of MMIC);
propagating the first amplified signal through an interstage matching network (Fig. 1, T-matching circuit comprising two capacitors and a transmission line);
clamping (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2. See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”), in conjunction with the propagating, the first amplified signal to produce an intermediate signal using two or more transistors (Fig. 6 (b), Q2 and Q3) that are coupled together in a Darlington transistor arrangement; and
amplifying, using a power amplifier (Fig. 1, second stage of MMIC), the intermediate signal to produce a second amplified signal (Fig. 1, signal from second stage of MMIC).
Regarding claim 23,
The method of claim 22, wherein the clamping comprises:
clamping a power of the first amplified signal to produce the intermediate signal using multiple diodes (Fig. 6 (b), D2) that establish a clamping voltage based on a quantity of the multiple diodes (Fig. 6 (b), D2), the multiple diodes coupled together in series between a channel terminal and a control terminal of the Darlington transistor arrangement (Fig. 6 (b), D2 is comprised of multiple diodes connected in series).
Regarding claim 24,
The method of claim 22, wherein:
the Darlington transistor arrangement (Fig. 6 (b), Q2 and Q3) comprises a first Darlington transistor arrangement (Fig. 6 (b), Q2); and
the clamping comprises:
clamping the first amplified signal to produce the intermediate signal using the first Darlington transistor arrangement to protect against forward signal swings (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”); and
clamping the first amplified signal to produce the intermediate signal using a second Darlington transistor arrangement to protect against reverse signal swings (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843