uNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/15/2025 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 - 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yintat (ESD Protection Design Considerations for InGaP/GaAs HBT RF Power Amplifiers. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005).
Regarding Independent Claim 1, Yintat teaches,
an amplifier circuit (Fig. 1, amplifier of MMIC) including an input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT), the amplifier circuit comprising:
a driver amplifier (Fig. 1, first stage of MMIC. See page 226, right-hand side column, “The schematic of this PA is shown in Fig. 1. It consists of two stages, i.e., the driver and output stages”) including a driver amplifier output (Fig. 1, collector of transistor in the driver stage), the driver amplifier coupled between the input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT);
a power amplifier (Fig. 1, second stage of MMIC) including a power amplifier input (Fig. 1, base of transistor in the second stage), the power amplifier coupled between the driver amplifier output and the output port (Fig. 1, second stage of MMIC is between the first stage of the MMIC and the output port);
an interstage matching network (Fig. 1, T-matching circuit comprising two capacitors and a transmission line) coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage); and
a clamping circuit (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2. See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”) coupled to the interstage matching network via a node that is coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage), the clamping circuit (See Fig. 6 (b)) comprising a transistor (Fig. 6 (b), Q2 and Q3) and a resistor (Fig. 6 (b), R1) coupled to the transistor.
Regarding claim 2,
The apparatus of claim 1, wherein the resistor (Fig. 6 (b), R1) is coupled between two terminals of the transistor (Fig. 6 (b), Q2 and Q3).
Regarding claim 3,
The apparatus of claim 2, wherein:
the two terminals of the transistor (Fig. 6 (b), Q2 and Q3) comprise a control terminal and a channel terminal (Fig. 6 (b), terminals of Q2 and Q3); and
the resistor (Fig. 6 (b), R1) is coupled between the control terminal of the transistor and the channel terminal of the transistor (Fig. 6 (b), terminals of Q2 and Q3).
Regarding claim 4,
The apparatus of claim 3, wherein:
the transistor (Fig. 6 (b), Q2 and Q3) comprises a bipolar junction transistor (BJT) (Fig. 6 (b), Q2);
the control terminal of the transistor comprises a base terminal of the bipolar junction transistor (Fig. 6 (b), terminal of Q2); and
the channel terminal of the transistor comprises an emitter terminal of the bipolar junction transistor (Fig. 6 (b), terminal of Q2).
Regarding claim 5,
The apparatus of claim 1, further comprising:
an integrated circuit die (See page 221, right-hand side column, “Furthermore, a novel compact ESD protection circuit for PAs will be introduced, which does not add more PA chip area.”) that comprises the amplifier circuit,
wherein the clamping circuit (Fig. 6 (b)) is configured to provide power clamping for a signal that propagates from the driver amplifier output to the power amplifier input.
Regarding claim 6,
The apparatus of claim 1, wherein the node is coupled between a channel terminal of a transistor of the driver amplifier (Fig. 1, terminal of the first stage) and a control terminal of a transistor of the power amplifier (Fig. 1, terminal of the second stage).
Regarding claim 7,
The apparatus of claim 1, wherein the interstage matching network comprises a T-network (Fig. 1, T-matching circuit).
Regarding claim 8,
The apparatus of claim 7, wherein the T-network comprises:
a first capacitor (Fig. 1, first capacitor in the T-matching circuit) coupled between the driver amplifier output and the power amplifier input;
a second capacitor (Fig. 1, second capacitor in the T-matching circuit) coupled between the driver amplifier output and the power amplifier input; and
at least one inductor (Fig. 1, transmission line in the T-matching circuit) coupled between an interstage matching network node and a power distribution node, the interstage matching network node coupled between the first capacitor and the second capacitor.
Regarding claim 9,
The apparatus of claim 8, wherein:
the at least one inductor comprises (Fig. 1, transmission line in the T-matching circuit) two or more inductors electromagnetically coupled together to form at least one transformer (Fig. 1, inductors coupled together are transformers and are well known in the art); and
the node that is coupled between the driver amplifier output and the power amplifier input corresponds to the interstage matching network node (Fig. 1, T-matching circuit).
Regarding claim 10,
The apparatus of claim 1, wherein the interstage matching network comprises a Pi-network (Fig. 1, T-matching circuit).
Regarding claim 11,
The apparatus of claim 1, wherein:
the transistor comprises a control terminal and a channel terminal (Fig. 6 (b), terminal of Q2);
the clamping circuit comprises one or more diodes (Fig. 6 (b), D2) coupled between the control terminal and the channel terminal of the transistor (Fig. 6 (b), terminal of Q2); and
the channel terminal of the transistor (Fig. 6 (b), terminal of Q2) is coupled to the node.
Regarding claim 12,
The apparatus of claim 11, wherein:
the one or more diodes (Fig. 6 (b), D2) comprise multiple diodes coupled together in series between the control terminal and the channel terminal of the transistor (Fig. 6 (b), D2 is comprised of multiple diodes connected in series); and
the clamping circuit is configured to clamp a voltage at the node responsive to a voltage level that is based, at least partly, on a quantity of diodes of the multiple diodes (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Regarding claim 13,
The apparatus of claim 12, wherein the clamping circuit is configured to increase a clamping action on the voltage at the node as the voltage at the node increases (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Regarding claim 14,
The apparatus of claim 1, wherein:
the transistor (Fig. 6 (b), Q2 and Q3) comprises a plus transistor (Fig. 6 (b), Q2) of the clamping circuit, and the resistor (Fig. 6 (b), R1) comprises a plus resistor (Fig. 6 (b), plus resistor of R1) of the clamping circuit;
the plus transistor (Fig. 6 (b), Q2) is coupled between a plus node of the interstage matching network (Fig. 1, T-matching circuit) and a minus node of the interstage matching network (Fig. 1, T-matching circuit);
the clamping circuit comprises a minus transistor (Fig. 6 (b), Q3) and a minus resistor (Fig. 6 (b), minus resistor of R1) coupled to the minus transistor (Fig. 6 (b), Q3); and
the minus transistor (Fig. 6 (b), Q3) is coupled between the plus node of the interstage matching network (Fig. 1, T-matching circuit) and a minus node of the interstage matching network (Fig. 1, T-matching circuit).
Regarding claim 15,
The apparatus of claim 14, wherein:
a first channel terminal of the plus transistor (Fig. 6 (b), terminal of Q2) is coupled to the plus node of the interstage matching network (Fig. 1, T-matching circuit), and a second channel terminal of the plus transistor (Fig. 6 (b), terminal of Q2) is coupled to the minus node of the interstage matching network (Fig. 1, T-matching circuit); and
a first channel terminal of the minus transistor (Fig. 6 (b), terminal of Q3) is coupled to the minus node of the interstage matching network (Fig. 1, T-matching circuit), and a second channel terminal of the minus transistor (Fig. 6 (b), terminal of Q3) is coupled to the plus node of the interstage matching network (Fig. 1, T-matching circuit).
Regarding claim 16,
The apparatus of claim 15, wherein:
the first channel terminal of the plus transistor (Fig. 6 (b), terminal of Q2) comprises a collector terminal of the plus transistor (Fig. 6 (b), terminal of Q2), and the second channel terminal of the plus transistor comprises an emitter terminal of the plus transistor (Fig. 6 (b), terminal of Q2); and
the first channel terminal of the minus transistor (Fig. 6 (b), terminal of Q3) comprises a collector terminal of the minus transistor (Fig. 6 (b), terminal of Q3), and the second channel terminal of the minus transistor comprises an emitter terminal of the minus transistor (Fig. 6 (b), terminal of Q3).
Regarding claim 17,
The apparatus of claim 15, wherein:
the plus resistor (Fig. 6 (b), plus resistor of R1) is coupled between a control terminal of the plus transistor (Fig. 6 (b), Q2) and the minus node of the interstage matching network (Fig. 1, T-matching circuit); and
the minus resistor (Fig. 6 (b), minus resistor of R1) is coupled between a control terminal of the minus transistor (Fig. 6 (b), Q3) and the plus node of the interstage matching network (Fig. 1, T-matching circuit).
Regarding claim 18,
The apparatus of claim 1, further comprising:
a wireless interface device (See page 221, right-hand side column, “Furthermore, a novel compact ESD protection circuit for PAs will be introduced, which does not add more PA chip area. It is based on a low-power conducting diode string to trigger turn on of a high current conducting switch, i.e., a Darlington pair. With proper sizing of the components (diode, transistor, and resistor), the main amplifier and the ESD protection circuit can be designed to meet ESD requirements without degrading RF and output power performance as demonstrated in the 5.4–6.0-GHz PA”) comprising the amplifier circuit.
Regarding claim 19,
The apparatus of claim 18, further comprising:
a display screen (See page 221, right-hand side column, “Furthermore, a novel compact ESD protection circuit for PAs will be introduced, which does not add more PA chip area. It is based on a low-power conducting diode string to trigger turn on of a high current conducting switch, i.e., a Darlington pair. With proper sizing of the components (diode, transistor, and resistor), the main amplifier and the ESD protection circuit can be designed to meet ESD requirements without degrading RF and output power performance as demonstrated in the 5.4–6.0-GHz PA”); and
one or more processors operatively coupled to the display screen and at least a portion of the wireless interface device (See page 221, right-hand side column, “Furthermore, a novel compact ESD protection circuit for PAs will be introduced, which does not add more PA chip area. It is based on a low-power conducting diode string to trigger turn on of a high current conducting switch, i.e., a Darlington pair. With proper sizing of the components (diode, transistor, and resistor), the main amplifier and the ESD protection circuit can be designed to meet ESD requirements without degrading RF and output power performance as demonstrated in the 5.4–6.0-GHz PA”), the one or more processors configured to present one or more graphical images on the display screen based on one or more wireless signals communicated using the amplifier circuit of the wireless interface device.
Regarding Independent claim 20,
An apparatus (See Fig. 1) comprising:
an amplifier circuit (Fig. 1, amplifier of MMIC) including an input port (Fig. 1, port receiving RF IN) and an output port (Fig. 1, port delivering RF OUT), the amplifier circuit comprising:
a driver amplifier (Fig. 1, first stage of MMIC. See page 226, right-hand side column, “The schematic of this PA is shown in Fig. 1. It consists of two stages, i.e., the driver and output stages”) including a driver amplifier input and a driver amplifier output, the driver amplifier input coupled to the input port (Fig. 1, port delivering RF OUT);
a power amplifier (Fig. 1, second stage of MMIC) including a power amplifier input and a power amplifier output, the power amplifier output coupled to the output port (Fig. 1, port delivering RF OUT);
an interstage matching network (Fig. 1, T-matching circuit comprising two capacitors and a transmission line) coupled between the driver amplifier output (Fig. 1, collector of transistor in the driver stage) and the power amplifier input (Fig. 1, base of transistor in the second stage); and
means for clamping a power (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2. See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”) of a signal flowing through the interstage matching network between the driver amplifier and the power amplifier using a transistor (Fig. 6 (b), Q2 and Q3) and a resistor (Fig. 6 (b), R1) coupled to the transistor.
Regarding claim 21,
The apparatus of claim 20, wherein:
the power amplifier comprises a differential power amplifier (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”), and the signal comprises a differential signal; and
the amplifier circuit further comprises means (See Fig. 6 (b)) for balancing plus and minus clamping of the differential signal.
Regarding Independent claim 22,
amplifying, using a driver amplifier (Fig. 1, first stage of MMIC. See page 226, right-hand side column, “The schematic of this PA is shown in Fig. 1. It consists of two stages, i.e., the driver and output stages”), a signal to produce a first amplified signal (Fig. 1, signal from the first stage of MMIC);
propagating the first amplified signal through an interstage matching network (Fig. 1, T-matching circuit comprising two capacitors and a transmission line);
clamping (Fig. 1, any of the ESD protection circuits connected to VC1, VREF2, and VCC2. See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”), in conjunction with the propagating, the first amplified signal to produce an intermediate signal using a transistor (Fig. 6 (b), Q2 and Q3) and a resistor (Fig. 6 (b), R1) coupled to the transistor; and
amplifying, using a power amplifier (Fig. 1, second stage of MMIC), the intermediate signal to produce a second amplified signal (Fig. 1, signal from second stage of MMIC).
Regarding claim 23,
The method of claim 22, wherein the clamping comprises:
increasing a balancing of the clamping between plus and minus voltage swings of differential signaling (See page 225, left-hand side column, “The proposed ESD protection circuit uses a diode string to trigger a Darlington pair, as shown in Fig. 6(b) [9]–[12]. The use of a Darlington pair instead of a single transistor allows lower capacitance due to smaller trigger diode size and less performance variation due to temperature and process variation.”).
Regarding claim 24,
The method of claim 22, wherein:
the transistor (Fig. 6 (b), Q2 and Q3) comprises a plus transistor (Fig. 6 (b), Q2), and the resistor (Fig. 6 (b), R1) comprises a plus resistor (Fig. 6 (b), plus resistor of R1);
the plus resistor (Fig. 6 (b), plus resistor of R1) is coupled between a control terminal of the plus transistor and a first channel terminal of the plus transistor (Fig. 6 (b), terminals of Q2); and
the clamping comprises clamping the first amplified signal using a minus transistor (Fig. 6 (b), Q3) and a minus resistor (Fig. 6 (b), minus resistor of R1), the minus resistor coupled between a control terminal of the minus transistor and a second channel terminal of the plus transistor (Fig. 6 (b), terminals of Q3).
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843