DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to the amendment filed on 3/12/2026.
Claims 4-5, 7, 21-22 and 24 have been canceled.
Claims 1-2, 6, 9, 12-14, 17-19, 23, 26 and 29-30 have been amended.
Claims 31-34 have been added.
Claims 1-3, 6, 8-20, 23 and 25-34 are pending for consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/6/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/12/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Regarding the rejection under 35 U.S.C. 112(b), the claims have been amended to remove the indefinite issue. Therefore, the previous rejection has been withdrawn. However, the amended claims raise new issues. Therefore, a new 112(b) is introduced in this office action.
Regarding the 101 rejection, claims have been amended to recite additional elements that integrate the judicial exception into a practical application. Therefore, Applicant’s arguments are considered and persuasive. The rejection has been withdrawn.
Applicant's arguments filed on 3/12/2026 have been fully considered but they are not persuasive.
Applicant alleges on page 14 of the Remarks that Wu fails to describe or make obvious an apparatus comprising, at least, "a first computation module having a first internal structure, wherein the first internal structure comprises a first static arrangement of routing traces and a first static arrangement of logic gates" and "a second computation module having a second internal structure, wherein the second internal structure comprises a second static arrangement of routing traces and a second static arrangement of logic gates," as claimed.
In response to the above allegation, Examiner respectfully disagrees. According to Applicant’s specification, the static arrangement of routing traces and logic gates appears to describe structure of computation modules (see paragraph 0049 and 0073). Nowhere in the Applicant’s specification discloses how the static arrangements are implemented for the routing traces and logic gates. Therefore, Examiner interprets the claims as best understood. Wu discloses different processors or processor cores, FPGAs or other configurable circuits (i.e., using logic gates and/or an FPGA) that can be used to execute instructions by a single computer (paragraphs 0031 and 0068). Examiner broadly interprets the structures described above as the first computation module and second computation module as recited in the claims.
Applicant’s arguments with respect to claim(s) 1-3, 5-20 and 22-30 have been considered but are moot.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3, 6, 8-20, 23 and 25-34 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 18 and 31-34 recite the following limitations “the first internal structure comprises a first static arrangement of routing traces and a first static arrangement of logic gates”, “the second internal structure comprises a second static arrangement of routing traces and a second static arrangement of logic gates”, “first mapping between bits” and “second mapping between bits” which are not disclosed by the applicant’s specification. Nowhere in the applicant’s specification defines the first internal structure that comprises a first static arrangement of routing traces and a first static arrangement of logic gates and the second internal structure that comprises a second static arrangement of routing traces and a second static arrangement of logic gates. The examiner suggests that for better clarity the newly added limitations should be amended or canceled to remove unsupported subject matter. Claims 2-3, 6, 8-17, 19-20, 23 and 25-30 are depended on the rejected base claims, and are rejected for the same rationales.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 6, 8-20, 23 and 25-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1 and 18, the claims are rejected for lack of sufficient written description. According to MPEP 2161.01 (I), a rejection under 35 U.S.C. 112(b) or the second paragraph of pre-AIA 35 U.S.C. 112 must be made in addition to the written description rejection. According to MPEP 2173, 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph requires that a patent application specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. A secondary purpose is to provide a clear measure of what the inventor or a joint inventor regards as the invention so that it can be determined whether the claimed invention meets all the criteria for patentability and whether the specification meets the criteria of 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph with respect to the claimed invention. Therefore, the claim must be rejected under 112(b) because it does not comply with written description requirement under 35 U.S.C 112(a).
Regarding claims 31-34, the claims are rejected for lack of sufficient written description (i.e., “first static arrangement and second static arrangement” and “first mapping between bits and second mapping between bits”). According to MPEP 2161.01 (I), a rejection under 35 U.S.C. 112(b) or the second paragraph of pre-AIA 35 U.S.C. 112 must be made in addition to the written description rejection. According to MPEP 2173, 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph requires that a patent application specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. A secondary purpose is to provide a clear measure of what the inventor or a joint inventor regards as the invention so that it can be determined whether the claimed invention meets all the criteria for patentability and whether the specification meets the criteria of 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph with respect to the claimed invention. Therefore, the claim must be rejected under 112(b) because it does not comply with written description requirement under 35 U.S.C 112(a).
Dependent claims 2-3, 6, 8-17, 19-20, 23 and 25-30 are rejected under 35 U.S.C. 112(b) as they being dependent upon a rejected base claims 1 and 18, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6, 8-20, 23, 25-31 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20230195943) (hereinafter Wu).
Regarding claim 1, Wu discloses an apparatus for securely performing cryptographic operations comprising (paragraph 0023): a memory (paragraph 0031, random access memory, hard disk memory, optical memory, a floppy disk, a CD, a solid state drive (SSD), server storage, volatile memory, nonvolatile memory, and other tangible mechanisms where instructions may subsequently be retrieved by a machine); and a processor coupled to the memory comprising (paragraphs 0023 and 0030, secure processor chip, where that chip includes circuitry to use and or apply a cryptographic key or other secret, and to provide for a myriad of secure processing functions; paragraph 0031, processor … can also be executed by the same processor, different processors or processor cores, FPGAs or other configurable circuits):
a first computation module having a first internal structure, wherein the first internal structure comprises a first static arrangement of routing traces and a first static arrangement of logic gates, the first computation module configured to (paragraph 0031, circuit processor, circuitry, one or more electronic circuits that are either “hard-wired” (or “dedicated”) to performing the stated function (i.e., in some cases without assistance of instructional logic), and the term can also include a microcontroller, microprocessor, FPGA or other form of processor which is general in design but which runs software or firmware (e.g., instructional logic) that causes or configures general circuitry (e.g., configures or directs a circuit processor) to perform the particular function):
obtain a public data and a security information asset (paragraph 0056, the depicted operations can be performed for elliptic curve cryptography applications, that is, to multiply the coordinates of a point on an elliptic curve corresponding to a private or public key or simply a designated basis vector for purposes of encryption/decryption/digital-signing/key-agreement of an operand; the digital value “P” in this FIG. represents such coordinates and the numerical operator “A” represents a secret (e.g., typically functioning as a private key that can either be a static entity or an ephemeral entity) that is to serve as a scalar multiplier with the digital value “P” so as to calculate the result “A*P;” as is well known, such a process can be performed in conjunction with elliptic curve processing techniques, e.g., for performing Diffie-Hellman key exchange); and
perform a Boolean [math] operation on the public data and the security information asset to generate a first output (paragraphs 0023-0033, 0058-0065 and 0057, firmware or hardware logic is scripted to perform this sequence identification “DSDSDDSDSDSDDD” (where “D” means divide and “S” means subtract), and then to invert the sequence, substituting “A” (additions) for “S” (subtractions), to obtain the reverse order sequence “DDDADADADDADAD.” By taking the digital value “P” and subjecting it to this sequence of double-and-add operations, one thereby obtains the value “630*P.” The control logic 191 controls the accumulator 193 (i.e., a first register) to calculate each term of the multiplication operation (e.g., “630*P=3*210*P”, “150*P=5*30*P”, “20*P=2*10*P”, “5*P” and “2*P=2*1*P”) in the desired term-order, and then uses the depicted memory 195 (i.e., a second memory) to add these terms together; the result, irrespective of the radix math applied, is the desired value “A*P”=“807*P” … functions can be performed either using dedicated hardware logic; paragraphs 0058-0065 and 0060, yielding the aggregated value of 27*P. Note that the power signature of the D/A execution unit roughly corresponds to the sequence “DDADD+DDAaDa”, where each “+” represents the equivalent of a load operation and the lower-case “a” denotes a power consumed by a second add operation which adds contents of an accumulator (first register) to a memory (second register).), wherein a first power signature is associated with performing the Boolean operation by the first computation module (paragraph 0060, Note that in each instance, the value of 27*P is calculated, but the calculation will exhibit a different power signature which varies dependent on execution order; paragraphs 0058-0065); and
a second computation module having a second internal structure, wherein the second internal structure comprises a second static arrangement of routing traces and a second static arrangement of logic gates, the second computation module configured to (paragraph 0031, can also be executed by the same processor, different processors or processor cores, FPGAs or other configurable circuits … the instructions can be executed by a single computer and, in other cases, can be stored and/or executed on a distributed basis, e.g., using one or more servers, web clients, or application-specific devices.):
obtain the public data and the security information asset (paragraph 0056, the depicted operations can be performed for elliptic curve cryptography applications, that is, to multiply the coordinates of a point on an elliptic curve corresponding to a private or public key or simply a designated basis vector for purposes of encryption/decryption/digital-signing/key-agreement of an operand; the digital value “P” in this FIG. represents such coordinates and the numerical operator “A” represents a secret (e.g., typically functioning as a private key that can either be a static entity or an ephemeral entity) that is to serve as a scalar multiplier with the digital value “P” so as to calculate the result “A*P;” as is well known, such a process can be performed in conjunction with elliptic curve processing techniques, e.g., for performing Diffie-Hellman key exchange); and
perform the Boolean [math] operation on the public data and the security information asset to generate a second output (paragraphs 0023-0033, 0058-0065 and 0060, With an alternative character processing order represented in the middle, e.g., the alternative labeled “27*P=2*P+2(2*5)*P+1(5)*P,” the power signature of the D/A execution unit generally corresponds to “D+DDADDaDDAa.” The FIG. also shows a third example where yet another radix character sequence computes a “right-to-left order, i.e., the power signature of the D/A execution unit in this event generally corresponds to “D+DDAaDDADDa.” ), the first output and the second output having an identical value (paragraph 0060, Note that in each instance, the value of 27*P is calculated), wherein a second power signature is associated with performing the Boolean operation by the second computation module, the first power signature being different from the second power signature (paragraph 0060, Note that in each instance, the value of 27*P is calculated, but the calculation will exhibit a different power signature which varies dependent on execution order; paragraphs 0058-0065)
Although Wu discloses the operations are math operations, and the claim recite “Boolean operation”, Boolean operation is a well-known math operation, and are often used in hashing operation, which Wu also discloses (See Wu: paragraph 0090, SHA), it would have been obvious to an ordinary skill in the art before the effective filing date to merely implement a math Boolean operations as one of the Math operations that Wu suggested, because it is merely one of limited number of basic Math operations that an ordinary skill can try with reasonable expectation of success to arrive at the recited “Boolean operation” (see also https://en.wikipedia.org/w/index.php?title=Secure_Hash_Algorithms&oldid=1090879684, SHA And, Xor, Or, Rot, Add (mod 232)).
Wu discloses that each particular function can be implemented using dedicated or hard-wired circuit (paragraph 0031, the term “circuitry” for performing a particular function can include one or more electronic circuits that are either “hard-wired” (or “dedicated”) to performing the stated function (i.e., in some cases without assistance of instructional logic)). The difference between Wu’s discloses and the recited limitations is that Wu does not explicitly state the particular function corresponds to one encryption procedure is implemented by its own module. It would have been obvious to an ordinary skill in the art before the effective filing date of the claimed invention to use each particular math operation that Wu teaches for each power signature in its own dedicated circuitry to result in the claimed limitation because it is merely applying the function Wu teaches having its own dedicated circuitry with each of the functions having the hard-wire math calculation sequence with reasonable expectation of success.
Regarding claim 18, the claim 18 discloses a method claim that is substantially equivalent to the apparatus of claim 1. Therefore, the arguments set forth above with respect to claim 1 are equally applicable to claim 18 and rejected for the same reasons.
Regarding claims 2 and 19, Wu as modified further discloses wherein the Boolean operation comprises combining a plurality of public bits of the public data with a plurality of bits of the security information asset in a bi-linear computation (paragraphs 0023-0033; 0058-0065 and 0057, firmware or hardware logic is scripted to perform this sequence identification “DSDSDDSDSDSDDD” (where “D” means divide and “S” means subtract), and then to invert the sequence, substituting “A” (additions) for “S” (subtractions), to obtain the reverse order sequence “DDDADADADDADAD.” By taking the digital value “P” and subjecting it to this sequence of double-and-add operations, one thereby obtains the value “630*P.” The control logic 191 controls the accumulator 193 (i.e., a first register) to calculate each term of the multiplication operation (e.g., “630*P=3*210*P”, “150*P=5*30*P”, “20*P=2*10*P”, “5*P” and “2*P=2*1*P”) in the desired term-order, and then uses the depicted memory 195 (i.e., a second memory) to add these terms together; the result, irrespective of the radix math applied, is the desired value “A*P”=“807*P” … functions can be performed either using dedicated hardware logic; paragraphs 0058-0065 and 0060, yielding the aggregated value of 27*P. Note that the power signature of the D/A execution unit roughly corresponds to the sequence “DDADD+DDAaDa”, where each “+” represents the equivalent of a load operation and the lower-case “a” denotes a power consumed by a second add operation which adds contents of an accumulator (first register) to a memory (second register).).
Regarding claims 3 and 20, Wu as modified further discloses wherein each bit of the plurality of public bits has a fixed value (paragraphs 0023-0033, 0042, 0058-0065 and 0057, “a radix order or maximum radix value is typically first defined for one or more individual elements of the variable radix vector, per numeral 157; this reference numeral indicates that, in this embodiment, each individual element of the radix vector has a range extending between “N1” and “N2,” e.g., the corresponding element of the radix vector can any possible value within this range (e.g., as seeded from the random number generator 159). For purposes of discussing this embodiment only, the value N1 will be exemplified as having a value of “9” and the value N2 will be exemplified as having a value of “2,” though again, any number range can be used. Note that, optionally, the range can be fixed or hardwired in some embodiments, or imputed from circumstance”).
Regarding claims 6 and 23, Wu as modified further discloses wherein the first internal structure of the first computation module comprises a first plurality of logic gates and the second internal structure of the second computation module comprises a second plurality of logic gates, wherein the first plurality of logic gates includes at least one logic gate that is different from any logic gates in the second plurality of logic gates (paragraphs 031 and 0068, “alternatively, a value corresponding to D (e.g., double, or equivalently, S for square) is stored in a register, with the value being halved, as represented y numerals 311 and 313. A new numerical value obtained by this process is then compared to the value “1,” and if this condition is not satisfied, this new value is then used in an ensuing iteration of the process as a new input value, as is indicated to be a consequence of decision block 315. For each new iteration, a new sequence step is identified for this process until the value that results is equal to “1,” whereupon the sequence is inverted and the process terminates, per block 317. Thus, with “210” as the input value, in ensuing steps, this value is halved (to obtain “105”) is decremented (to obtain “104”), is halved again (to obtain “52”), is halved again (to obtain “26”), is halved again (to obtain “13”), is decremented (to obtain “12”), is halved (to obtain “6”), is halved (to obtain “3”), is decremented and then halved again to obtain “1.” The inverted sequence then becomes DADDADDDAD, as indicated at the bottom of the FIG., which can be used to script steps of an execution unit, as described herein. Note that, as with most every process described in this disclosure, these functions can be optionally implemented in software (e.g., firmware), in hardware (e.g., using logic gates and/or an FPGA), or can be instantiated as a combination of the two”).
Regarding claims 8 and 25, Wu as modified further discloses wherein the public data and the security information asset obtained by the first computation module and the second computation module are masked (paragraphs 0049, 0056 and 0065, the depicted operations can be performed for elliptic curve cryptography applications, that is, to multiply the coordinates of a point on an elliptic curve corresponding to a private or public key or simply a designated basis vector for purposes of encryption/decryption/digital-signing/key-agreement of an operand; the digital value “P” in this FIG. represents such coordinates and the numerical operator “A” represents a secret (e.g., typically functioning as a private key that can either be a static entity or an ephemeral entity) that is to serve as a scalar multiplier with the digital value “P” so as to calculate the result “A*P;” as is well known, such a process can be performed in conjunction with elliptic curve processing techniques, e.g., for performing Diffie-Hellman key exchange… “processes for effectuating these efficiencies will be discussed further below in reference to FIGS. 3A and 6-8. Note that optimal processing efficiency is not necessarily preferred for all embodiments, e.g., in some implementations, a designer might desire to implement added entropy for power signature/timing obfuscation that be obtained via the use of a completely random (i.e., highly-varied) symbol processing order.”).
Regarding claims 9 and 26, Wu as modified further discloses wherein the second internal structure of the second computation module is configured to generate an even number of dummy products during performance of the Boolean operation that are canceled out in the second output generated by the second computation module (paragraphs 0020, 0028 and 0074, “In still other embodiments, dummy operations (e.g., using dedicated dummy circuits or other circuitry) and/or varied character order processing can also be injected into a scripted operational sequence to provide further entropy.”… “padding, in the form of dummy operations, can be used to provide for either a fixed aggregate number of steps or a minimum number of steps. In still other embodiments, some other form of padding can be used. As an example, if a minimum number of “13 steps” was specified, one embodiment might add a dummy operation “x” to the 12 step process only, optionally at a randomly selected position within the processing sequence, e.g., to obtain D+DDAaDDADDax; such a process further obfuscates correlation between operations performed and the circuit's power signature and/or associated timing. In the depicted implementation, the location insertion point of the dummy operation in the sequence can be based on a random number (e.g., per numeral 437), with a sort vector being generated as described by our other incorporated-by-reference patent, U.S. Pat. No. 9,635,011, and used to identify that insertion point. For example, thirteen random numbers can be generated, one being assigned to each of thirteen total steps of the execution sequence, including the dummy operation “x,” with a prime number modulo process being applied and the numeric order of the thirteen remainders then being sorted and used to decide which one of thirteen operational slots will be assigned the dummy operation. In other implementations, the dummy operations can simply be prepended to or added to the end of the calculated processing sequence (e.g., as leading or trailing padding), or inserted in some other manner. To cite a second example, in one embodiment, a fixed number of processing steps is specified, e.g., 18 as an example; in this second example, the first (12-step) processing sequence referenced above might be padded with 6 dummy operations, inserted at random points, e.g., D+DyxDAzaDxyDzADDax, where x, y and z are each different dummy operations randomly selected, with different associated power characteristics, and the second (15-step) processing sequence might be padded with three steps in the same manner to be something like DADxyzADaDADAaDADa, i.e., such that the same number of total operational sequence steps (e.g., 18) are employed, irrespective of selected radix. Clearly, these examples are nonlimiting, and many variations of these techniques will occur to those having ordinary skill in the art. To perform padding of the type indicated, any pertinent start value (e.g., seq.Math.size.sub.fixed/min) which establishes operational parameters is retrieved, per reference numeral 427 and, as indicated by processing block 429, is compared with information 431 representing the calculated operational sequence, to identify the number of dummy steps that are to be generated and inserted. This information is then provided to processing block 433, via flow arrow 434, which identifies the specific dummy operations and sequence insertion points; per arrow 435, control logic then injects these dummy operations into the calculated operational sequence.”).
Regarding claims 10 and 27, Wu as modified further discloses wherein input data used for generating the even number of dummy products includes one or more of bits of public data or bits derived from bits of public data (paragraphs 0023-0033, 0058-0065, 0057 and 0074, “padding, in the form of dummy operations, can be used to provide for either a fixed aggregate number of steps or a minimum number of steps. In still other embodiments, some other form of padding can be used. As an example, if a minimum number of “13 steps” was specified, one embodiment might add a dummy operation “x” to the 12 step process only, optionally at a randomly selected position within the processing sequence, e.g., to obtain D+DDAaDDADDax; such a process further obfuscates correlation between operations performed and the circuit's power signature and/or associated timing. In the depicted implementation, the location insertion point of the dummy operation in the sequence can be based on a random number (e.g., per numeral 437), with a sort vector being generated as described by our other incorporated-by-reference patent, U.S. Pat. No. 9,635,011, and used to identify that insertion point. For example, thirteen random numbers can be generated, one being assigned to each of thirteen total steps of the execution sequence, including the dummy operation “x,” with a prime number modulo process being applied and the numeric order of the thirteen remainders then being sorted and used to decide which one of thirteen operational slots will be assigned the dummy operation. In other implementations, the dummy operations can simply be prepended to or added to the end of the calculated processing sequence (e.g., as leading or trailing padding), or inserted in some other manner. To cite a second example, in one embodiment, a fixed number of processing steps is specified, e.g., 18 as an example; in this second example, the first (12-step) processing sequence referenced above might be padded with 6 dummy operations, inserted at random points, e.g., D+DyxDAzaDxyDzADDax, where x, y and z are each different dummy operations randomly selected, with different associated power characteristics, and the second (15-step) processing sequence might be padded with three steps in the same manner to be something like DADxyzADaDADAaDADa, i.e., such that the same number of total operational sequence steps (e.g., 18) are employed, irrespective of selected radix. Clearly, these examples are nonlimiting, and many variations of these techniques will occur to those having ordinary skill in the art. To perform padding of the type indicated, any pertinent start value (e.g., seq.Math.size.sub.fixed/min) which establishes operational parameters is retrieved, per reference numeral 427 and, as indicated by processing block 429, is compared with information 431 representing the calculated operational sequence, to identify the number of dummy steps that are to be generated and inserted. This information is then provided to processing block 433, via flow arrow 434, which identifies the specific dummy operations and sequence insertion points; per arrow 435, control logic then injects these dummy operations into the calculated operational sequence.”).
Regarding claims 11 and 28, Wu as modified further discloses wherein the first computation module is configured to generate a plurality of products between bits of the public data and bits of the security information asset and generate a plurality of sums of products between pairs of products included in the plurality of products, wherein the plurality of sums of products can be recoded with a dedicated shared random variable (paragraphs 0064 and 0086, “which illustrate examples where a double-and-add execution is used for math functions, FIG. 3 illustrates use of a “square-and-multiply” execution unit. Note that this type of unit is common in cryptographic processing where it is common to mathematically calculate values such as P.sup.A, where P is a cryptographic key or encrypted operand having k bits, and where this digital value will be multiplied by itself “A” times (e.g., P*P*P*P . . . *P*P*P), and is then typically subjected to a modulo operation; the modulo operation itself is typically performed in a power-neutral manner for each operation, and hence, is typically is not of issue in terms of power-signature variability. As indicated in the FIG., for this example, the hypothetical radix vector {6,7,3,2,5} is once again used for purposes of discussion, although here “A” is illustrated as being equal to the base-10 number “71” (i.e., or “2101” in the format dictated by the hypothetical radix vector {6,7,3,2,5}).”).
Regarding claims 12 and 29, Wu as modified further discloses wherein the first computation module comprises a plurality of computation elements configured to generate the first output based on a pre-determined fixed order of operations (paragraphs 0039-0040 and 0057, “this embodiment features a secure hardware processor 143 having an internal double-and-add execution unit 145. The double-and-add execution unit 145 is seen to be part of a hardware multiplication unit 147. In this example, the hardware multiplication unit will, from time-to-time, be provided with two values that are to be multiplied together to obtain a numeric result; in the FIG., these values are represented by the register function “load A,B” (numeral 149); per numeral 151, in an example to be discussed below, the value “A” can be a number such as the hypothetical number “27,” that is to be multiplied against digital value “B,” which can be any number (but in some embodiments, as discussed below, will be a cryptographic key, e.g., a 256-bit key), or any two-dimensional or higher dimensional curve point (x,y, . . . z) on a designated elliptic curve or lattice, where x, y . . . z are each, for example, a 256-bit number in a finite field. As with the techniques generally discussed earlier, a variable radix vector 153 will be provided and used to determine sequencing order of mathematical operations performed by secure processor 143, in order to compute the result of “27” times “B” (which is symbolically represented in the FIG. as “27*B,” per numeral 155). Note that by extension, while illustrated for multiplication and/or exponentiation, these techniques can be applied to other mathematical operations including for example division, logarithmic, and other functions, without limitation.”).
Regarding claims 13 and 30, Wu as modified further discloses wherein the pre-determined order of operations comprises one or more of an order of calculating a plurality of products of bits of the public data with bits of the security information asset or an order of adding the plurality of products (paragraphs 0023-0033, 0058-0065 and 0057, “With a radix vector being defined, and the input multiplier “A” being factored to multi-character value as expressed in the numeral space defined by the radix vector, the control logic 191 of the D/A execution unit 175 is then scripted to control the performance of double-and-add operations, e.g., using an accumulator (first register 193) and a memory (second register 195); these, and other hardware registers, may be used in support of the various processing steps as described herein, with respect to this or other embodiments. The value of each character or symbol of the expression of “A” in the radix numerical space is first calculated—continuing with the example where a digital value (e.g., elliptic curve coordinate “P”) is to be multiplied by “A,” and where “A” has been factored to 3*(210)+5*(30)+2*(10)+1*(5)+2*(1) on the basis of hypothetical radix vector RV={6,7,3,2,6}, the control 191 logic, in one embodiment, can perform a sequence of inverse operations according to predetermined rules in order to identify the double-and-add execution sequence that will be used for multiplication of each term of this expression. For example, the control logic can follow an iterative process where, for example, it identifies value of the “next” character, divides that value by “two” if it is even and subtracts “1” if it is odd, until the value “1” is reached, recording each step in this iterative process in order. For example, applying these principles to this example, the term value “3*210” can be processed to yield a sequence of “3/5” (630 is Divided by 2), “314” (1 is Subtracted), “157” (314 is Divided by 2), “156” (1 is Subtracted), “78” (Divide by 2), “39” (Divide by 2), “38” (1 is Subtracted), “19” (Divide by 2), “18” (1 is Subtracted), “9” (Divide by 2), “8” (1 is Subtracted), “4” (Divide by 2), “2” (Divide by 2) and “1” (Divide by 2); software, firmware or hardware logic is scripted to perform this sequence identification “DSDSDDSDSDSDDD” (where “D” means divide and “S” means subtract), and then to invert the sequence, substituting “A” (additions) for “S” (subtractions), to obtain the reverse order sequence “DDDADADADDADAD.” By taking the digital value “P” and subjecting it to this sequence of double-and-add operations, one thereby obtains the value “630*P.” The control logic 191 controls the accumulator 193 (i.e., a first register) to calculate each term of the multiplication operation (e.g., “630*P=3*210*P”, “150*P=5*30*P”, “20*P=2*10*P”, “5*P” and “2*P=2*1*P”) in the desired term-order, and then uses the depicted memory 195 (i.e., a second memory) to add these terms together; the result, irrespective of the radix math applied, is the desired value “A*P”=“807*P” which can be consumed on-chip or output externally, depending on application, as indicated by numeral 197. Note that as indicated earlier, functions can be performed either using dedicated hardware logic, or general purpose hardware circuits controlled by instructions on physical storage media”).
Regarding claim 14, Wu as modified further discloses wherein a pseudo random seed is expanded into a list that specifies the pre-determined fixed order of operations (paragraphs 0039-0040 and 0057, “this embodiment features a secure hardware processor 143 having an internal double-and-add execution unit 145. The double-and-add execution unit 145 is seen to be part of a hardware multiplication unit 147. In this example, the hardware multiplication unit will, from time-to-time, be provided with two values that are to be multiplied together to obtain a numeric result; in the FIG., these values are represented by the register function “load A,B” (numeral 149); per numeral 151, in an example to be discussed below, the value “A” can be a number such as the hypothetical number “27,” that is to be multiplied against digital value “B,” which can be any number (but in some embodiments, as discussed below, will be a cryptographic key, e.g., a 256-bit key), or any two-dimensional or higher dimensional curve point (x,y, . . . z) on a designated elliptic curve or lattice, where x, y . . . z are each, for example, a 256-bit number in a finite field. As with the techniques generally discussed earlier, a variable radix vector 153 will be provided and used to determine sequencing order of mathematical operations performed by secure processor 143, in order to compute the result of “27” times “B” (which is symbolically represented in the FIG. as “27*B,” per numeral 155). Note that by extension, while illustrated for multiplication and/or exponentiation, these techniques can be applied to other mathematical operations including for example division, logarithmic, and other functions, without limitation.”).
Regarding claim 15, Wu as modified further discloses wherein the plurality of computation elements comprises single-bit multiplication elements, wherein the single-bit multiplication elements comprise one or more of NAND gates or AND gates (paragraphs 0027, 0068 and 0086, “Per reference numeral 303, the process first identifies an input value (which in this case is initialized using a hypothetical value of “210”). As was exemplified earlier, this value is then subjected to a process where it is identified as odd or even (e.g., per decision block 305) and where, if the value is odd, “1” is subtracted from this value and a corresponding sequence step representing A (e.g., add or equivalently, M for multiply) is stored in a register, per numerals 307 and 309; alternatively, a value corresponding to D (e.g., double, or equivalently, S for square) is stored in a register, with the value being halved, as represented y numerals 311 and 313. A new numerical value obtained by this process is then compared to the value “1,” and if this condition is not satisfied, this new value is then used in an ensuing iteration of the process as a new input value, as is indicated to be a consequence of decision block 315. For each new iteration, a new sequence step is identified for this process until the value that results is equal to “1,” whereupon the sequence is inverted and the process terminates, per block 317. Thus, with “210” as the input value, in ensuing steps, this value is halved (to obtain “105”) is decremented (to obtain “104”), is halved again (to obtain “52”), is halved again (to obtain “26”), is halved again (to obtain “13”), is decremented (to obtain “12”), is halved (to obtain “6”), is halved (to obtain “3”), is decremented and then halved again to obtain “1.” The inverted sequence then becomes DADDADDDAD, as indicated at the bottom of the FIG., which can be used to script steps of an execution unit, as described herein. Note that, as with most every process described in this disclosure, these functions can be optionally implemented in software (e.g., firmware), in hardware (e.g., using logic gates and/or an FPGA), or can be instantiated as a combination of the two.”).
Regarding claim 16, Wu as modified further discloses wherein the plurality of computation elements comprises XOR gates (paragraphs 0027, 0068 and 0086, “Per reference numeral 303, the process first identifies an input value (which in this case is initialized using a hypothetical value of “210”). As was exemplified earlier, this value is then subjected to a process where it is identified as odd or even (e.g., per decision block 305) and where, if the value is odd, “1” is subtracted from this value and a corresponding sequence step representing A (e.g., add or equivalently, M for multiply) is stored in a register, per numerals 307 and 309; alternatively, a value corresponding to D (e.g., double, or equivalently, S for square) is stored in a register, with the value being halved, as represented y numerals 311 and 313. A new numerical value obtained by this process is then compared to the value “1,” and if this condition is not satisfied, this new value is then used in an ensuing iteration of the process as a new input value, as is indicated to be a consequence of decision block 315. For each new iteration, a new sequence step is identified for this process until the value that results is equal to “1,” whereupon the sequence is inverted and the process terminates, per block 317. Thus, with “210” as the input value, in ensuing steps, this value is halved (to obtain “105”) is decremented (to obtain “104”), is halved again (to obtain “52”), is halved again (to obtain “26”), is halved again (to obtain “13”), is decremented (to obtain “12”), is halved (to obtain “6”), is halved (to obtain “3”), is decremented and then halved again to obtain “1.” The inverted sequence then becomes DADDADDDAD, as indicated at the bottom of the FIG., which can be used to script steps of an execution unit, as described herein. Note that, as with most every process described in this disclosure, these functions can be optionally implemented in software (e.g., firmware), in hardware (e.g., using logic gates and/or an FPGA), or can be instantiated as a combination of the two.”).
Regarding claim 17, Wu as modified further discloses further comprising an additional processor coupled to the memory, wherein the additional processor comprises a third computation module having a third internal structure, the third computation module (paragraph 0031, circuit processor, circuitry, one or more electronic circuits that are either “hard-wired” (or “dedicated”) to performing the stated function (i.e., in some cases without assistance of instructional logic), and the term can also include a microcontroller, microprocessor, FPGA or other form of processor which is general in design but which runs software or firmware (e.g., instructional logic) that causes or configures general circuitry (e.g., configures or directs a circuit processor) to perform the particular function)) configured to:
obtain the public data and the security information asset (paragraph 0056, the depicted operations can be performed for elliptic curve cryptography applications, that is, to multiply the coordinates of a point on an elliptic curve corresponding to a private or public key or simply a designated basis vector for purposes of encryption/decryption/digital-signing/key-agreement of an operand; the digital value “P” in this FIG. represents such coordinates and the numerical operator “A” represents a secret (e.g., typically functioning as a private key that can either be a static entity or an ephemeral entity) that is to serve as a scalar multiplier with the digital value “P” so as to calculate the result “A*P;” as is well known, such a process can be performed in conjunction with elliptic curve processing techniques, e.g., for performing Diffie-Hellman key exchange); and
perform the Boolean operation on the public data and the security information asset to generate a third output, the third output having an identical value to the first output and the second output (paragraphs 0023-0033, 0058-0065 and 0060, With an alternative character processing order represented in the middle, e.g., the alternative labeled “27*P=2*P+2(2*5)*P+1(5)*P,” the power signature of the D/A execution unit generally corresponds to “D+DDADDaDDAa.” The FIG. also shows a third example where yet another radix character sequence computes a “right-to-left order, i.e., the power signature of the D/A execution unit in this event generally corresponds to “D+DDAaDDADDa.” ), the first output and the second output having an identical value, (paragraph 0060, Note that in each instance, the value of 27*P is calculated, but the calculation will exhibit a different power signature which varies dependent on execution order; paragraphs 0058-0065), wherein the third internal structure comprises a third static arrangement of routing traces and a third static arrangement of logic gates, the first internal structure configured to perform the Boolean operation, the third internal structure being different from the first internal structure and the second internal structure (paragraphs 0023-0033, 0058-0065 and 0060, With an alternative character processing order represented in the middle, e.g., the alternative labeled “27*P=2*P+2(2*5)*P+1(5)*P,” the power signature of the D/A execution unit generally corresponds to “D+DDADDaDDAa.” The FIG. also shows a third example where yet another radix character sequence computes a “right-to-left order, i.e., the power signature of the D/A execution unit in this event generally corresponds to “D+DDAaDDADDa.”). The same motivation to modify Wu, as applied in claim 1 above, applies here.
Regarding claims 31 and 33, Wu as modified further discloses wherein: the first static arrangement of routing traces comprises a first mapping between bits of the security information asset and the first static arrangement of logic gates (paragraphs 0036, 0044 and 0057-0060); and the second static arrangement of routing traces comprises a second mapping between bits of the security information asset and the second static arrangement of logic gates, the second mapping being different from the first mapping (paragraphs 0036, 0044 and 0057-0060, “Because the execution unit has different instantaneous power consumption depending on whether it is performing shifting (e.g., loading/resetting), doubling, or adding values together, squaring, multiplying, etc., each of the different operations referenced above causes the execution unit to exhibit a different power profile relative to time (e.g., microprocessor clock cycles). As should be apparent, there are many ways (not limited to those shown) in which the value “5x” can be computed, even with operations restricted to simply doubling an input (x) and adding an input (x) to an accumulated result; there also exist many ways (not limited to those discussed) that will produce x.sup.5 as an accumulated result. Because the power consumption of the execution is different for each type of operation, each different sequence of processing steps exhibits a different power consumption profile, that is, even though each of these sequences will invariably yield the same ultimate value (5x or x.sup.5) as an output.”).
Allowable Subject Matter
Claims 32 and 34 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and rejection(s) under 35 U.S.C. 112(a) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/TRANG T DOAN/Primary Examiner, Art Unit 2431
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