Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Regarding claim 1, the claim states: An apparatus, comprising: a co-operative scheduler of a task of an application; a timer circuit to detect a task of the application executing longer than an expected execution time for the task without interrupting execution of the task; and a record circuit to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task.
Under Prong 1, the limitation “detect a task of the application executing longer than an expected execution time for the task without interrupting execution of the task”, “record that the task of the application has been executing longer than the expected execution time for the task” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper; as a person with the aid of a computer can time the behavior of an application, and record that the task had been completed. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The additional element “a co-operative scheduler of a task of an application; a timer circuit and a record circuit” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a co-operative scheduler of a task of an application; a timer circuit and a record circuit” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more.
Regarding claim 2, The apparatus as claimed in claim 1, comprising a correction circuit to correct the expected execution time by adding a correction factor based on the time the task executes after an overrun has been detected.
The apparatus of claim 2, which recites the abstract idea of “correct the expected execution time by adding a correction factor based on the time the task executes after an overrun has been detected” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper; as a person with the aid of a computer can time the behavior of an application, and record that the task had been completed. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The additional element “a correction circuit” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a correction circuit” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more.
Regarding claim 3, The apparatus as claimed in claim 1, wherein the timer circuit is to capture a run execution time of the task.
The apparatus of claim 3, which recites the abstract idea of “capture a run execution time of the task” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper; as a person with the aid of a computer can time the behavior of an application, and record that the task had been completed. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The additional element “a timer circuit” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a timer circuit” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more.
Regarding claim 4, The apparatus as claimed in claim 1, wherein the timer circuit is to increment a timer counter as the task executes and compare the timer counter and the expected execution time for the task, and generate a detection output when the timer counter and the expected execution time are equal, the detection output recorded by the record circuit so as to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task.
The apparatus of claim 4, which recites the abstract idea of “increment a timer counter as the task executes and compare the timer counter and the expected execution time for the task”, “generate a detection output when the timer counter and the expected execution time are equal” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper; as a person with the aid of a computer can time the behavior of an application, and record that the task had been completed. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The additional element “a timer circuit” and “a record circuit” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g). Further “record that the task of the application has been executing longer than the expected execution time for the task” amounts to insignificant extra-solution activity of data storing, see MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a timer circuit” and “a record circuit” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more. Further “record that the task of the application has been executing longer than the expected execution time for the task” amounts to insignificant extra-solution activity that WURC of data storing, see MPEP 2106.05(d) - iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Regarding claim 5, The apparatus as claimed in claim 1, wherein the timer circuit is to decrement a timer counter from the expected execution time toward zero (0) as the task executes and generate a detection output when the timer counter equals zero (0), the detection output recorded by the record circuit so as to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task.
The apparatus of claim 5, which recites the abstract idea of “wherein the timer circuit is to decrement a timer counter from the expected execution time toward zero (0) as the task executes and generate a detection output” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper; as a person with the aid of a computer can time the behavior of an application, and record that the task had been completed. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The additional element “a timer circuit” and “a record circuit” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g). Further “record that the task of the application has been executing longer than the expected execution time for the task” amounts to insignificant extra-solution activity of data storing, see MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a timer circuit” and “a record circuit” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more. Further “record that the task of the application has been executing longer than the expected execution time for the task” amounts to insignificant extra-solution activity that WURC of data storing, see MPEP 2106.05(d) - iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
6. Regarding claim 6, The apparatus as claimed in claim 1, wherein the timer circuit comprises: a time base generator; a timer; a timer counter register to store timer counter values as the task executes; an expected execution time register to store an expected execution time for the task; and wherein the timer circuit is to generate a detection output based on a timer counter value stored in the timer counter register, the detection output recorded by the record circuit so as to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task.
The apparatus of claim 6, which recites the abstract idea of “storing an expected execution time register to store an expected execution time for the task; and wherein the timer circuit is to generate a detection output based on a timer counter value stored in the timer counter register, the detection output recorded by the record circuit so as to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task “ as drafted, Under Prong 2, are additional elements that amounts to insignificant extra-solution activity of data storing, see MPEP 2106.05(g). Further, The additional element “a time base generator; a timer; a timer counter register” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the additional element “storing an expected execution time register to store an expected execution time for the task; and wherein the timer circuit is to generate a detection output based on a timer counter value stored in the timer counter register, the detection output recorded by the record circuit so as to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task “ as drafted, amounts to insignificant extra-solution activity that WURC of data storing, see MPEP 2106.05(d) - iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. Further the additional element of “a time base generator; a timer; a timer counter register” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more.
7. Regarding claim 7, The apparatus as claimed in claim 1, comprising an application programming interface to provide the expected execution time to the timer circuit.
The apparatus of claim 7, the additional element of “an application programming interface” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “an application programming interface” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more.
8. Regarding claim 8, The apparatus as claimed in claim 2, comprising an application programming interface to allow a user to provide a corrected expected execution time to the timer circuit.
The apparatus of claim 8, the additional element “an application programming interface” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “an application programming interface” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more.
9. Regarding claim 9, The apparatus as claimed in claim 1, wherein the record circuit is to capture a pulse signal from the timer circuit, wherein the pulse signal output corresponds to a detection of a task overrun.
The apparatus of claim 9, which recites the abstract idea of “capture a pulse signal from the timer circuit” and “detection of a task overrun” as drafted amount to additional elements of insignificant extra-solution activity using “record circuit” which is recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “capture a pulse signal from the timer circuit” and “detection of a task overrun” as drafted amount to additional elements of data gathering that is WURC using “record circuit” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g); see also MPEP 2106.05(d) - i. Receiving or transmitting data over a network, e.g., using the Internet to gather data. The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more.
10. Regarding claim 10, The apparatus as claimed in claim 8, wherein the timer circuit is to capture a run execution time of the task, and comprising a correction circuit to calculate a correction factor based on the expected execution time and the run execution time.
The apparatus of claim 9, which recites the abstract idea of “calculate a correction factor based on the expected execution time and the run execution time”, as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper; as a person with the aid of a computer can time the behavior of an application, and record that the task had been completed. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The additional element of “capture a run execution time of the task” using “timer circuit” and “correction circuit” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(d), does nothing more than add insignificant extra solution activity to the judicial exception of apply it. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “capture a run execution time of the task” using “timer circuit” and “correction circuit” amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(g). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101 as the limitations individually or when viewed as a whole does not amount to a practical application of the abstract idea or amount to significantly more.
Regarding claims 11-21, they are rejected with the same rationale as applied to claims 1-10, and
therefore, are rejected under U.S.C 101 as well.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-15, 18 – 19, 21, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20230102089 A1 (Bellubbi et. al).
Regarding claim 1, Bellubbi teaches, An apparatus, comprising: a co-operative scheduler of a task of an application; a timer circuit to detect a task of the application executing longer than an expected execution time for the task without interrupting execution of the task ; and a record circuit to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task (paragraph 69, 249, 250, 315, a runtime log that stores the runtime of the timer which kept the runtime, with a detection that an error had occurred, including running for an extended period, see paragraph 50, 267-270, 275-276, 281-283, 294, 304-319, 335, 336, and 349-350).
Regarding claim 2, Bellubbi teaches, The apparatus as claimed in claim 1, comprising a correction circuit to correct the expected execution time by adding a correction factor based on the time the task executes after an overrun has been detected (paragraph 281-283, 294, 304-319, 333, a correction circuit that modifies the scheduler based on the tasks overrunning).
Regarding claim 3, Bellubbi teaches, The apparatus as claimed in claim 1, wherein the timer circuit is to capture a run execution time of the task (a timer circuit that records the runtime of a task, see paragraph 69, 249, 250, 281-283, 294, 304-319, 340, 350).
Regarding claim 4, Bellubbi teaches, The apparatus as claimed in claim 1, wherein the timer circuit is to increment a timer counter as the task executes and compare the timer counter and the expected execution time for the task, and generate a detection output when the timer counter and the expected execution time are equal, the detection output recorded by the record circuit so as to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task (paragraph 69, 249, 250, 315, a runtime log that stores the runtime of the timer which kept the runtime, with a detection that an error had occurred, including running for an extended period, see paragraph 294, 335, 336, and 350, where there is an expected runtime of said task, paragraph 269, 280, 296).
Regarding claim 5, Bellubbi teaches, The apparatus as claimed in claim 1, wherein the timer circuit is to decrement a timer counter from the expected execution time toward zero (0) as the task executes and generate a detection output when the timer counter equals zero (0), the detection output recorded by the record circuit so as to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task (paragraph 271, 276, 278, 280, a timestamp that determines the runtime, recording expected time, with the difference between the expected time and current time is determined. Further, paragraph 69, 249, 250, 315, a runtime log that stores the runtime of the timer which kept the runtime, with a detection that an error had occurred, including running for an extended period, see paragraph 294, 335, 336, and 350, where there is an expected runtime of said task, paragraph 269, 280, 296) (see also 281-283, 294, 304-319).
Regarding claim 6, Bellubbi teaches, The apparatus as claimed in claim 1, wherein the timer circuit comprises: a time base generator; a timer; a timer counter register to store timer counter values as the task executes; an expected execution time register to store an expected execution time for the task (paragraph 282, time based timestamps used by the timer, that gets generated, which stores in the runtime log, paragraph 249); and wherein the timer circuit is to generate a detection output based on a timer counter value stored in the timer counter register, the detection output recorded by the record circuit so as to record that the task of the application has been detected by the timer circuit executing longer than the expected execution time for the task (paragraph 69, 249, 250, 315, a runtime log that stores the runtime of the timer which kept the runtime, with a detection that an error had occurred, including running for an extended period, see paragraph 294, 335, 336, and 350, where there is an expected runtime of said task, paragraph 269, 280, 296).
Regarding claim 9, Bellubbi teaches, The apparatus as claimed in claim 1, wherein the record circuit is to capture a pulse signal from the timer circuit, wherein the pulse signal output corresponds to a detection of a task overrun (paragraph 271, 276, 278, 280, a timestamp that determines the runtime, recording expected time, with the difference between the expected time and current time is determined. Further, paragraph 69, 249, 250, 315, a runtime log that stores the runtime of the timer which kept the runtime, with a detection that an error had occurred, including running for an extended period, see paragraph 294, 335, 336, and 350, where there is an expected runtime of said task, paragraph 269, 280, 296).
Regarding claim 10, Bellubbi teaches, The apparatus as claimed in claim 8, wherein the timer circuit is to capture a run execution time of the task, and comprising a correction circuit to calculate a correction factor based on the expected execution time and the run execution time (a timer circuit that records the runtime of a task, see paragraph 69, 249, 250, 315, 340, 350, further, paragraph 311, 333, a correction circuit that modifies the scheduler based on the tasks overrunning).
Regarding claims 11-15, 18 – 19, 21, they are rejected with the same rationale as applied to claims 1-6, 9-10, and therefore, are rejected under U.S.C 102(a)(1) as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 8, 16, 17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230102089 A1 (Bellubbi et. al) as applied to claim 1-6, 9-15, 18 – 19, 21 above, and further in view of US 20080049254 A1 (Phan et. al).
Regarding claim 7, Bellubbi recites, The apparatus as claimed in claim 1.
However, Bellubbi does not recite, comprising an application programming interface to provide the expected execution time to the timer circuit.
Phan recites, comprising an application programming interface to provide the expected execution time to the timer circuit (paragraph 31, the user can submit a computational time to the scheduler).
Therefore, it would have been obvious before the effective filing date of the claimed invention
to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bellubbi with the API system to allow users to define the runtime as taught by Phan, as it would allow the user to better execute a workload in a timely manner without causing errors.
Regarding claim 8, Bellubbi recites, The apparatus as claimed in claim 2.
However, Bellubbi does not recite, comprising an application programming interface to allow a user to provide a corrected expected execution time to the timer circuit.
Phan recites, comprising an application programming interface to allow a user to provide a corrected expected execution time to the timer circuit (paragraph 31, the user can submit a computational time to the scheduler).
Therefore, it would have been obvious before the effective filing date of the claimed invention
to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bellubbi with the API system to allow users to define the runtime as taught by Phan, as it would allow the user to better execute a workload in a timely manner without causing errors.
Regarding claims 16, 17, and 20, they are rejected with the same rationale as applied to claims 7 and 8, and therefore, are rejected under U.S.C 103 as well.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTIAN BAKHIT whose telephone number is (571)272-4314. The examiner can normally be reached Monday-Thursday: 6:30-5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached at (571)272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTIAN BAKHIT whose telephone number is (571)272-4314. The examiner can normally be reached Monday-Thursday: 6:30-5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEWIS BULLOCK can be reached at (571) 272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTIAN M BAKHIT/Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199
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