DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to communication filed 12/30/2025.
The instant application having application No. 18/470,602 filed on September 20, 2023, presents claims 1-20 for examination. The instant application claims priority to the Indian application having application No. IN202311051957 filed on August 2, 2023.
Status of the Claims
Claims 1, 3-5, 9, 11, 12, 16, and 18 have been amended, claims 1-20 are currently pending in the application.
Response to Amendment
(A). Regarding claim objections: Applicant's amendment to claims appropriately addressed the objections to claim 5, the objections are withdrawn.
(B). Regarding 35 U.S.C. § 101 rejection: The amended claims overcome the 101 abstract idea rejections which are withdrawn.
(C). Regarding art rejection: In regards to pending claims Applicant’s arguments are not persuasive; further, Applicant's amendments necessitated new grounds of rejections presented in the following art rejection.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 1-8 and 16-20 are objected to because of the following informalities:
Claim 1, line 19, at end, missing “;”. Claim 16 has the same issue. Dependent claims 2-8 and 17-20 are objected to for the same reason because they depend from their respective independent claims.
Claim 1, line 7, “comparingthe”, suggestion: -comparing the-. Claims 2-8 are objected for the same reason because they depend from claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-10, 15-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Suryanarayana et al. (US 20200326930 A1, hereinafter “Suryanarayana” cited from IDS filed on 9/20/2023) in view of Mallur et al. (US 20140082160 A1, hereinafter “Mallur”), Fontenot et al. (US 20140279985 A1, hereinafter “Fontenot”) and YANG et al. (CN 112118246 A, hereinafter “YANG”, please refer to the attached English translation copy).
With respect to claim 1 (Currently Amended), Suryanarayana discloses A method comprising:
determining, by a processor, a first version of a system firmware of an information handling system for update (e.g. para [0041], “… At block 605, the structure of the flash memory device and firmware components along with its versions using the implemented MFFS may be determined. …”):
retrieving first binaries of the first version of the system firmware of the information handling system for update and second binaries of a second version of the system firmware (e.g. para [0043], “… the firmware update manager can compare the contents of the existing firmware components in the flash memory device with the contents of the updated firmware images.” This paragraph indicates that the existing firmware components in the flash memory device (reads on the first version of the system firmware) and the updated firmware images (read on second version of the system firmware) are retrieved);
comparing the first binaries of the first version of the system firmware with the second binaries of the second version of the system firmware (e.g. para [0043], “… the firmware update manager can compare the contents of the existing firmware components in the flash memory device with the contents of the updated firmware images.”);
identifying modified modules based on the comparing of the first binaries of the first version of the system firmware and the second binaries of the second version of the system firmware (e.g. para [0045], “At block 625, the update package is generated based on the delta payload map. The update package may be a combination of generated firmware images. Each firmware image may include the deltas or the updates to at least one of the firmware files in the firmware component.” Wherein the deltas or the updates to at least one of the firmware files indicates that modified modules (files) are identified); and
bundling the modified modules and [a module with a hash value and a signature] including [write only] offset definitions based on deltas in the modified modules as a binary file (e.g. para [0047], “Generating the update package includes generating the MFFST of the update package. ….. Finally, the structure may include information regarding the firmware volumes, such as the number of firmware update files and its corresponding firmware update file header.” Wherein MFFST suggests based on deltas in the modified modules, see, e.g. para [0022], “… A modular flash file structure (MFFS) allows for an update package to contain revisions for a specific firmware file or a portion thereof. In addition, additional headers and attributes included in the MFFS dynamically identifies size and location of a revision. …” also para [0043]. para [0048], “… The location may include an address and/or an offset of the firmware image, the firmware volume, or the firmware update file.”).
generating a payload package based on the binary file (e.g. para [0044], “At block 620, a delta payload map may be generated based on the determined deltas between the existing firmware component and the updated firmware image. …” para [0045], “At block 625, the update package is generated based on the delta payload map. …” wherein the update package reads on a payload package): and
publishing the payload package for download (e.g. para [0049], “… Alternatively, a user of the information handling system may download the update package from an original equipment provider or the like. …” this paragraph indicates that the update package (read on payload package) is published for download).
updating the first version of the system firmware based on the offset definitions (e.g. para [0049], “At block 630, updates the existing firmware components may be initiated using the update package. …” para [0047-0048] disclose that the update package includes offset definitions)
Suryanarayana does not appear to explicitly disclose
(bundling the modified modules and) a module with a hash value and a signature including [write only] (offset definitions based on deltas in the modified modules as a binary file);
(generating a payload package based on the binary file,) wherein the payload package includes the module with the hash value and the signature including the write only offset definitions;
in response to determining that the payload package includes a driver that is split across at least two modules, retrieving information of location of data in the two modules from a database included in the payload package.
However, in analogous art, Mallur discloses
in response to determining that the payload package includes a driver that is split across at least two modules, retrieving information of location of data in the two modules from a database included in the payload package (e.g. para [0099], “… Both drivers associated with one or more classes of hardware platforms identified in the device driver configuration file, and common drivers associated with two or more hardware platforms identified in the device driver configuration file, can be imported into the driver-store. …” wherein common drivers associated with two or more hardware platforms read on a driver that is split across at least two modules; drivers can be imported into the driver-store indicates that information of location of data in the two or more platforms can be retrieved from the device driver configuration file, the information can be included in the payload package which is taught by primary reference Suryanarayana. The combination of Suryanarayana and Mallur renders the claim feature obvious).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the invention of Suryanarayana with the invention of Mallur because it provides techniques for efficiently deploying software applications, drivers, updates (e.g., QFEs), and feature components (e.g., Microsoft feature components) to client devices. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of providing techniques for efficiently deploying software applications, drivers, updates (e.g., QFEs), and feature components (e.g., Microsoft feature components) to client devices as suggested by Mallur (see para [0002, 0029]).
Suryanarayana as modified by Mallur does not appear to explicitly disclose
(bundling the modified modules and) a module with a hash value and a signature including [write only] (offset definitions based on deltas in the modified modules as a binary file);
(generating a payload package based on the binary file,) wherein the payload package includes the module with the hash value and the signature including the write only offset definitions;
However, in analogous art, Fontenot discloses
a module with a hash value and a signature (e.g. para [0030], “… Program modification module 140 also includes computer program 120's program identifier in hash update table entry information 170, which is stored with the updated hash value
and the digital signature (see FIG. 2 and corresponding text for further details).”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the invention of Fontenot because it provides techniques with an integrity measurement module to optimize computer program loading performance within a computer system's trusted computing environment. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of providing techniques with an integrity measurement module to optimize computer program loading performance within a computer system's trusted computing environment as suggested by Fontenot (see para [0001-0005]).
Suryanarayana as modified by Mallur and Fontenot does not appear to explicitly disclose
wherein the payload package includes (the module with the hash value and the signature) including the write only offset definitions;
However, this is taught in analogous art, YANG (e.g. Abstract, “… the WP# of the hardware control flash memory prohibits writing signal, ensuring the data in the protection area after the system initialization is written only once, cannot be modified; the casting section page storage protection mechanism for the flash memory space set by upper and lower limit address for " casting " type write protection, that is, once shaping, writing one time. …, data write-once, multiple reading, ensuring the integrity of the upper chain data, not being deleted.” Wherein data in protection area is written only once reads on write only, the memory space set by upper and lower limit address reads on the offer definition. Suryanarayana teaches the payload package; the combination of Suryanarayana and YANG renders the claim feature obvious.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the invention of YANG because it provides techniques for efficiency reading and writing speed and ensuring the integrity of the upper chain data, not being deleted. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of providing techniques for efficiency reading and writing
speed and ensuring the integrity of the upper chain data, not being deleted as suggested by YANG (see Abstract).
With respect to claim 2, Suryanarayana discloses wherein the offset definitions are in a segment offset table (e.g. para [0035], “… MFF ST 555 may also include a number, a location, and a size each of the firmware volumes in each firmware image. The location may include an offset and an address of each of the firmware volumes, the modified data, and the firmware update files. …” wherein MFFST reads on a segment offset table).
With respect to claim 8, Suryanarayana discloses further comprising interpolating the offset definitions of the modified modules with platform offset definitions which results in generating a new flash offset map. (e.g. Fig. 5A, para [0038], “… Delta payload map 515 may include a relocation index, a size, an address and/or an offset of the firmware component, the firmware volume, the firmware file, a page, a block, code and/or data. Firmware update manager 505 may determine the name, version, address, size and/or offset of the firmware component and/or firmware file to be updated. Firmware update manager 505 may flash the identified firmware component and/or firmware file with the modified data using delta payload map 515,.. …” Fig. 5A shows Flash 170 that includes Platform Data Area which suggest platform offset definitions, the delta payload map 515 reads on a new flash offset map and indicates that offset definitions of the modified modules are interpolated with platform offset definitions).
With respect to claim 9 (Currently Amended), it is directed to an information handling system to implement the method disclosed in claim 1, please see the rejections directed to claim 1 above which also cover the limitations recited in claim 9. Note that, Suryanarayana discloses An information handling system, comprising:
a processor; and
a memory storing instructions that when executed cause the processor to perform operations including (e.g. Fig. 1):
With respect to claim 10, it recites same features as claim 2, and is rejected for the same reason.
With respect to claim 15, it recites same features as claim 8, and is rejected for the same reason.
With respect to claim 16 (Currently Amended), it is directed to a non-transitory computer-readable medium to implement the method disclosed in claim 1, please see the rejections directed to claim 1 above which also cover the limitations recited in claim 16. Note that, Suryanarayana discloses A non-transitory computer-readable medium to store instructions that are executable to perform operations comprising (e.g. Fig. 1):
With respect to claim 17, it recites same features as claim 2, and is rejected for the same reason.
With respect to claim 20, it recites same features as claim 8, and is rejected for the same reason.
Claims 3, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Suryanarayana in view of Mallur, Fontenot and Yang as applied to claims 1, 8, and 16 respectively, in further view of MUECK (US 20240129194 A1, hereinafter “MUECK”).
With respect to claim 3 (Previously Presented), Suryanarayana as modified by Mallur, Fontenot and Yang discloses The method of claim 1, but does not appear to explicitly disclose wherein a reserved space is included at an end portion of each module. However, this is taught in analogous art, MUECK (e.g. Fig. 6. para [0104], “… The RAP container formats 600a and 600b include, header IE 602, a security information IE 604, a code IE 606, a manufacturer information IE 608 (also referred to as “Installation Code section 608” or the like), an initial profile section IE 610, and a reserved section 612. …”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the invention of MUECK because it provides techniques for enabling a unified method for the validation of the ETSI SW reconfiguration framework. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of providing techniques for enabling a unified method for the validation of the ETSI SW reconfiguration framework as suggested by MUECK (see para [0016]).
With respect to claim 11 (Previously Presented), it recites same features as claim 3, and is rejected for the same reason.
With respect to claim 18 (Previously Presented), it recites same features as claim 3, and is rejected for the same reason.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Suryanarayana in view of Mallur, Fontenot, Yang and MUECK as applied to claim 3, in further view of Wilson (US 20080177799 A1, hereinafter “Wilson”).
With respect to claim 4 (Previously Presented), Suryanarayana as modified by Mallur, Fontenot, Yang and MUECK discloses The method of claim 3, but does not appear to explicitly disclose wherein the hash value is calculated excluding the reserved space.. However, this is taught in analogous art, Wilson (e.g. para [0022], “… A predefined subset of document elements, which may be expected to be undeterminable from a printed version of a document, are excluded from the initial calculation of an integrity verification code (IVC) while the document is in electronic form. For example, metadata, tabs, spaces, special characters, formatting commands, and the like, may be excluded from a hash value calculation. ,. …” wherein spaces read on the reserved space).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the invention of Wilson because it provides techniques for excluding undeterminable elements from calculating hash values. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of providing techniques for excluding undeterminable elements from calculating hash values as suggested by Wilson (see para [0022]).
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Suryanarayana in view of Mallur, Fontenot and Yang as applied to claims 1 and 9 respectively, in further view of Bielski (US 20090064122 A1, hereinafter “Bielski”).
With respect to claim 5 (Currently Amended), Suryanarayana as modified by Mallur, Fontenot, Yang discloses The method of claim 1, but does not appear to explicitly disclose wherein the hash value is calculated based on a set of drivers. However, this is taught in analogous art, Bielski (e.g. para [0017], “Each of the computers (108, 112, 104, 110, and 126) of FIG. 1 have installed upon them one or more drivers and each are capable of evaluating computer driver update compliance in accordance with the present invention by applying a hashing algorithm to the contents of a driver repository, yielding a first hash value, the driver repository containing installed drivers for a computer; …”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the invention of Bielski because it provides techniques for evaluating computer driver update compliance. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of providing techniques for evaluating computer driver update compliance as suggested by Bielski (see para [0004-0006]).
With respect to claim 12 (Currently Amended), it recites same features as claim 5, and is rejected for the same reason.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Suryanarayana in view of Mallur, Fontenot and Yang as applied to claims 1 and 9 respectively, in further view of Hiltgen et al. (US 20130055247 A1, hereinafter “Hiltgen”).
With respect to claim 6, Suryanarayana as modified by Mallur, Fontenot and Yang discloses The method of claim 1, but does not appear to explicitly disclose further comprising collecting information associated with drivers that are split into at least two modules. However, this is taught in analogous art, Hiltgen (e.g. para [0044], “… The virtualization layer 306 has two instances of virtual machines 308a, 308b, each of which runs a separate OS. Each OS uses drivers that work with virtual hardware ("vh 1") presented by the respective virtual machines 308a, 308b.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the invention of Hiltgen because it provides techniques for maintaining proper dependencies and compatibility limitations between components when patching or upgrading any component. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of providing techniques for maintaining proper dependencies and compatibility limitations between components when patching or upgrading any component as suggested by Hiltgen (see para [0006-0007]).
With respect to claim 13, it recites same features as claim 6, and is rejected for the same reason.
Claims 7, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Suryanarayana in view of Mallur, Fontenot and Yang as applied to claims 1, 9, and 16 respectively, in further view of Bassi (US 20170308473 A1, hereinafter “Bassi”).
With respect to claim 7, Suryanarayana as modified by Mallur, Fontenot and Yang discloses The method of claim 1, but does not appear to explicitly disclose further comprising generating a payload offset table with a dynamic link of an overflow offset. However, this is taught in analogous art, Bassi (e.g. para [0069], “Upon receiving a first-in-time write command, the driver 404 may dynamically generate a search tree (e.g., self-balancing search tree 410) and a global linked list (e.g., global linked list 600 as shown in FIG. 6A). The global linked list may map where blocks are stored in the virtual cache 406 and/or the virtual overflow disk 408. … The record for the block may include a pointer to the block's location in the virtual cache 406 if stored in the virtual cache 406, an offset to the block's location in the virtual overflow disk 408 if stored in the virtual overflow disk 408, the block size for the block, the block's position in a least recently used list, a pointer back to the tree 410, etc.” wherein the global linked list 600 of Fig. 6A reads on a payload offset table, dynamically generated search tree reads on a dynamic link of an overflow offset).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the invention of Bassi because it enhances the user experience by managing virtual memory so as to reduce boot time, increase available virtual memory. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of enhancing the user experience by managing virtual memory so as to reduce boot time, increase available virtual memory, as suggested by Bassi (see para [0005]).
With respect to claim 14, it recites same features as claim 7, and is rejected for the same reason.
With respect to claim 19, it recites same features as claim 7, and is rejected for the same reason.
Response to Arguments
Applicant's arguments with respect art rejections filed 12/30/2025 have been fully considered and are moot upon new ground of rejections made in the office action above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Zengpu Wei whose telephone number is 571-270-1302. The examiner can normally be reached on Monday to Friday from 8:00AM to 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets, can be reached on 571-272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZENGPU WEI/
Examiner, Art Unit 2197
Prosecution Insights