DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 06/17/2026, in which claim 1 was amended, claims 11 and 19 were cancelled, claim 20 was withdrawn, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. (US Pub. 20240421074) in view of Arai et al. (US Pub. 20170263598).
Regarding claim 1, Wong et al. discloses in Fig. 7, Fig. 10, paragraph [0047]-[0049] a semiconductor integrated circuit (IC) device comprising:
a frontside back end of line (BEOL) network [106a, 106b, 112c, 114c];
a deep via contact [108c] that is directly connected to a backside resistor [R1] and that is directly connected to the frontside BEOL network [106a, 106b, 112c, 114c]; and
a backside BEOL network [110, 102, 114a, 112a] comprising a conductive pathway [110] directly connected to the backside resistor [R1].
Wong et al. fails to disclose
wherein the backside resistor is horizontally between a first front end of line (FEOL) diode and a second FEOL diode.
Arai et al. discloses in Fig. 1, Fig. 2, paragraph [0032]
wherein a resistor [108 or 110] is horizontally between a first front end of line (FEOL) diode [106] and a second FEOL diode [112]
Wong et al. discloses the resistor is the backside resistor.
Thus, the combination of Wong et al. and Arai et al. would result to “wherein the backside resistor is horizontally between a first front end of line (FEOL) diode and a second FEOL diode.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Arai et al. into the method of Wong et al. to include wherein the backside resistor is horizontally between a first front end of line (FEOL) diode and a second FEOL diode. The ordinary artisan would have been motivated to modify Wong et al. in the above manner for the purpose of providing suitable location of the backside resistor with respect to diodes of an integrated circuit device [paragraph [0009], [0044] of Arai et al.].
Regarding claim 2, Wong et al. discloses in Fig. 7, Fig. 10
wherein the backside resistor [R1] is vertically between the deep via contact [108c] and the backside BEOL network [110, 102, 114a, 112a].
Regarding claim 3, Wong et al. discloses in Fig. 7, Fig. 10
wherein a top surface of the backside resistor [R1] is directly connected to a bottom surface of the deep via contact [108c].
Regarding claim 4, Wong et al. discloses in Fig. 7, Fig. 10,
wherein a bottom surface of the backside resistor [R1] is connected to the backside BEOL network [110, 102, 114a, 112a].
Regarding claim 5, Wong et al. discloses in Fig. 7, Fig. 10, paragraph [0028], [0044]
wherein the backside resistor [R1] is composed of a first conductive material [cermet material, ruthenium oxide, titanium nitride, tantalum nitride, nickel chromium, silicon chromium, copper nickel, copper chromium] and the deep via contact [108c] is composed of a second conductive material [copper] that is different than the first conductive material [cermet material, ruthenium oxide, titanium nitride, tantalum nitride, nickel chromium, silicon chromium, copper nickel, copper chromium].
Regarding claim 6, Wong et al. discloses in Fig. 7, Fig. 10,
wherein the deep via contact [108c] and the backside resistor [R1] route current between the frontside BEOL network [106a, 106b, 112c, 114c] and the backside BEOL network [110, 102, 114a, 112a].
It is noted that the above limitation of claim 6 directs to intended function and manner operation of the deep via contact and the backside resistor. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.” Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 7, the limitation “provide a substantially same electrical potential to both the frontside BEOL network and to the backside BEOL network” of claim 7 directs to intended function and manner operation of the deep via contact and the backside resistor. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.” Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
In this case, Wong et al. discloses in Fig. 7, Fig. 10 all the structural limitations of the claim including structural limitations of the deep via contact and the backside resistor, thus it meets the claim.
Regarding claim 10, Wong et al. discloses in Fig. 7, Fig. 8, paragraph [0047]
wherein the backside resistor [R1] is below a shallow trench isolation (STI) region [118].
The insulating layer 118 is an isolation region. Per MPEP 2131: The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).
Claims 1-7, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. (US Pub. 20240421074) in view of Schaffer et al. (US Pub. 20240038756).
Regarding claim 1, Wong et al. discloses in Fig. 7, Fig. 10, paragraph [0047]-[0049] a semiconductor integrated circuit (IC) device comprising:
a frontside back end of line (BEOL) network [106a, 106b, 112c, 114c];
a deep via contact [108c] that is directly connected to a backside resistor [R1] and that is directly connected to the frontside BEOL network [106a, 106b, 112c, 114c]; and
a backside BEOL network [110, 102, 114a, 112a] comprising a conductive pathway [110] directly connected to the backside resistor [R1].
Wong et al. fails to disclose
wherein the backside resistor is horizontally between a first front end of line (FEOL) diode and a second FEOL diode.
Schaffer et al. discloses in Fig. 1, Fig. 3, paragraph [0004], [0014], [0025], [0030]
wherein a resistor [122] is horizontally between a first front end of line (FEOL) diode [108] and a second FEOL diode [110]
Wong et al. discloses the resistor is the backside resistor.
Thus, the combination of Wong et al. and Schaffer et al. would result to “wherein the backside resistor is horizontally between a first front end of line (FEOL) diode and a second FEOL diode.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Schaffer et al. into the method of Wong et al. to include wherein the backside resistor is horizontally between a first front end of line (FEOL) diode and a second FEOL diode. The ordinary artisan would have been motivated to modify Wong et al. in the above manner for the purpose of providing suitable location of the backside resistor with respect to diodes of an integrated circuit device to allow for a symmetrical or near symmetrical arrangement of the circuit elements and minimize higher order harmonic effects, including second order harmonic effects [paragraph 0030] of Schaffer et al.].
Regarding claim 2, Wong et al. discloses in Fig. 7, Fig. 10
wherein the backside resistor [R1] is vertically between the deep via contact [108c] and the backside BEOL network [110, 102, 114a, 112a].
Regarding claim 3, Wong et al. discloses in Fig. 7, Fig. 10
wherein a top surface of the backside resistor [R1] is directly connected to a bottom surface of the deep via contact [108c].
Regarding claim 4, Wong et al. discloses in Fig. 7, Fig. 10,
wherein a bottom surface of the backside resistor [R1] is connected to the backside BEOL network [110, 102, 114a, 112a].
Regarding claim 5, Wong et al. discloses in Fig. 7, Fig. 10, paragraph [0028], [0044]
wherein the backside resistor [R1] is composed of a first conductive material [cermet material, ruthenium oxide, titanium nitride, tantalum nitride, nickel chromium, silicon chromium, copper nickel, copper chromium] and the deep via contact [108c] is composed of a second conductive material [copper] that is different than the first conductive material [cermet material, ruthenium oxide, titanium nitride, tantalum nitride, nickel chromium, silicon chromium, copper nickel, copper chromium].
Regarding claim 6, Wong et al. discloses in Fig. 7, Fig. 10,
wherein the deep via contact [108c] and the backside resistor [R1] route current between the frontside BEOL network [106a, 106b, 112c, 114c] and the backside BEOL network [110, 102, 114a, 112a].
It is noted that the above limitation of claim 6 directs to intended function and manner operation of the deep via contact and the backside resistor. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.” Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 7, the limitation “provide a substantially same electrical potential to both the frontside BEOL network and to the backside BEOL network” of claim 7 directs to intended function and manner operation of the deep via contact and the backside resistor. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.” Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
In this case, Wong et al. discloses in Fig. 7, Fig. 10 all the structural limitations of the claim including structural limitations of the deep via contact and the backside resistor, thus it meets the claim.
Regarding claim 10, Wong et al. discloses in Fig. 7, Fig. 8, paragraph [0047]
wherein the backside resistor [R1] is below a shallow trench isolation (STI) region [118].
The insulating layer 118 is an isolation region. Per MPEP 2131: The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. (US Pub. 20240421074) and Schaffer et al. (US Pub. 20240038756) as applied to claim 1 above and further in view of Hong et al. (US Pub. 20230095421).
Regarding claims 8-9, Wong et al. fails to disclose
wherein a top surface of the backside resistor is coplanar with a bottom surface of a backside contact associated with a front end of line (FEOL) microdevice;
wherein a bottom surface of the backside resistor is below a bottom surface of a backside contact associated with a front end of line (FEOL) microdevice.
Hong et al. discloses in Fig. 5, paragraph [0020]-[0021], [0029]-[0031]
wherein a top surface of the backside resistor [32] is coplanar with a bottom surface of a backside contact [62] associated with a front end of line (FEOL) microdevice [20];
wherein a bottom surface of the backside resistor [32] is below a bottom surface of a backside contact [62] associated with a front end of line (FEOL) microdevice [20].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Hong et al. into the method of Wong et al. to include wherein a top surface of the backside resistor is coplanar with a bottom surface of a backside contact associated with a front end of line (FEOL) microdevice; wherein a bottom surface of the backside resistor is below a bottom surface of a backside contact associated with a front end of line (FEOL) microdevice. The ordinary artisan would have been motivated to modify Wong et al. in the above manner for the purpose of providing suitable location of the backside resistor with respect to other devices of an integrated circuit device.
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot in view of the new ground of rejection.
Applicant's arguments filed 06/17/2026 have been fully considered but they are not persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Furher, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In this case, Arai et al. is not cited to teach the shape of the diode. Arai et al. is cited to teach the location of a resistor with respect to diodes of an integrated circuit.
The newly cited art, Schaffer et al., is cited to further providing support that in an integrated circuit, a resistor (regardless shape and configuration) can be placed horizontally between two diodes.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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