DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention Group I, species 2, a device shown in Fig. 2 in the reply filed on 02/09/2026 is acknowledged.
Response to Amendment
Applicant’s amendment dated 02/09/2026, in which claims 14-19 were withdrawn, has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 20, claim 20 claims both a transistor and the method steps of using the transistor. “A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011).” See MPEP 2173.05(p).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lu et al. (US Pub. 20190131403).
Regarding claim 1, Lu et al. discloses in Fig. 17A-17C or 37C an integrated circuit device comprising:
a transistor on a substrate [100 or 300], the transistor comprising:
a pair of thin semiconductor layers [102 or 302] spaced apart from each other [paragraph [0015]];
a channel region [101’ or 301] between the pair of thin semiconductor layers [102 or 302], wherein a side surface of the channel region [101’ or 301] is recessed with respect to side surfaces of the pair of thin semiconductor layers [102 or 302] and defines a recess between the pair of thin semiconductor layers [102 or 302][paragraph [0015]-0016], [0035], [0064]];
a gate electrode [114] on the pair of thin semiconductor layers [102 or 302] and the channel region [101’ or 301][paragraph [0035], [0064]]; and
a gate insulator [113] separating the gate electrode [114] from both the pair of thin semiconductor layers [102 or 302] and the channel region [101’ or 301][paragraph [0035], [0064]];
wherein a portion of the gate insulator [113] is in the recess.
Regarding claim 2, Lu et al. discloses in Fig. 17A-17C, paragraph [0027]
wherein the transistor further comprises a pair of source/drain regions [112] spaced apart from each other in a first horizontal direction, wherein the channel region [101’] comprises opposing side surfaces that are spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction, and the side surface of the channel region [101’] is one of the opposing side surfaces.
Regarding claim 3, Lu et al. discloses in Fig. 17B and Fig. 37C
wherein an upper surface and a lower surface of the channel region [101’ or 301], respectively, contact the pair of thin semiconductor layers [102 or 302].
Regarding claim 4, Lu et al. discloses in paragraph [0016], [0063]-[0064]
wherein the pair of thin semiconductor layers [102 or 302] comprise a material different from the channel region [101’ or 301].
Regarding claim 5, Lu et al. discloses in Fig. 17B and Fig. 37C
wherein a portion of the gate electrode [114] is in the recess.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20190103317) in view of Lu et al. (US Pub. 20190131403).
Regarding claim 1, Yu et al. discloses in Fig. 17A an integrated circuit device comprising:
a transistor on a substrate [10], the transistor comprising:
a pair of thin semiconductor layers [15] spaced apart from each other [paragraph [0031]];
a channel region [20] between the pair of thin semiconductor layers [15][paragraph [0032]];
a gate electrode [100] on the pair of thin semiconductor layers [15] and the channel region [20][paragraph [0026]]; and
a gate insulator [95] separating the gate electrode [100] from both the pair of thin semiconductor layers [15] and the channel region [20][paragraph [0072]]
Yu et al. fails to disclose
wherein a side surface of the channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and defines a recess between the pair of thin semiconductor layers;
wherein a portion of the gate insulator is in the recess.
Lu et al. discloses in Fig. 16B, Fig. 37C, paragraph [0035], [0064],
wherein a side surface of the channel region [101’ or 301] is recessed with respect to side surfaces of the pair of thin semiconductor layers [102 or 302] and defines a recess between the pair of thin semiconductor layers [102 or 302];
wherein a portion of the gate insulator [113] is in the recess.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lu et al. into the method of Yu et al. to include wherein a side surface of the channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and defines a recess between the pair of thin semiconductor layers; wherein a portion of the gate insulator is in the recess. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of improving the Ion of the semiconductor device [paragraph [0069] of Lu et al.].
Regarding claim 2, Lu et al. discloses in Fig. 17A-17C, paragraph [0027]
wherein the transistor further comprises a pair of source/drain regions [112] spaced apart from each other in a first horizontal direction, wherein the channel region [101’] comprises opposing side surfaces that are spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction, and the side surface of the channel region [101’] is one of the opposing side surfaces.
Regarding claim 3, Yu et al. discloses in Fig. 17A
wherein an upper surface and a lower surface of the channel region [20], respectively, contact the pair of thin semiconductor layers [15].
Lu et al. also discloses in Fig. 17B and Fig. 37C
wherein an upper surface and a lower surface of the channel region [101’ or 301], respectively, contact the pair of thin semiconductor layers [102 or 302].
Regarding claim 4, Yu et al. discloses in paragraph [0031]-[0032]
wherein the pair of thin semiconductor layers [15] comprise a material different from the channel region [20].
Lu et al. discloses in paragraph [0016], [0063]-[0064]
wherein the pair of thin semiconductor layers [102 or 302] comprise a material different from the channel region [101’ or 301].
Regarding claim 5, Lu et al. discloses in Fig. 17B and Fig. 37C
wherein a portion of the gate electrode [114] is in the recess.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20190103317) in view of Lu et al. (US Pub. 20190131403) as applied to claim 1 above and further in view of Kim et al. (US Pub. 20160276484).
Regarding claims 6-7, Yu et al. discloses in Fig. 17A and Lu et al. discloses in Fig. 17A-17C or 37C
wherein the transistor is a first transistor, and the channel region is a first channel region.
Yu et al. and Lu et al. fails to disclose
wherein the integrated circuit device further comprises a second transistor comprising a second channel region that is spaced apart from the first channel region in a vertical direction and overlaps the first channel region in the vertical direction, the first channel region comprises a material different from the second channel region, and the vertical direction is perpendicular to an upper surface of the substrate;
wherein the second transistor is between the substrate and the first transistor.
Kim et al. discloses in Fig. 3, Fig. 4A-4B, paragraph [0024]-[0038]
wherein the integrated circuit device further comprises a second transistor comprising a second channel region [308C or 304M or 404C] that is spaced apart from the first channel region [310C or 310M or 480B] in a vertical direction and overlaps the first channel region [310C or 310M or 480B] in the vertical direction, the first channel region [310C or 310M or 480B] comprises a material [silicon germanium] different from the second channel region [silicon portion 308C or 304M or 404C], and the vertical direction is perpendicular to an upper surface of the substrate [302 or 402];
wherein the second transistor [transistor formed of channel 308C] is between the substrate [302] and the first transistor [transistor formed of channel 310C][Fig. 3, the fin/omega FET hybrid channel region 300C].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Yu et al. and Lu et al. to include wherein the integrated circuit device further comprises a second transistor comprising a second channel region that is spaced apart from the first channel region in a vertical direction and overlaps the first channel region in the vertical direction, the first channel region comprises a material different from the second channel region, and the vertical direction is perpendicular to an upper surface of the substrate; wherein the second transistor is between the substrate and the first transistor. The ordinary artisan would have been motivated to modify Yu et al. and Lu et al. in the above manner for the purpose of providing hybrid structures to optimize device performance and power consumption [paragraph [0024] of Kim et al.].
Claims 8-10, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20190103317) in view of Kim et al. (US Pub. 20160276484)
Regarding claim 8, Yu et al. discloses in Fig. 17A an integrated circuit device comprising:
a first transistor on a substrate [10],
wherein the first transistor comprises:
a pair of thin semiconductor layers [15] spaced apart from each other [paragraph [0031]];
a first channel region [20] between the pair of thin semiconductor layers [15][paragraph [0032]];
a first gate electrode [100] on the pair of thin semiconductor layers [15] and the first channel region [20][paragraph [0026]]; and
a first gate insulator [95] separating the first gate electrode [100] from both the pair of thin semiconductor layers [15] and the first channel region [20][paragraph [0072]].
Yu et al. fails to disclose
a second transistor stacked on a substrate,
wherein the second transistor comprises:
a second channel region;
a second gate electrode on the second channel region; and
a second gate insulator separating the second gate electrode from the second channel region,
wherein the first channel region and the second channel region are spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate and overlap each other in the vertical direction, and
the first channel region comprises a material different from the second channel region.
Kim et al. discloses in Fig. 4A-4B, paragraph [0024]-[0038]
a second transistor stacked on a substrate [402],
wherein the second transistor comprises:
a second channel region [404C];
a second gate electrode [upper portion of 408] on the second channel region [404C]; and
a second gate insulator separating the second gate electrode [upper portion of 408] from the second channel region [404C][Fig. 4A, Fig. 4B, paragraph [0030]],
wherein the first channel region [480B] and the second channel region [404C] are spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate [402] and overlap each other in the vertical direction, and
the first channel region [480B] comprises a material [silicon germanium] different from the second channel region [silicon portion 404C].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Yu et al. to include a second transistor stacked on a substrate, wherein the second transistor comprises: a second channel region; a second gate electrode on the second channel region; and a second gate insulator separating the second gate electrode from the second channel region, wherein the first channel region and the second channel region are spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate and overlap each other in the vertical direction, and the first channel region comprises a material different from the second channel region. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of providing hybrid structures to optimize device performance and power consumption [paragraph [0024] of Kim et al.].
Regarding claims 9-10, Yu et al. discloses in Fig. 17A, paragraph [0031]-[0032]
wherein the pair of thin semiconductor layers [15] comprise a material different from the first channel region [20];
wherein the first channel region [20] contacts both the pair of thin semiconductor layers [15].
Regarding claim 13, Kim et al. discloses in Fig. 3
wherein the second transistor [transistor formed of channel 308C] is between the substrate [302] and the first transistor [transistor formed of channel 310C][Fig. 3, the fin/omega FET hybrid channel region 300C].
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20190103317) in view of Kim et al. (US Pub. 20160276484) as applied to claim 8 above and further in view of Lu et al. (US Pub. 20190131403).
Regarding claims 11-12, Yu et al. fails to disclose
wherein a side surface of the first channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and defines a recess between the pair of thin semiconductor layers, and a portion of the first gate insulator is in the recess;
wherein a portion of the first gate electrode is in the recess.
Lu et al. discloses in Fig. 16B, Fig. 37C, paragraph [0035], [0064],
wherein a side surface of the first channel region [101’ or 301] is recessed with respect to side surfaces of the pair of thin semiconductor layers [102 or 302] and defines a recess between the pair of thin semiconductor layers [102 or 302], and a portion of the gate insulator [113] is in the recess;
wherein a portion of the first gate electrode [114] is in the recess.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lu et al. into the method of Yu et al. to include wherein a side surface of the first channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and defines a recess between the pair of thin semiconductor layers, and a portion of the first gate insulator is in the recess; wherein a portion of the first gate electrode is in the recess. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of improving the Ion of the first transistor [paragraph [0069] of Lu et al.].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US Pub. 20190131403) in view of and Kim et al. (US Pub. 20080143907)
Regarding claim 20, Lu et al. discloses in Fig. 17A-17C or 37C
a transistor comprising:
a pair of thin semiconductor layers [102 or 302] spaced apart from each other [paragraph [0015]];
a channel region [101’ or 301] between the pair of thin semiconductor layers [102 or 302], wherein a side surface of the channel region [101’ or 301] is recessed with respect to side surfaces of the pair of thin semiconductor layers [102 or 302] and defines a recess between the pair of thin semiconductor layers [102 or 302][paragraph [0015]-0016], [0035], [0064]];
a gate insulator [113] separating a gate electrode [114] from both the pair of thin semiconductor layers [102 or 302] and the channel region [101’ or 301][paragraph [0035], [0064]];
the gate electrode [114] on the pair of thin semiconductor layers [102 or 302] and the channel region [101’ or 301][paragraph [0035], [0064]]; and
wherein a portion of the gate insulator [113] is in the recess.
Lu et al. fails to disclose
a method of transmitting a signal comprising:
applying a signal to a first source/drain of the transistor; and
applying a control signal to a gate electrode of the transistor, wherein the applying the control signal to the gate electrode allows the signal to be transmitted to a second source/drain of the transistor through a channel region of the transistor.
Kim et al. discloses in paragraph [0047]
a method of transmitting a signal comprising:
applying a signal to a first source/drain [17] of a transistor; and
applying a control signal to a gate electrode [13] of the transistor, wherein the applying the control signal to the gate electrode [13] allows the signal to be transmitted to a second source/drain [18] of the transistor through a channel region [15] of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Lu et al. to include a method of transmitting a signal comprising: applying a signal to a first source/drain of the transistor; and applying a control signal to a gate electrode of the transistor, wherein the applying the control signal to the gate electrode allows the signal to be transmitted to a second source/drain of the transistor through a channel region of the transistor. The ordinary artisan would have been motivated to modify Lu et al. in the above manner for the purpose of providing known method for operating a transistor. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893