DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 05/20/2026, in which claims 1-6, 8, 10 were withdrawn, claims 14-16, 18-19 were withdrawn, claims 12, 17 were cancelled, claims 21-23 were added, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-11, 13, 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner et al. (US Pub. 20210104522) in view of Yu et al. (US Pub. 20190103317) and Wang et al. (US Pub. 20220093743).
Regarding claim 1, Gardner et al. discloses in Fig. 1A, Fig. 2A-2B, Fig. 6, paragraphs [0008], [0041]-[0050] an integrated circuit device comprising:
a first transistor [102A] and a second transistor [102B] on a substrate,
wherein the first transistor [102A] comprises:
a first channel region [110];
a first pair of source/drain regions [126 and 128], wherein the first channel region [110] is between the first pair of source/drain regions [126 and 128];
a gate electrode [208] on the first channel region [110]; and
a gate insulator [202 and 204] separating the gate electrode [208] from the first channel region [110];
wherein the second transistor [102B] comprises:
a second pair of source/drain regions [130 and 132] spaced apart from the first pair of source/drain regions [126 and 128]; and
a second channel region [114] between the second pair of source/drain regions [130 and 132].
Gardner et al. fails to disclose
the first transistor comprises:
a pair of thin semiconductor layers spaced apart from each other;
the first channel region between the pair of thin semiconductor layers,
wherein a side surface of the first channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and defines a recess between the pair of thin semiconductor layers;
wherein the pair of thin semiconductor layers is between the first pair of source/drain regions;
the gate electrode on the pair of thin semiconductor layers, wherein a portion of the gate insulator is in the recess.
Yu et al. discloses in Fig. 17A, Fig. 17F, paragraph [0079]-[0084], [0090]
the first transistor comprises:
a pair of thin semiconductor layers [15] spaced apart from each other;
the first channel region [20] between the pair of thin semiconductor layers [15];
wherein the pair of thin semiconductor layers [15] is between the first pair of source/drain regions [80];
the gate electrode [100] on the pair of thin semiconductor layers [15].
Wang et al. discloses in Fig. 15B, Fig. 16C, Fig. 17A-17B, Fig. 19A, paragraph [0023], [0026], [0060], [0067], [0079], [0084], [0089]
the first transistor comprises:
a pair of thin semiconductor layers [106a and 106b] spaced apart from each other;
the first channel region [108a or 108e] between the pair of thin semiconductor layers [106a and 106b],
wherein a side surface of the first channel region [108a or 108e] is recessed with respect to side surfaces of the pair of thin semiconductor layers [106a and 106b] and defines a recess between the pair of thin semiconductor layers [106a and 106b];
wherein the pair of thin semiconductor layers [106a and 106b] is between the first pair of source/drain regions [146];
the gate electrode [172] on the pair of thin semiconductor layers [106a and 106b], wherein a portion of the gate insulator [170] is in the recess.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. and Wang et al. into the method of Gardner et al. to include the first transistor comprises: a pair of thin semiconductor layers spaced apart from each other; the first channel region between the pair of thin semiconductor layers, wherein a side surface of the first channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and defines a recess between the pair of thin semiconductor layers; wherein the pair of thin semiconductor layers is between the first pair of source/drain regions; the gate electrode on the pair of thin semiconductor layers, wherein a portion of the gate insulator is in the recess. The ordinary artisan would have been motivated to modify Gardner et al. in the above manner for the purpose of providing suitable alternative configuration of nanowire having an improved process window of nanowire release etching, leading to higher device yield [paragraph [0084] of Yu et al.] and providing additional conductive area for effective control of drive current in the nanowire transistors of the first transistor [paragraph [0060] of Wang et al.].
Regarding claim 2, Gardner et al. discloses in Fig. 1A, Fig. 6
wherein the first pair of source/drain regions [126 and 128] are spaced apart from each other in a first horizontal direction, wherein the first channel region [110] comprises opposing side surfaces that are spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction, and
wherein the second pair of source/drain regions [130 and 132] are spaced apart from the first pair of source/drain regions [126 and 128] in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction.
Wang et al. discloses in Fig. 14A-14B, Fig. 15B, Fig. 16C, Fig. 17A-17B, Fig. 19A
wherein the first pair of source/drain regions [146] are spaced apart from each other in a first horizontal direction [X direction], wherein the first channel region [108a or 108e] comprises opposing side surfaces that are spaced apart from each other in a second horizontal direction [Y direction] that is perpendicular to the first horizontal direction [X direction], and the side surface of the first channel region [108a or 108e] is one of the opposing side surfaces.
Consequently, the combination of Gardner et al. and Wang et al. discloses limitation of claim 2.
Regarding claim 3, Wang et al. discloses in Fig. 15B, Fig. 16C, Fig. 17A-17B, Fig. 19A, paragraph [0029]
wherein an upper surface and a lower surface of the first channel region [108a or 108e], respectively, contact the pair of thin semiconductor layers [106a and 106b];
wherein a thickness of at least one of the pair of thin semiconductor layers [106a and 106b] in a vertical direction perpendicular to an upper surface of the substrate is less than a thickness of the first channel region [108a or 108e] in the vertical direction [Paragraph [0026], “Each second semiconductor layer 108 may have a thickness that is equal, less, or greater than the thickness of the first semiconductor layer 106”.].
Regarding claim 4, Wang et al. discloses in paragraph [0023]
wherein the pair of thin semiconductor layers [106a and 106b] comprise a material different from the first channel region [108a or 108e].
Regarding claims 6-7, Gardner et al. discloses in Fig. 1A, Fig. 2B, paragraph [0041]-[0042]
wherein the second channel region [114] is spaced apart from the first channel region [110] in a vertical direction and overlaps the first channel region [110] in the vertical direction, the first channel region [110] comprises a material different from the second channel region [114], and the vertical direction is perpendicular to an upper surface of the substrate;
wherein the second transistor [102B] is between the substrate and the first transistor [102A].
Regarding claims 8-11, and 13, Gardner et al. discloses in Fig. 1A, Fig. 2A-2B, Fig. 6, paragraphs [0008], [0041]-[0050] an integrated circuit device comprising:
a first transistor [102A] and a second transistor [102B] stacked on a substrate,
wherein the first transistor [102A] comprises:
a first channel region [110];
a first source/drain region [126 and 128] adjacent to the first channel region [110];
a first gate electrode [208] on the first channel region [110]; and
a first gate insulator [202 and 204] separating the first gate electrode [208] from the first channel region [110],
wherein the second transistor [102B] comprises:
a second channel region [114]
a second source/drain regions [130 and 132] adjacent to the second channel region [114];
a second gate electrode [216] on the second channel region [114]; and
a second gate insulator [210 and 212] separating the second gate electrode [216] from the second channel region [114],
wherein the first channel region [110] and the second channel region [114] are spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate and overlap each other in the vertical direction,
wherein the first source/drain region [126 and 128] and the second source/drain region [130 and 132] are spaced apart from each other in the vertical direction and overlap each other in the vertical direction, and
wherein the first channel region [110] comprises a material different from the second channel region [114][paragraph [0042]];
wherein the second transistor [102B] is between the substrate and the first transistor [102A].
Gardner et al. fails to disclose
the first transistor comprises:
a pair of thin semiconductor layers spaced apart from each other;
the first channel region between the pair of thin semiconductor layers,
the first source/drain region adjacent to the pair of thin semiconductor layers;
the first gate electrode on the pair of thin semiconductor layers,
the first gate insulator separating the first gate electrode from the pair of thin semiconductor layers;
wherein the pair of thin semiconductor layers comprise a material different from the first channel region;
wherein the first channel region contacts both the pair of thin semiconductor layers, and
wherein a concentration of germanium in at least one of the pair of thin semiconductor layers is less than a concentration of germanium in the first channel region;
wherein a side surface of the first channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and defines a recess between the pair of thin semiconductor layers, and a portion of the first gate insulator is in the recess.
Yu et al. discloses in Fig. 17A, Fig. 17F, paragraph [0079]-[0084], [0090]
the first transistor comprises:
a pair of thin semiconductor layers [15] spaced apart from each other;
the first channel region [20] between the pair of thin semiconductor layers [15];
the first source/drain region [80] adjacent to the pair of thin semiconductor layers [15];
the first gate electrode [100] on the pair of thin semiconductor layers [15].
the first gate insulator [95] separating the first gate electrode [100] from the pair of thin semiconductor layers [15];
wherein the pair of thin semiconductor layers [15] comprise a material different from the first channel region [20];
wherein the first channel region [20] contacts both the pair of thin semiconductor layers [15];
Wang et al. discloses in Fig. 15B, Fig. 16C, Fig. 17A-17B, Fig. 19A, paragraph [0023], [0026], [0060], [0067], [0079], [0084], [0089]
the first transistor comprises:
a pair of thin semiconductor layers [106a and 106b] spaced apart from each other;
the first channel region [108a or 108e] between the pair of thin semiconductor layers [106a and 106b],
the first source/drain region [146] adjacent to the pair of thin semiconductor layers [106a and 106b];
the first gate electrode [172] on the pair of thin semiconductor layers [106a and 106b],
the first gate insulator [170] separating the second gate electrode [172] from the pair of thin semiconductor layers [106a and 106b];
wherein the pair of thin semiconductor layers [106a and 106b] comprise a material different from the first channel region [108a or 108e][paragraph [0023]];
wherein the first channel region [108a or 108e] contacts both the pair of thin semiconductor layers [106a and 106b], and
wherein a concentration of germanium in at least one of the pair of thin semiconductor layers [106a and 106b] is less than a concentration of germanium in the first channel region [108a or 108e][paragraph [0023], “the first semiconductor layers 106 may be made of Si and the second semiconductor layers 108 may be made of SiGe”];
wherein a side surface of the first channel region [108a or 108e] is recessed with respect to side surfaces of the pair of thin semiconductor layers [106a and 106b] and defines a recess between the pair of thin semiconductor layers [106a and 106b], and a portion of the first gate insulator [170] is in the recess.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. and Wang et al. into the method of Gardner et al. to include the first transistor comprises: a pair of thin semiconductor layers spaced apart from each other; the first channel region between the pair of thin semiconductor layers, the first source/drain region adjacent to the pair of thin semiconductor layers; the first gate electrode on the pair of thin semiconductor layers, the first gate insulator separating the second gate electrode from the pair of thin semiconductor layers; wherein the pair of thin semiconductor layers comprise a material different from the first channel region; wherein the first channel region contacts both the pair of thin semiconductor layers, and wherein a concentration of germanium in at least one of the pair of thin semiconductor layers is less than a concentration of germanium in the first channel region; wherein a side surface of the first channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and defines a recess between the pair of thin semiconductor layers, and a portion of the first gate insulator is in the recess. The ordinary artisan would have been motivated to modify Gardner et al. in the above manner for the purpose of providing suitable alternative configuration of nanowire having an improved process window of nanowire release etching, leading to higher device yield [paragraph [0084] of Yu et al.]; and providing additional conductive area for effective control of drive current in the nanowire transistor comprising the first channel region [paragraph [0060] of Wang et al.].
Regarding claim 21, Gardner et al., Yu et al. and Wang et al. discloses
wherein the pair of thin semiconductor layers are a first pair of thin semiconductor layers.
Gardner et al. further discloses in Fig. 1, Fig. 2A
wherein the first transistor further comprises:
a third channel region [112]
wherein the gate electrode [208] extends between the first channel region [110] and the third channel region [112].
Gardner et al. fails to disclose
a second pair of thin semiconductor layers spaced apart from the first pair of thin semiconductor layers; and
the third channel region between the second pair of thin semiconductor layers,
wherein a side surface of the third channel region is recessed with respect to side surfaces of the second pair of thin semiconductor layers and defines a recess between the second pair of thin semiconductor layers.
Yu et al. discloses in Fig. 17A, paragraph [0079], [0084], [0090]
a second pair of thin semiconductor layers [15 top] spaced apart from the first pair of thin semiconductor layers [15 middle]; and
the third channel region [20 middle] between the second pair of thin semiconductor layers [15 middle].
Wang et al. suggests in Fig. 15B, Fig. 16C, Fig. 17A-17B, Fig. 19A, paragraph [0060]
wherein a side surface of a channel region is recessed with respect to side surfaces of a pair of thin semiconductor layers and defines a recess between a pair of thin semiconductor layers for providing additional conductive area for effective control of drive current in the nanowire transistor(s).
Thus, it would be obvious to recess a side surface of the third channel region taught by Yu et al. for effective control of drive current in the nanowire transistor comprising the third channel region.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. and Wang et al. into the method of Gardner et al. to include a second pair of thin semiconductor layers spaced apart from the first pair of thin semiconductor layers; and the third channel region between the second pair of thin semiconductor layers, wherein a side surface of the third channel region is recessed with respect to side surfaces of the second pair of thin semiconductor layers and defines a recess between the second pair of thin semiconductor layers. The ordinary artisan would have been motivated to modify Gardner et al. in the above manner for the purpose of providing suitable alternative configuration of nanowire having an improved process window of nanowire release etching, leading to higher device yield [paragraph [0084] of Yu et al.] and providing additional conductive area for effective control of drive current in the nanowire transistor comprising the third channel region [paragraph [0060] of Wang et al.].
Regarding claim 22, Gardner et al. discloses in Fig. 1A, Fig. 2A, Fig. 2B, paragraph [0049]-[0050]
wherein the gate electrode [208] is a first gate electrode, and the gate insulator [202 and 204] is a first gate insulator,
wherein the integrated circuit device further comprises:
a second gate electrode [216] on the second channel region [114]; and
a second gate insulator [210 and 212] separating the second gate electrode [216] from the second channel region [114],
wherein the second gate insulator [210 and 212] is directly on an upper surface and a lower surface of the second channel region [114].
Wang et al. discloses in Fig. 15B, Fig. 16C, Fig. 17A-17B, Fig. 19A
wherein a first one [106a] of the pair of thin semiconductor layers [106a and 106b] is between an upper surface of the first channel region [108a or 108e] and the first gate insulator [170],
wherein a second one [106b] of the pair of thin semiconductor layers [106a and 106b] is between a lower surface of the first channel region [108a or 108e] and the first gate insulator [170].
Yu et al. discloses in Fig. 17A
wherein a first one of the pair of thin semiconductor layers [15] is between an upper surface of the first channel region [top 20] and the first gate insulator [95],
wherein a second one of the pair of thin semiconductor layers [15] is between a lower surface of the first channel region [top 20] and the first gate insulator [95]
Consequently, the combination of Wang et al., Yu et al. and Gardner et al. discloses limitation of claim 22.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Gardner et al. (US Pub. 20210104522) in view of Yu et al. (US Pub. 201901003317) and Wang et al. (US Pub. 20220093743) as applied to claim 1 above and further in view of Su et al. (US Pub. 20210391341).
Regarding claim 5, Gardner et al. discloses in paragraph [0049]
wherein the gate electrode comprises a metal layer.
Gardner et al. fails to disclose
wherein the gate electrode comprises a work function layer between the metal layer and the gate insulator, and
wherein at least a portion of the work function layer is in the recess.
Yu et al. discloses in paragraph [0078]
wherein the gate electrode [100] comprises a work function layer between the metal layer and the gate insulator [95].
Su et al. discloses in Fig. 3B, paragraph [0036]-[0039]
wherein the gate electrode [116 and 114] comprises a work function layer [114] between the metal layer [116] and the gate insulator [112], and
wherein at least a portion of the work function layer [114] is in the recess.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. and Su et al. into the method of Gardner et al. and Wang et al. to include wherein the gate electrode comprises a work function layer between the metal layer and the gate insulator, and wherein at least a portion of the work function layer is in the recess. The ordinary artisan would have been motivated to modify Gardner et al. and Wang et al. in the above manner for the purpose of providing suitable configuration of gate electrode having desired work function [paragraph [0036] of Su et al., paragraph [0078] of Yu et al.].
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Serizawa et al. (US Pub. 20230053433) in view of Yu et al. (US Pub. 20190103317).
Regarding claim 23, Serizawa et al. discloses in Fig. 7, paragraph [0029]-[0032] an integrated circuit device comprising:
a first transistor [formed of nanosheet 122] and a second transistor [formed of nanosheet 121] on a substrate [101],
wherein the first transistor [formed of nanosheet 122] comprises:
a channel structure [122] comprising a first channel region;
a first source/drain region [163] adjacent to the channel structure [122];
a first gate electrode [upper 110] on the channel structure [122];
a first gate insulator [upper 130] separating the first gate electrode [110] from the channel structure [122],
wherein the second transistor [formed of nanosheet 121] comprises:
a second channel region [121];
a second source/drain region [161] adjacent to the second channel region [114];
a second gate electrode [lower 110] on the second channel region [121]; and
a second gate insulator [lower 130] separating the second gate electrode [110] from the second channel region [121],
and wherein a thickness of the channel structure [122] in a vertical direction perpendicular to an upper surface of the substrate is equal to a thickness of the second channel region [121] in the vertical direction [paragraph [0030].
Serizawa et al. fails to disclose
the channel structure comprising a pair of thin semiconductor layers and the first channel region between the pair of thin semiconductor layers;
wherein the pair of thin semiconductor layers comprise a material different from the first channel region.
Yu et al. discloses in Fig. 17A-17B, paragraph [0034]-[0035], [0065], [0072]
a channel structure comprising a pair of thin semiconductor layers [15] and the first channel region [20] between the pair of thin semiconductor layers [15];
wherein the pair of thin semiconductor layers [15] comprise a material different from the first channel region [20].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. into the method of Serizawa et al. to include the channel structure comprising a pair of thin semiconductor layers and the first channel region between the pair of thin semiconductor layers; wherein the pair of thin semiconductor layers comprise a material different from the first channel region. The ordinary artisan would have been motivated to modify Serizawa et al. in the above manner for the purpose of providing suitable alternative configuration of nanowire having an improved process window of nanowire release etching, leading to higher device yield [paragraph [0084] of Yu et al.].
Yu et al. discloses in paragraph [0035] that the channel structure comprising a pair of thin semiconductor layers [15] and the first channel region [20] between the pair of thin semiconductor layers [15] having a thickness in a range of 3.5nm-25nm.
Serizawa et al. discloses in paragraph [0030] that a thickness of the channel structure [122] is equal to a thickness of the second channel region [121], for example, about 5 nm. Thus, the combination of Serizawa et al. and Yu et al. would result to a thickness of the channel structure comprising a pair of thin semiconductor layers and the first channel region between the pair of thin semiconductor layers is equal to a thickness of the second channel region.
In addition, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a thickness of the channel structure comprising a pair of thin semiconductor layers and the first channel region with respect to a thickness of the second channel region: a thickness of the channel structure comprising a pair of thin semiconductor layers and the first channel region is greater than/less than/equal to a thickness of the second channel region. Absent unexpected results, it would have been obvious to try a thickness of the channel structure comprising a pair of thin semiconductor layers and the first channel region is equal to a thickness of the second channel region to yield a device having desired performance.
Response to Arguments
Applicant’s arguments with respect to claims 1-11, 13, 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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