DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
The title of the invention is not descriptive. A new title is required that is clearly
indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5 and 15 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification, as originally filed, does not reasonably convey to one of ordinary skill in the art that inventors were in possession of these limitations at the time of filing, provide description for “the first IPC message sent to the second MCU comprises a copy of the information”. The limitation “the first IPC message sent to the second MCU comprises a copy of the information ” is all undefined in the specification. It is unclear what is actually being described and thus what is actually being claimed to the point where one of ordinary skill in the art would be unable to make or use the invention.
Claim 10 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification, as originally filed, does not reasonably convey to one of ordinary skill in the art that inventors were in possession of these limitations at the time of filing, provide description for “the first and second MCUs receiving a second message; the second MCU, but not the first MCU, accepting the second message, and; the second MCU responding to the second message”. The limitation “the first and second MCUs receiving a second message; the second MCU, but not the first MCU, accepting the second message, and; the second MCU responding to the second message” is all undefined in the specification. It is unclear what is actually being described and thus what is actually being claimed to the point where one of ordinary skill in the art would be unable to make or use the invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Meng et al. (Meng) US publication no. 2017/0003728 A1 in view of Barber et al. (Barber), US patent no. 6240521 B1.
As per claim 1, Meng teaches a method [figure 1c, 4] comprising:
a first microcontroller unit (MCU) receiving a first message while operating in active mode [para 8, 25]; the first MCU generating and sending a first inter processor
communication (IPC) message to a second MCU in response to the first MCU receiving the first message [para 25-26, 68];
the second MCU transitioning from sleep mode to active mode in response to the second MCU receiving the first IPC message [para 25-26, 61, 78];
the second MCU responding to the first message after transitioning to active mode [para 79].
Meng fails to teach the first MCU transitioning from active mode to sleep mode after the first MCU sends the first IPC message to the second MCU; wherein the first MCU is in sleep mode while the second MCU responds to the first message; wherein the second MCU consumes more power operating in active mode than the first MCU consumes while operating in active mode.
Barber teaches the first MCU transitioning from active mode to sleep mode after the first MCU sends the first IPC message to the second MCU [figure 3; col. 4, lines 31]; wherein the first MCU is in sleep mode while the second MCU responds to the first message [col. 3, lines 5-14, 45-47; col. 4, lines 1-8]; wherein the second MCU consumes more power operating in active mode than the first MCU consumes while operating in active mode [col. 4, lines 1-8].
It would have been obvious to one of ordinary skill in the art at time the invention to combine the teachings of Meng and Barber because they both disclose dual processor system, the specify teachings of Barber stated above would have further enhanced the performance and functionality of Meng system to obtain predictable results to perform power saving.
Meng teaches:
[0038] In embodiments of the present disclosure, by sending the interrupt wakeup signal to the second MCU via the wakeup pin connected between the first MCU and the second MCU, the MCU in the deep sleep state may be woken up by other MCUs through triggering an external interrupt event, without waiting for an inner interrupt event in the MCU under the deep sleep state, thus improving the efficiency of communication between MCUs.
[0068] In step 401, a detecting message is sent to the second MCU via a communication interface between a first MCU and the second MCU, when the first MCU triggers a communication event of transmitting data to the second MCU.
Barber teaches:
Both processors 12, 14 share a common instruction set, common 1/0 system and memory system address space, and each processor includes an active mode and a sleep mode. The computer system 10 includes elements permitting a user to place each processor into its sleep mode, and to selectively activate one processor from the sleep mode to an active mode. The active processor executes program instructions
stored in the memory system 20. Both processors can be placed simultaneously in the sleep mode. One processor at a time can be activated to execute program instructions.
In like manner, the low-power processor 44 can be placed into the sleep mode, and will suspend the execution of the 25 program, save its current machine state in the predetermined block of the shared memory system 50, and enter the sleep mode. The high-speed processor 42 can be aroused from the sleep mode and will retrieve the previously saved machine state from the shared memory system 50 and use that state
30 to resume the execution of the previously suspended program. Alternatively, the low-power processor 44 can be called out of the sleep mode to resume the execution of the program. In this specific embodiment, the program can be executed by either processor, and neither processor need be 35 aware of which processor is active.
As per claim 2, Meng teaches the first message comprises a message to establish a network connection [para 23, 26, 38, 106].
As per claim 3, Meng teaches the second MCU transfers or receives data in packets while responding to the first message [para 23, 31, 35, 106].
As per claim 4, Barber teaches the first MCU operates at a first clock speed while operating in active mode, wherein the second MCU operates at a second clock speed; while operating in active mode, and wherein the second clock speed is greater than the first clock speed [figures 3, 4; col. 3, lines 55-58, col. 5, lines 49-56].
As per claim 5, Meng teaches the first message comprises information, and wherein the first IPC message sent to the second MCU comprises a copy of the information [para 25, 31].
As per claim 6, Meng teaches the information comprises an internet protocol (IP) address and a port identifier [para 106].
As per claim 7, Barber teaches the first MCU executes instructions of an application stored in a memory while operating in active mode, and wherein the second MCU executes instructions of the application in the memory while operating in active mode [col. 3, lines 36-49, col. 4, lines 23-31].
As per claim 8, Barber teaches the first IPC message comprises an address in the memory where instructions of the application are stored [col. 4, lines 55-64, col. 5, lines 43-48].
As per claim 9, Barber teaches the second MCU generating and sending a second IPC message to the first MCU after the second MCU responds to the first message; the second MCU transitioning to sleep mode after the second MCU sends the second IPC message to the first MCU [col. 4, lines 14-22], and; the first MCU transitioning to active mode in response to the first MCU receiving the second IPC message [col. 4, lines 14-33].
As per claim 10, Barber teaches the first and second MCUs receiving a second message; the second MCU, but not the first MCU, accepting the second message, and; the second MCU responding to the second message [figures 3, 4; col. 4, lines 1-35].
As to claims 11-17, basically are the corresponding elements that are carried out the method of operating step in claims 1-10. Accordingly, claims 11-17 are rejected for the same reason as set forth in claims 1-10.
As to claims 18-20, basically are the corresponding elements that are carried out the method of operating step in claims 1 and 4. Accordingly, claims 18-20 are rejected for the same reason as set forth in claims 1 and 4.
9. Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS."
10. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Sheynblat et al,, US publication no. 2009/0259865, discloses a power management circuit in a mobile station comprising: a main processor configured to execute applications including signal processing applications and further configured to enter a sleep mode in response to predetermined criteria; and a circuit configured to operate when said main processor is in the sleep mode comprising at least one of a low power processor and a sensor to monitor at least one of signals, commands, inputs, and changes in environment, said circuit waking up said main processor responsive to one of said low power processor and said sensor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN CAO whose telephone number is (571)272-3664. The examiner can normally be reached on M-F 7:.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini Shah can be reached on 571-272-9. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN CAO/Primary Examiner, Art Unit 2115