DETAILED ACTION
This office action is in response to the application filed on 09/20/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The listing of references in the specification is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
In re to claims 14-26, method claims 14-26 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3,5, 10, 14-16, 18 and 23 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen US 2023/0170784.
Regarding Claims 1 and 14, Chen teaches (Figures 2-11) a buck-boost switching converter (fig. 2), configured to perform power conversion between a first voltage (Vbus) at a first power node and a second voltage (Vsys) at a second power node, the buck-boost switching converter comprising: a first sub-converter (fly capacitor converter), coupled between the first power node and a first switching node (sw1), wherein the first sub-converter is a first switched-capacitor converter which includes a first group of plural switches (Qhs1-2 and Qls1-2) and a first capacitor (Cfly); and a second sub-converter (Csys, Qhs3 and Qls3), which is coupled between a second switching node (sw2) and the second power node (at sys), and includes a second group of plural switches (fig. 3); wherein the first group of plural switches and the second group of plural switches are configured to periodically switch the first capacitor and an inductor (220) between a plurality of electrical connection states based on a switching frequency according to a plurality of switching signals (See fig. 3, 5 and 7), wherein the inductor is coupled between the first switching node and the second switching node (sw1-sw2); wherein the plurality of switching signals switch the first capacitor between the plurality of electrical connection states to perform a switched-capacitor voltage division on the first voltage (buck mode), so as to switch the first switching node between a first reference potential (Vbus) and a divided voltage of the first voltage obtained by the switched-capacitor voltage division (Vcfly or Vsw1, par. 25), and switching the second switching node between at least two potentials (at Sys and ground), thereby performing power conversion between the first voltage and the second voltage; wherein the first reference potential is the first voltage (Vbus), a ground potential, or another divided voltage of the first voltage; and wherein one of the at least two potentials is related to the second voltage (Vsys). (For Example: Par. 25-30, 37, 42 and 45)
Regarding Claims 2 and 15, Chen teaches (Figures 2-11) wherein the first voltage is greater (buck mode) than, equal to, or lower than the second voltage. (For Example: Par. 25-30, 37, 42 and 45)
Regarding Claims 3 and 16, Chen teaches (Figures 2-11) wherein the second group of plural switches includes: a high-side switch (Qhs3), coupled between the inductor (L) and the second voltage (Vsys); and a low-side switch (Qls3), coupled between the inductor and the ground potential (gnd); wherein in a boost mode or a buck-boost mode, the inductor is periodically switched by the high-side switch and the low-side switch, such that the second switching node switches between the second voltage and the ground potential (Figs. 7-8). (For Example: Par. 25-30, 37, 42 and 45)
Regarding Claims 5 and 18, Chen teaches (Figures 2-11) wherein the first group of plural switches includes four switches for periodically switching the first capacitor according to the plurality of switching signals (Qs1 and Qs2), such that the first capacitor (Cfly1) is switched between a one-half of the first voltage and the first voltage (par. 40-41), or switching the first switching node between the one-half of the first voltage and the ground potential. (For Example: Par. 25-30, 37-42 and 45)
Regarding Claims 10 and 23, Chen teaches (Figures 2-11) wherein the first sub-converter (flycapacitor converter) is operated in a boost mode, a buck mode, a buck-boost mode (Figs. 5-11), or a bypass mode according to the plurality of switching signals (GH and GL) and a voltage conversion ratio between the second voltage and the first voltage (Vout and Vin). (For Example: Par. 25-30, 37, 42 and 45)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chen14 US2023/0170784.
Regarding Claims 4 and 17, Chen teaches (Figures 2-11) a converter.
Chen does not teach wherein the second sub-converter is a second switched-capacitor converter and further includes a second capacitor; wherein the second switched-capacitor converter operates the second capacitor to perform switched-capacitor switching over the second voltage to switch the second switching node between a divided voltage of the second voltage and a second reference potential; and wherein the second reference potential is the second voltage, the ground potential, or another divided voltage of the second voltage.
Chen14 teaches (Figure 14) wherein the second sub-converter (at fig. 14, right side of L) is a second switched-capacitor converter and further includes a second capacitor (cfly2); wherein the second switched-capacitor converter operates the second capacitor to perform switched-capacitor switching over the second voltage to switch the second switching node (sw2) between a divided voltage of the second voltage (at Cfly2 or sw2) and a second reference potential (Vsys and ground); and wherein the second reference potential is the second voltage (Vsys), the ground potential, or another divided voltage of the second voltage. (For Example: Par. 38-41 and 55)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Chen to include wherein the second sub-converter is a second switched-capacitor converter and further includes a second capacitor; wherein the second switched-capacitor converter operates the second capacitor to perform switched-capacitor switching over the second voltage to switch the second switching node between a divided voltage of the second voltage and a second reference potential; and wherein the second reference potential is the second voltage, the ground potential, or another divided voltage of the second voltage, as taught by Chen14 to achieve the optimal efficiency.
Claim(s) 6-8, 11-13, 19-21 and 24-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Liu US 2021/0367520.
Regarding Claims 6 and 19, Chen teaches (Figures 2-11) a buck-boost switching converter.
Chen does not teach wherein the switching frequency is related to a resonant frequency, such that the buck-boost switching converter operates in a resonant mode to control a voltage ratio of the second voltage to the first voltage to be related to a voltage division ratio of the divided voltage of the first voltage to the first voltage, wherein the resonant frequency is related to a capacitance of the first capacitor and an inductance of the inductor.
Liu teaches (Figures 3, 5 and 10-11) wherein the switching frequency is related to a resonant frequency (par. 99), such that the converter operates in a resonant mode to control a voltage ratio of the second voltage (Vout) to the first voltage (Vin) to be related to a voltage division ratio of the divided voltage of the first voltage to the first voltage (par. 53, 65 and 83), wherein the resonant frequency is related to a capacitance of the first capacitor and an inductance of the inductor (par. 53-55).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Chen to include wherein the switching frequency is related to a resonant frequency, such that the buck-boost switching converter operates in a resonant mode to control a voltage ratio of the second voltage to the first voltage to be related to a voltage division ratio of the divided voltage of the first voltage to the first voltage, wherein the resonant frequency is related to a capacitance of the first capacitor and an inductance of the inductor, as taught by Liu to reduce a wide variation range of the capacitance of the capacitor, resulting in a larger switching power loss.
Regarding Claims 7 and 20, Chen teaches (Figures 2-11) a buck-boost switching converter.
Chen does not teach further comprising a control circuit configured to operably generate the plurality of switching signals, wherein the control circuit includes a zero-current detection circuit coupled to the inductor to generate a zero-current signal according to a zero-current time point in which an inductor current flowing through the inductor is zero-current; and wherein the plurality of switching signals switch a corresponding first group of plural switches and/or the second group of plural switches subsequent to the zero-current time point indicated by the zero-current signal, so as to switch the plurality of electrical connection states.
Liu teaches (Figures 3, 5 and 10-11) further comprising a control circuit (301-303) configured to operably generate the plurality of switching signals (from 303), wherein the control circuit includes a zero-current detection circuit (302) coupled to the inductor to generate a zero-current signal (ZCD) according to a zero-current time point (Vref1) in which an inductor current flowing through the inductor is zero-current; and wherein the plurality of switching signals switch a corresponding first group of plural switches and/or the second group of plural switches subsequent to the zero-current time point indicated by the zero-current signal, so as to switch the plurality of electrical connection states (Fig. 11). (For Example: Par. 70-75)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Chen to include further comprising a control circuit configured to operably generate the plurality of switching signals, wherein the control circuit includes a zero-current detection circuit coupled to the inductor to generate a zero-current signal according to a zero-current time point in which an inductor current flowing through the inductor is zero-current; and wherein the plurality of switching signals switch a corresponding first group of plural switches and/or the second group of plural switches subsequent to the zero-current time point indicated by the zero-current signal, so as to switch the plurality of electrical connection states, as taught by Liu to reduce a wide variation range of the capacitance of the capacitor, resulting in a larger switching power loss.
Regarding Claims 8 and 21, Chen teaches (Figures 2-11) a buck-boost switching converter.
Chen wherein the plurality of switching signals further adjust a conduction time of the first group of plural switches and/or a conduction time of the second group of plural switches according to the zero-current signal; and/or, the plurality of switching signals further adjust the switching frequency according to a dead-time after the zero-current time point of the zero-current signal, wherein the inductor current is zero during an electrical connection state within the dead-time.
Liu teaches (Figures 3, 5 and 10-11) wherein the plurality of switching signals (from 303) further adjust a conduction time of the first group of plural switches and/or a conduction time of the second group of plural switches according to the zero-current signal (Figs. 11); and/or, the plurality of switching signals further adjust the switching frequency according to a dead-time after the zero-current time point of the zero-current signal, wherein the inductor current is zero during an electrical connection state within the dead-time. (For Example: Par. 70-75 and 97-99)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Chen to include wherein the switching frequency is related to a resonant frequency, such that the buck-boost switching converter operates in a resonant mode to control a voltage ratio of the second voltage to the first voltage to be related to a voltage division ratio of the divided voltage of the first voltage to the first voltage, wherein the resonant frequency is related to a capacitance of the first capacitor and an inductance of the inductor, as taught by Liu to reduce a wide variation range of the capacitance of the capacitor, resulting in a larger switching power loss.
Regarding Claims 11 and 24, Chen teaches (Figures 2-11) wherein the first group of plural switches and/or the second group of plural switches (QH and QL) are turned on during a constant conduction time (par. 29-30) according to the plurality of switching signals.
Chen does not teach wherein a switching period corresponding to the switching frequency is determined according to the first voltage, the second voltage and a load, or according to the zero-current signal.
Liu teaches (Figures 3, 5 and 10-11) wherein a switching period corresponding to the switching frequency is determined according to the first voltage, the second voltage and a load, or according to the zero-current signal (ZCD, Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Chen to include a switching period corresponding to the switching frequency is determined according to the first voltage, the second voltage and a load, or according to the zero-current signal, as taught by Liu to reduce a wide variation range of the capacitance of the capacitor, resulting in a larger switching power loss.
Regarding Claims 12 and 25, Chen teaches (Figures 2-11) a buck-boost switching converter.
Chen does not teach wherein when an inductor current flowing through the inductor is zero or close to zero, a part of switches of the first group of plural switches and/or a part of switches of the second group of plural switches are turned off to achieve zero-current switching (ZCS).
Liu teaches (Figures 3, 5 and 10-11) wherein when an inductor current flowing through the inductor (L) is zero or close to zero, a part of switches of the first group of plural switches and/or a part of switches of the second group of plural switches are turned off to achieve zero-current switching (ZCS). (For Example: Par.48-49, 80 and 97-99)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Chen to include wherein when an inductor current flowing through the inductor is zero or close to zero, a part of switches of the first group of plural switches and/or a part of switches of the second group of plural switches are turned off to achieve zero-current switching (ZCS), as taught by Liu to reduce a wide variation range of the capacitance of the capacitor, resulting in a larger switching power loss.
Regarding Claims 13 and 26, Chen teaches (Figures 2-11) a buck-boost switching converter.
Chen does not teach wherein a part of switches of the first group of plural switches and/or a part of switches of the second group of plural switches are turned off after a delay time when an inductor current flowing through the inductor reaches zero-current, thereby generating a reverse current to achieve zero voltage switching (ZVS).
Liu teaches (Figures 3, 5 and 10-11) wherein a part of switches of the first group of plural switches and/or a part of switches of the second group of plural switches (with ga and gb) are turned off after a delay time (e.g. determined by and t2-t3) when an inductor current flowing through the inductor reaches zero-current, thereby generating a reverse current to achieve zero voltage switching (ZVS). (For Example: Par. 58, 65, 82 and 97-99)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Chen to include wherein a part of switches of the first group of plural switches and/or a part of switches of the second group of plural switches are turned off after a delay time when an inductor current flowing through the inductor reaches zero-current, thereby generating a reverse current to achieve zero voltage switching (ZVS), as taught by Liu to reduce a wide variation range of the capacitance of the capacitor, resulting in a larger switching power loss.
Claim(s) 9 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hirose US 2022/0278612.
Regarding Claims 9 and 22, Chen teaches (Figures 2-11) the buck-boost switching converter.
Chen does not teach wherein the switching frequency is much higher than a resonant frequency to an extent, such that the buck-boost switching converter operates in a non-resonant mode, thereby regulating the second voltage at a predetermined level, wherein the resonant frequency is related to the capacitance of the first capacitor and the inductance of the inductor..
Hirose teaches (Figures 1-7) wherein the switching frequency (Fs) is much higher than a resonant frequency (Fh) to an extent (Figs. 5 and 5), such that the converter operates in a non-resonant mode (fig. 7a), thereby regulating the second voltage at a predetermined level (determined by the controller), wherein the resonant frequency is related to the capacitance of the first capacitor and the inductance of the inductor(par. 50-51). (For Example: Par. 60-70)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Chen to include wherein the switching frequency is much higher than a resonant frequency to an extent, such that the buck-boost switching converter operates in a non-resonant mode, thereby regulating the second voltage at a predetermined level, wherein the resonant frequency is related to the capacitance of the first capacitor and the inductance of the inductor, as taught by Hirose to be able to control switching of a charge pump in accordance with a result of detecting a current, while lowering a peak value of the current to facilitate the current detection and reducing or preventing variations in the peak value of the current and variations in the time to charge and discharge.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838