Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This final Office action is responsive to the amendment filed on 01/07/2026. Claims 1, 3-21 and 23-39 are presented for examination and are still rejected for the reasons indicated herein below.
Response to arguments
2. Applicant's arguments filed on 01/07/2026 have been fully considered but they are not persuasive and the claims are still rejected (see the rejection below).
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
4. Claims 1, 3-4, 8, 23-24 and 28 are objected to because of the following informalities:
Claim 1, line 11, recites “the applied voltage” it should be changed to “[[the]] an applied voltage”. Appropriate correction is required.
Each of claims 3 and 4 should depend from claim 1. Appropriate correction is required.
Claim 8, line 1, recites “wherein the plurality of gate drivers comprises” it should be changed to “wherein the plurality of gate drivers comprise
Each of claims 23 and 24 should depend from claim 21. Appropriate correction is required.
Claim 28, line 1, recites “wherein the plurality of gate drivers comprises” it should be changed to “wherein the plurality of gate drivers comprise
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 7-9, 12, 17-18, 21, 23, 27-30 and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Asai (U.S. Pub. No. 2009/0052211 A1).
Regarding claim 1, Asai (e.g. see Figs. 1-11) discloses “A system for discharging a capacitor bank of a DC bus in a power inverter circuit for an electric motor (e.g. see Figs. 1-11), the system comprising: circuitry configured to receive charge from the capacitor bank connected to the DC bus, wherein the capacitor bank includes one or more capacitors (e.g. Fig. 4, see at least 61 and its connections. Implicit); a plurality of power transistors (51a-51f) connected to the DC bus and configured to provide power to the electric motor (81), wherein each power transistor has drain, gate, and source terminals (e.g. Fig. 4, see plurality of power transistors 51a-51f, motor 81 and each power transistor has drain, gate, and source terminals. Implicit); and a plurality of gate drivers (31a-31f) connected to the plurality of power transistors (51a-51f), respectively, wherein the plurality of gate drivers (31a-31f) is configured to: connect the gate terminal to the drain terminal of the plurality of power transistors, respectively, and to apply the applied voltage across the drain and source terminals, respectively (e.g. Figs. 1-11, see plurality of power transistors 51a-51f, each power transistor has a respective gate driver configured to connect the respective gate terminal to the respective drain terminal of the respective power transistor and to apply the applied voltage across the respective drain and source terminals. Examiner’s Note: based on the broadest reasonable interpretation, this limitation is in fact taught by Asai and shown in each of Figs. 2, 4, 6-7 and 9-10); and apply the applied voltage across the plurality of power transistors (51a-51f) during a controlled time, respectively, and to cause the plurality of power transistors (51a-51f) to conduct current during the controlled time, wherein charge is controllably dissipated from the capacitor bank during the controlled time (e.g. Figs. 1-11, see 91, 61, 81, plurality of power transistors 51a-51f, each power transistor has a respective gate driver. Implicit)”.
Regarding claim 3, Asai (e.g. see Figs. 1-11) discloses “wherein the applied voltage comprises a gate threshold voltage of the plurality of power transistors (e.g. Figs. 1-11, see plurality of power transistors 51a-51f, also see threshold voltage in Figs. 3 and 8, also see para. 0011, para. 0029-0042, and para. 0046-0053. Implicit)”.
Regarding claim 7, Asai (e.g. see Figs. 1-11) discloses “wherein the plurality of gate drivers (31a-31f) are configured to cause the plurality of power transistors (51a-51f) to operate in a linear region of a gain curve of the plurality of power transistors during the controlled time (e.g. Figs. 1-11, see at least Figs. 3 and 8, also see para. 0011, para. 0029-0042, and para. 0046-0053. Implicit)”.
Regarding claim 8, Asai (e.g. see Figs. 1-11) discloses “wherein the plurality of gate drivers comprises a plurality of programmable gate drivers (e.g. Figs. 1-11, see plurality of gate driver. Implicit)”.
Regarding claim 9, Asai (e.g. see Figs. 1-11) discloses “wherein the plurality of programmable gate drivers are configured to apply the applied voltage according to a duty cycle (e.g. Figs. 1-11, see plurality of gate driver, also see Figs. 5 and 11. Implicit)”.
Regarding claim 12, Asai (e.g. see Figs. 1-11) discloses “wherein the plurality of power transistors comprise MOSFETs (e.g. Figs. 1-11, see plurality of power transistors 51a-51f, also see para. 0011-0012 and para. 0027-0028. Implicit)”.
Regarding claim 17, Asai (e.g. see Figs. 1-11) discloses “further comprising a battery configured to provide power to the electric motor (e.g. Figs. 1-11, see 91 and 81, also see para. 0001 and para. 0039. Implicit)”.
Regarding claim 18, Asai (e.g. see Figs. 1-11) discloses “wherein the battery is configured to store power received from the electric motor (e.g. Figs. 1-11, see 91 and 81, also see para. 0001 and para. 0039. Implicit)”.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 4-6, 19-20, 24-26 and 38-39 are rejected under 35 U.S.C. 103(a) as being unpatentable over Asai (U.S. Pub. No. 2009/0052211 A1) in view of Trainer et al. (U.S. Pub. No. 2024/0280414 A1).
Regarding claim 4, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 2, except for “wherein the applied voltage is between a gate threshold voltage and a voltage corresponding to a Miller plateau of a gate-charge curve of the plurality of power transistors”. However, Trainer et al. shows “wherein the applied voltage is between a gate threshold voltage and a voltage corresponding to a Miller plateau of a gate-charge curve of the plurality of power transistors (Trainer et al., e.g. see Figs. 5-6. Implicit)”. Having the applied voltage being between a gate threshold voltage and a voltage corresponding to a Miller plateau of a gate-charge curve of the plurality of power transistors as taught by Trainer et al. in the power converter of Asai would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the applied voltage being between a gate threshold voltage and a voltage corresponding to a Miller plateau of a gate-charge curve of the plurality of power transistors as taught by Trainer et al. in the power converter of Asai for the purpose of protection and enhancing the power efficiency of the power converter and minimizing power loss. Also, for the purpose of making the device more widely usable.
Regarding claim 5, the combination of Asai (e.g. see Figs. 1-11) and Trainer et al. (e.g. see Figs. 2-8) discloses “wherein the plurality of gate drivers are configured to monitor slope change of the gate-charge curve to detect a transition to the Miller plateau (Asai, e.g. Figs. 1-11, see plurality of gate driver, also see Trainer et al., e.g. see Figs. 5-6. Implicit)”.
Regarding claim 6, the combination of Asai (e.g. see Figs. 1-11) and Trainer et al. (e.g. see Figs. 2-8) discloses “wherein the plurality of gate drivers are further configured to respond to the transition to the Miller plateau by terminating a charge event of the plurality of power transistors and initiating a discharge event (Asai, e.g. Figs. 1-11, see plurality of gate driver, also see Trainer et al., e.g. see Figs. 5-6. Implicit)”.
Regarding claim 19, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 1, except for “wherein the electric motor comprises a permanent magnet synchronous motor (PMSM)”. However, Trainer et al. shows “wherein the electric motor comprises a permanent magnet synchronous motor (PMSM) (Trainer et al., e.g. see Figs. 2-8, also see para. 0081 “may be of any suitable type, for example of the permanent magnet synchronous type”. Implicit)”. Having the electric motor of Asai being a permanent magnet synchronous motor (PMSM) as taught by Trainer et al. would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been an obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the electric motor of Asai being a permanent magnet synchronous motor (PMSM) as taught by Trainer et al. for the purpose of using a well-known alternative electric motor type. Also, for the purpose of making the system more widely usable.
Regarding claim 20, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 1, except for “wherein the plurality of gate drivers are configured to adjust the applied voltage based on a temperature associated with the plurality of power transistors”. However, Trainer et al. shows “wherein the plurality of gate drivers are configured to adjust the applied voltage based on a temperature associated with the plurality of power transistors (Trainer et al., e.g. Figs. 2-8, see 710 and 309, also see para. 0090-0100. Implicit)”. Having the plurality of gate drivers of Asai being configured to adjust the applied voltage based on a temperature associated with the plurality of power transistors as taught by Trainer et al. would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of gate drivers of Asai being configured to adjust the applied voltage based on a temperature associated with the plurality of power transistors as taught by Trainer et al. for the purpose of protection from overheat and minimizing power loss. Also, for the purpose of making the device more widely usable.
Claims 10-11, 13-16, 31-32 and 34-37 are rejected under 35 U.S.C. 103(a) as being unpatentable over Asai (U.S. Pub. No. 2009/0052211 A1)
Regarding claim 10, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 1, except for “wherein the plurality of power transistors comprise enhancement mode transistors”. However, having the plurality of power transistors comprise enhancement mode transistors would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been an obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of power transistors comprise enhancement mode transistors for the purpose of using a well-known alternative switching element type and making the circuit more widely usable.
Regarding claim 11, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 1, except for “wherein the plurality of power transistors comprise depletion mode transistors”. However, having the plurality of power transistors comprise depletion mode transistors would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been an obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of power transistors comprise depletion mode transistors for the purpose of using a well-known alternative switching element type and making the circuit more widely usable.
Regarding claim 13, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 1, except for “wherein the plurality of power transistors comprise MESFETs”. However, having the plurality of power transistors comprise MESFETs would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been an obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of power transistors comprise MESFETs for the purpose of using a well-known alternative switching element type and making the circuit more widely usable.
Regarding claim 14, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 1, except for “wherein the plurality of power transistors comprise JFETs”. However, having the plurality of power transistors comprise JFETs would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been an obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of power transistors comprise JFETs for the purpose of using a well-known alternative switching element type and making the circuit more widely usable.
Regarding claim 15, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 1, except for “wherein the plurality of power transistors comprise silicon carbide (SiC) FETs”. However, having the plurality of power transistors comprise silicon carbide (SiC) FETs would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been an obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of power transistors comprise silicon carbide (SiC) FETs for the purpose of using a well-known alternative switching element type and making the circuit more widely usable.
Regarding claim 16, Asai (e.g. see Figs. 1-11) discloses a power converter having all the claimed subject matter as discussed in the rejection to claim 1, except for “wherein the plurality of power transistors comprise gallium nitride (GaN) FETs”. However, having the plurality of power transistors comprise gallium nitride (GaN) FETs would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been an obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of power transistors comprise gallium nitride (GaN) FETs for the purpose of using a well-known alternative switching element type and making the circuit more widely usable.
Regarding method claims 21 and 23-39; they all comprise substantially same subject matter as in the recited apparatus claims 1 and 3-20, therefore method claims 21 and 23-39 are also rejected under the same ground of rejection as clearly discussed in the rejection to the apparatus claims 1 and 3-20. Also the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated).
Conclusion
7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUSEF A AHMED whose telephone number is (571)272-6057. The examiner can normally be reached on Monday-Friday 11AM-7PM.
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/YUSEF A AHMED/Primary Examiner, Art Unit 2838