DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 8, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ginsburg (US 20190195987, hereinafter “Ginsburg”, in view of Ben-Yishay (US 20200186175, hereinafter “Ben”), and further in view of Reynolds et al. (US 20090051394, hereinafter “Reynolds”).
Regarding claim 1, Ginsburg discloses,
A multi-chip apparatus (Fig. 1; FMCW radar system 100), wherein:
the multi-chip apparatus comprises a first chip (Fig. 3; master SOC 102) and a second chip (Fig. 3; slave SOC 104), the first chip comprises a first internal signal generator (Fig. 2; 230, Fig. 3; 302 and Para. [0026]: the radio frequency synthesizer (RFSYNTH) 230 including functionality to generate FMCW signals for transmission) and a first frequency multiplier coupled to the first internal signal generator (Fig. 2; 240, Fig. 3; 310 and Para. [0029]: The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208) and the second chip (Fig. 3; slave SOC 104) comprises a second internal signal generator (Fig. 3; 314) and a second frequency multiplier (Fig. 3; 322) coupled to the second internal signal generator (Fig. 3 shows clock multiplier 322 is coupled to the RFSYNTH 314);
an input end of the first receiving circuit is coupled to an output end of the first internal signal generator through an input/output pin between the first chip and the second chip, an input end of the second receiving circuit is coupled to an output end of the second internal signal generator ([0027]: If the radar SOC 200 is used as the slave radar SOC 104, the radar SOC 200 receives signals generated by the RFSYNTH of the master radar SOC 102 via the buffer 236. The multiplexer 232 is configurable to select between signals received in the input buffer 236 and signals generated by the RFSYNTH 230…..[0032]: . The output buffer 308 of the master radar SOC 102 is coupled to the input buffer 320 of the slave radar SOC 104.),
the first internal signal generator (Fig. 2; 230, Fig. 3; 302) is configured to generate a first local oscillator signal (Para. [0026]: The radio frequency synthesizer (RFSYNTH) 230 includes functionality to generate FMCW signals for transmission. In some embodiments, the RFSYNTH 230 includes a phase locked loop (PLL) with a voltage controlled oscillator (VCO), and a programmable ramp generator that is programmed by the control module 226.);
the first frequency multiplier (Fig. 2; 240, Fig. 3; 310) is configured to receive the first local oscillator signal, and perform frequency multiplication on the first local oscillator signal (Para. [0029]: coupled to the first internal signal generator, The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208);
the second internal signal generator (Fig. 3; 314) is configured to generate a second local oscillator signal (Para. [0026]: The radio frequency synthesizer (RFSYNTH) 230 includes functionality to generate FMCW signals for transmission. In some embodiments, the RFSYNTH 230 includes a phase locked loop (PLL) with a voltage controlled oscillator (VCO), and a programmable ramp generator that is programmed by the control module 226.); and
the second frequency multiplier (Fig. 3; 322) is configured to receive the first local oscillator signal by using the first receiving circuit, receive the second local oscillator signal by using the second receiving circuit ([0027]:The multiplexer 232 is configurable to select between signals received in the input buffer 236 and signals generated by the RFSYNTH 230), and perform frequency multiplication on the first local oscillator signal or the second local oscillator signal ([0029] The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208. In the radar system 100, the transmission signal for the master radar SOC 102 and the slave radar SOC 104 is generated by the RFSYNTH of the master radar SOC 102);.
However, Ginsburg does not explicitly disclose, the second frequency multiplier comprises a first receiving circuit, a second receiving circuit, and a load circuit, and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit.
In the same field of endeavor, Ben discloses, the second frequency multiplier comprises a first receiving circuit, a second receiving circuit ([0004]: “One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter.” i.e., each nonlinear element with its driven path is equated as first receiving circuit and second receiving circuit), and a load circuit ([0004]: The first and second branch signals combine at the summation node to form a combined signal.), and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit ([0004]: “The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal”).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Ginsburg by specifically providing the second frequency multiplier comprises a first receiving circuit, a second receiving circuit, and a load circuit, and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit, as taught by Ben for the purpose of achieving high harmonic rejection and sufficient output power in both modes to drive the mixer [0019].
Further, the combination of Ginsburg and Ben does not teach, a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1. In the same field of endeavor, Reynolds discloses, a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1 (for the fundamental and even-order harmonic components of a given FET, the combined effect of the other two FETs provide a short circuit to ground Vss whereas for the third harmonic component each FET provides a high impedance and hence all the third harmonic component flows across load resistor R if the RLC tank is tuned to the tripled frequency, [0034]… he effective voltage that develops at output OUT has a frequency that is three times the input signal frequency [0033]. i.e., for the frequency tripler (n=3, odd).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Ginsburg and Ben by specifically providing a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1, as taught by Reynolds for the purpose of efficient operation to prevent loss of power at any other harmonic other than the harmonic of interest [0006].
Regarding claim 3, the combination of Ginsburg, Ben and Reynolds teaches everything claimed as applied above (see claim 1), further Ginsburg discloses, wherein the first chip further comprises an output driver, the output driver is coupled to the output end of the first internal signal generator, and the output driver is configured to amplify the first local oscillator signal ([0027]-[0028]: The multiplexer 232 is coupled to the RFSYNTH 230 and the input buffer 236. If the radar SOC 200 is used as the slave radar SOC 104, the radar SOC 200 receives signals generated by the RFSYNTH of the master radar SOC 102 via the buffer 236. The multiplexer 232 is configurable to select between signals received in the input buffer 236 and signals generated by the RFSYNTH 230. The output buffer 238 is coupled to the multiplexer 232 and may be used to transmit signals selected by the multiplexer 232 to the input buffer of another radar SOC……[0032]-[003]: The output buffer 308 of the master radar SOC 102 is coupled to the input buffer 320 of the slave radar SOC 104. In some embodiments, the output buffer 318 of the slave radar SOC 104 and the input buffer 306 of the master radar SOC 102 are not coupled externally and are not used. The master multiplexer 312 is configured to select the output signal of the master RFSYNTH 302 in both normal mode and phase noise measurement mode. This output signal is sent to the slave radar SOC 104 via the master output buffer 308.)
Regarding claim 8, the combination of Ginsburg, Ben and Reynolds teaches everything claimed as applied above (see claim 1), in addition Ben discloses, wherein the second receiving circuit comprises a second differential circuit ([0004]-[0007]: second nonlinear branch that is driven by differential signal (i.e., differential receiving circuit), and the second differential circuit is configured to receive the second local oscillator signal ([0004]-[0007]: One illustrative dual-band transceiver embodiment includes: a phase lock loop (PLL), a dual-mode frequency multiplier having a switchable phase shifter, and a mixer. The PLL provides a PLL signal in a 10.5 GHz to 11.5 GHz frequency band), and output the second local oscillator signal to the load circuit ([0004]-[0007]: The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal).
Regarding claim 19, Ginsburg discloses,
A communication apparatus (Fig. 1; FMCW radar system 100), wherein:
the communication apparatus comprises a first chip (Fig. 3; master SOC 102) and a second chip (Fig. 3; slave SOC 104), a plurality of first antennas, and a plurality of second antennas ([0022]: an embodiment of the radar SOC 200 may have two transmit channels and four receive channels. A transmit channel includes a suitable transmitter and antenna. A receive channel includes a suitable receiver and antenna.);
the first chip comprises a first internal signal generator (Fig. 2; 230, Fig. 3; 302 and Para. [0026]: the radio frequency synthesizer (RFSYNTH) 230 including functionality to generate FMCW signals for transmission) and a first frequency multiplier (Fig. 2; 240, Fig. 3; 310) coupled to the first internal signal generator (Para. [0029]: The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208) and the second chip (Fig. 3; slave SOC 104) comprises a second internal signal generator (Fig. 3; 314) and a second frequency multiplier (Fig. 3; 322) coupled to the second internal signal generator (Fig. 3 shows clock multiplier 322 is coupled to the RFSYNTH 314);
an input end of the first receiving circuit is coupled to an output end of the first internal signal generator through an input/output pin between the first chip and the second chip, an input end of the second receiving circuit is coupled to an output end of the second internal signal generator ([0027]: If the radar SOC 200 is used as the slave radar SOC 104, the radar SOC 200 receives signals generated by the RFSYNTH of the master radar SOC 102 via the buffer 236. The multiplexer 232 is configurable to select between signals received in the input buffer 236 and signals generated by the RFSYNTH 230…..[0032]: . The output buffer 308 of the master radar SOC 102 is coupled to the input buffer 320 of the slave radar SOC 104.),
the first internal signal generator (Fig. 2; 230, Fig. 3; 302) is configured to generate a first local oscillator signal (Para. [0026]: The radio frequency synthesizer (RFSYNTH) 230 includes functionality to generate FMCW signals for transmission. In some embodiments, the RFSYNTH 230 includes a phase locked loop (PLL) with a voltage controlled oscillator (VCO), and a programmable ramp generator that is programmed by the control module 226.);
the first frequency multiplier (Fig. 2; 240, Fig. 3; 310) is configured to receive the first local oscillator signal, and perform frequency multiplication on the first local oscillator signal (Para. [0029]: coupled to the first internal signal generator, The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208);
the second internal signal generator (Fig. 3; 314) is configured to generate a second local oscillator signal (Para. [0026]: The radio frequency synthesizer (RFSYNTH) 230 includes functionality to generate FMCW signals for transmission. In some embodiments, the RFSYNTH 230 includes a phase locked loop (PLL) with a voltage controlled oscillator (VCO), and a programmable ramp generator that is programmed by the control module 226.); and
the second frequency multiplier (Fig. 3; 322) is configured to receive the first local oscillator signal by using the first receiving circuit, receive the second local oscillator signal by using the second receiving circuit ([0027]:The multiplexer 232 is configurable to select between signals received in the input buffer 236 and signals generated by the RFSYNTH 230), and perform frequency multiplication on the first local oscillator signal or the second local oscillator signal ([0029] The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208. In the radar system 100, the transmission signal for the master radar SOC 102 and the slave radar SOC 104 is generated by the RFSYNTH of the master radar SOC 102) and
the plurality of first antennas are coupled to a plurality of first phased array channels, respectively, and the plurality of second antennas are coupled to a plurality of second phased array channels, respectively ([0022]: “The radar SOC 200 may include multiple transmit channels 204 for transmitting FMCW signals and multiple receive channels 202 for receiving the reflected transmitted signals. Further, the number of receive channels may be larger than the number of transmit channels. For example, an embodiment of the radar SOC 200 may have two transmit channels and four receive channels. A transmit channel includes a suitable transmitter and antenna. A receive channel includes a suitable receiver and antenna”…[0029]: “The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208. In the radar system 100, the transmission signal for the master radar SOC 102 and the slave radar SOC 104 is generated by the RFSYNTH of the master radar SOC 102”). However, Ginsburg does not explicitly disclose, the second frequency multiplier comprises a first receiving circuit, a second receiving circuit, and a load circuit, and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit.
In the same field of endeavor, Ben discloses, the second frequency multiplier comprises a first receiving circuit, a second receiving circuit ([0004]: “One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter.” i.e., each nonlinear element with its driven path is equated as first receiving circuit and second receiving circuit), and a load circuit ([0004]: The first and second branch signals combine at the summation node to form a combined signal.), and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit ([0004]: “The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal”).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Ginsburg by specifically providing the second frequency multiplier comprises a first receiving circuit, a second receiving circuit, and a load circuit, and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit, as taught by Ben for the purpose of achieving high harmonic rejection and sufficient output power in both modes to drive the mixer [0019].
Further, the combination of Ginsburg and Ben does not teach, a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1. In the same field of endeavor, Reynolds discloses, a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1 (for the fundamental and even-order harmonic components of a given FET, the combined effect of the other two FETs provide a short circuit to ground Vss whereas for the third harmonic component each FET provides a high impedance and hence all the third harmonic component flows across load resistor R if the RLC tank is tuned to the tripled frequency, [0034]… he effective voltage that develops at output OUT has a frequency that is three times the input signal frequency [0033]. i.e., for the frequency tripler (n=3, odd).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Ginsburg and Ben by specifically providing a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1, as taught by Reynolds for the purpose of efficient operation to prevent loss of power at any other harmonic other than the harmonic of interest [0006].
Regarding claim 20, Ginsburg discloses,
A electronic device (Fig. 1; FMCW radar system 100), wherein the electronic device comprising a baseband chip ([0022]: The bandpass filter, VGA, and ADC of a receive channel may be collectively referred to as a baseband chain or baseband filter chain) and a multi-chip apparatus (Fig. 1; FMCW radar system 100), wherein:
the multi-chip apparatus comprises a first chip (Fig. 3; master SOC 102) and a second chip (Fig. 3; slave SOC 104), the first chip comprises a first internal signal generator (Fig. 2; 230, Fig. 3; 302 and Para. [0026]: the radio frequency synthesizer (RFSYNTH) 230 including functionality to generate FMCW signals for transmission) and a first frequency multiplier coupled to the first internal signal generator (Fig. 2; 240, Fig. 3; 310 and Para. [0029]: The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208) and the second chip (Fig. 3; slave SOC 104) comprises a second internal signal generator (Fig. 3; 314) and a second frequency multiplier (Fig. 3; 322) coupled to the second internal signal generator (Fig. 3 shows clock multiplier 322 is coupled to the RFSYNTH 314);
an input end of the first receiving circuit is coupled to an output end of the first internal signal generator through an input/output pin between the first chip and the second chip, an input end of the second receiving circuit is coupled to an output end of the second internal signal generator ([0027]: If the radar SOC 200 is used as the slave radar SOC 104, the radar SOC 200 receives signals generated by the RFSYNTH of the master radar SOC 102 via the buffer 236. The multiplexer 232 is configurable to select between signals received in the input buffer 236 and signals generated by the RFSYNTH 230…..[0032]: . The output buffer 308 of the master radar SOC 102 is coupled to the input buffer 320 of the slave radar SOC 104.),
the first internal signal generator (Fig. 2; 230, Fig. 3; 302) is configured to generate a first local oscillator signal (Para. [0026]: The radio frequency synthesizer (RFSYNTH) 230 includes functionality to generate FMCW signals for transmission. In some embodiments, the RFSYNTH 230 includes a phase locked loop (PLL) with a voltage controlled oscillator (VCO), and a programmable ramp generator that is programmed by the control module 226.);
the first frequency multiplier (Fig. 2; 240, Fig. 3; 310) is configured to receive the first local oscillator signal, and perform frequency multiplication on the first local oscillator signal (Para. [0029]: coupled to the first internal signal generator, The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208);
the second internal signal generator (Fig. 3; 314) is configured to generate a second local oscillator signal (Para. [0026]: The radio frequency synthesizer (RFSYNTH) 230 includes functionality to generate FMCW signals for transmission. In some embodiments, the RFSYNTH 230 includes a phase locked loop (PLL) with a voltage controlled oscillator (VCO), and a programmable ramp generator that is programmed by the control module 226.); and
the second frequency multiplier (Fig. 3; 322) is configured to receive the first local oscillator signal by using the first receiving circuit, receive the second local oscillator signal by using the second receiving circuit ([0027]:The multiplexer 232 is configurable to select between signals received in the input buffer 236 and signals generated by the RFSYNTH 230), and perform frequency multiplication on the first local oscillator signal or the second local oscillator signal ([0029] The clock multiplier 240 increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers 206, 208. In the radar system 100, the transmission signal for the master radar SOC 102 and the slave radar SOC 104 is generated by the RFSYNTH of the master radar SOC 102). However, Ginsburg does not explicitly disclose, the second frequency multiplier comprises a first receiving circuit, a second receiving circuit, and a load circuit, and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit.
In the same field of endeavor, Ben discloses, the second frequency multiplier comprises a first receiving circuit, a second receiving circuit ([0004]: “One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter.” i.e., each nonlinear element with its driven path is equated as first receiving circuit and second receiving circuit), and a load circuit ([0004]: The first and second branch signals combine at the summation node to form a combined signal.), and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit ([0004]: “The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal”).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Ginsburg by specifically providing the second frequency multiplier comprises a first receiving circuit, a second receiving circuit, and a load circuit, and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit, as taught by Ben for the purpose of achieving high harmonic rejection and sufficient output power in both modes to drive the mixer [0019].
Further, the combination of Ginsburg and Ben does not teach, a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1. In the same field of endeavor, Reynolds discloses, a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1 (for the fundamental and even-order harmonic components of a given FET, the combined effect of the other two FETs provide a short circuit to ground Vss whereas for the third harmonic component each FET provides a high impedance and hence all the third harmonic component flows across load resistor R if the RLC tank is tuned to the tripled frequency, [0034]… he effective voltage that develops at output OUT has a frequency that is three times the input signal frequency [0033]. i.e., for the frequency tripler (n=3, odd).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Ginsburg and Ben by specifically providing a resonance frequency of the load circuit is n times a frequency of the first local oscillator signal or a frequency of the second local oscillator signal, and n is an odd number greater than 1, as taught by Reynolds for the purpose of efficient operation to prevent loss of power at any other harmonic other than the harmonic of interest [0006].
Allowable Subject Matter
Claims 2, 4-7 and 9-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the closest prior arts, Ginsburg and Ben, whether taken alone or in combination, do not teach the following novel features:
“wherein the multi- chip apparatus further comprises a power splitter, the power splitter comprises a first output end and a second output end, an input end of the power splitter is coupled to the output end of the first internal signal generator, and the first output end and the second output end of the power splitter are respectively coupled to the first frequency multiplier and the second frequency multiplier”, combination with the other limitations in claim 1.
Regarding claim 4, the closest prior arts, Ginsburg and Ben, whether taken alone or in combination, do not teach the following novel features:
“The multi-chip apparatus wherein: the first receiving circuit comprises a conversion circuit and a first differential circuit, an input end of the conversion circuit is an input end of the first receiving circuit, two output ends of the conversion circuit are respectively coupled to two input ends of the first differential circuit, and output ends of the first differential circuit are output ends of the first receiving circuit; the conversion circuit is configured to convert the first local oscillator signal into differential signals; and the first differential circuit is configured to receive the differential signals, and output the differential signals to the load circuit”, combination with the other limitations in claim 1.
Dependent claims 5-7 are allowed as those inherit the allowable subject matter from claim 4.
Regarding claim 9, the closest prior arts, Ginsburg and Ben, whether taken alone or in combination, do not teach the following novel features:
“The multi-chip apparatus wherein the second differential circuit comprises a third MOS transistor and a fourth MOS transistor, a first end of the third MOS transistor and a first end of the fourth MOS transistor are two input ends of the second receiving circuit, a second end of the third MOS transistor and a second end of the fourth MOS transistor are grounded or connected to a second power supply, and a third end of the third MOS transistor and a third end of the fourth MOS transistor are output ends of the second receiving circuit”, combination with the other limitations in claim 1 and claim 8.
Dependent claim 10 is allowed as those inherit the allowable subject matter from claim 9.
Regarding claim 11, the closest prior arts, Ginsburg and Ben, whether taken alone or in combination, do not teach the following novel features:
“The multi-chip apparatus wherein the load circuit comprises a second transformer, one end of a primary coil of the second transformer is connected to a third power supply, the other end of the primary coil of the second transformer is an input end of the load circuit, and two ends of a secondary coil of the second transformer are output ends of the load circuit”, combination with the other limitations in claim 1.
Regarding claim 12, the closest prior arts, Ginsburg and Ben, whether taken alone or in combination, do not teach the following novel features:
“The multi-chip apparatus wherein the load circuit comprises a third transformer and a fifth MOS transistor, one end of a primary coil of the third transformer is coupled to a fourth power supply and a first end of the fifth MOS transistor, the other end of the primary coil of the third transformer is coupled to a third end of the fifth MOS transistor, a second end of the fifth MOS transistor is an input end of the load circuit, and two ends of a secondary coil of the third transformer are output ends of the load circuit, combination with the other limitations in claim 1.
Dependent claim 13 is allowed as those inherit the allowable subject matter from claim 12.
Regarding claim 14, the closest prior arts, Ginsburg and Ben, whether taken alone or in combination, do not teach the following novel features:
“The multi-chip apparatus wherein: the load circuit comprises a sixth MOS transistor, a seventh MOS transistor, and a first LC circuit, a first end of the sixth MOS transistor is coupled to a third end of the seventh MOS transistor, a second end of the sixth MOS transistor and a second end of the seventh MOS transistor are grounded or connected to a fifth power supply, a third end of the sixth MOS transistor is coupled to a first end of the seventh MOS transistor, and the first end of the sixth MOS transistor and the first end of the seventh MOS transistor are respectively two input ends of the load circuit; and two input ends of the first LC circuit are coupled to a sixth power supply, two output ends of the first LC circuit are respectively coupled to the third end of the sixth MOS transistor and the third end of the seventh MOS transistor, and the two output ends of the first LC circuit are two output ends of the load circuit”, combination with the other limitations in claim 1.
Dependent claim 15 is allowed as those inherit the allowable subject matter from claim 14.
Regarding claim 16, the closest prior arts, Ginsburg and Ben, whether taken alone or in combination, do not teach the following novel features:
“The multi-chip apparatus wherein: the load circuit comprises an eighth MOS transistor, a ninth MOS transistor, and a second LC circuit, a first end of the eighth MOS transistor is coupled to a third end of the ninth MOS transistor, a third end of the eighth MOS transistor is coupled to a first end of the ninth MOS transistor, and a second end of the eighth MOS transistor and a second end of the ninth MOS transistor are respectively two input ends of the load circuit; and two input ends of the second LC circuit are coupled to a seventh power supply, two output ends of the second LC circuit are respectively coupled to the third end of the eighth MOS transistor and the third end of the ninth MOS transistor, and the two output ends of the second LC circuit are two output ends of the load circuit”, combination with the other limitations in claim 1.
Dependent claim 17 is allowed as those inherit the allowable subject matter from claim 16.
Regarding claim 18, the closest prior arts, Ginsburg and Ben, whether taken alone or in combination, do not teach the following novel features:
“The multi-chip apparatus wherein: the first chip further comprises a plurality of first phased array channels and a first frequency mixer, and the plurality of first phased array channels are coupled to the first frequency multiplier through the first frequency mixer; and the second chip further comprises a plurality of second phased array channels and a second frequency mixer, and the plurality of second phased array channels are coupled to the second frequency multiplier through the second frequency mixer”, combination with the other limitations in claim 1.
Prior Art of the Record:
The prior art made of record not relied upon and considered pertinent to
Applicant’s disclosure:
US 20210099130: Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers.
US 10116290: The RF integrated circuit has a RF transceiver to transmit and receive RF signals. A frequency synthesizer (200) is coupled to the RF transceiver to perform frequency synthesis. The frequency synthesizer includes a local oscillator (LO) to generate a LO signal, a frequency doubler circuit coupled to the LO to double a frequency of the LO signal.
US 20210099130: Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GOLAM SOROWAR/Primary Examiner, Art Unit 2641
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