DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on by KANAMORI et al. 20170287928 applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANAMORI et al. 20170287928.
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Regarding claim 1, fig. 3 of KANAMORI (as shown above) discloses a semiconductor memory device comprising:
a cell substrate 200;
a mold structure ST including a plurality of gate electrodes Gen stacked on the cell substrate;
a channel structure (D/VC) penetrating the mold structure;
a string select line SSL2/SSL1 on the mold structure;
a string select channel structure SCP2/SCP1 penetrating the string select line and contacting the channel structure;
an anti-arcing contact 180 (inherently as such) penetrating the mold structure;
an insulating pattern 182 between the anti-arcing contact and the plurality of gate electrodes; and
an anti-arcing insulating pattern 200 penetrating the string select line and contacting a lower surface the anti-arcing contact 180, and
the lower surface of the anti-arcing contact is above the string select line (see fig. 3 above).
Regarding claim 2, fig. 3 of KANAMORI discloses wherein the anti- arcing contact is at an end of the string select line.
Regarding claim 3, fig. 3 of KANAMORI discloses further comprising: a stud 212; and a bit line BL on the stud, wherein the stud is on the string select channel structure without being on the anti-arcing insulating pattern.
Regarding claim 4, fig. 3 of KANAMORI discloses wherein the insulating pattern extends along a sidewall of the anti-arcing contact.
Regarding claim 5, fig. 3 of KANAMORI discloses wherein the cell substrate comprises a source layer, and a sidewall of a channel pattern of the channel structure is in contact with the source layer.
Regarding claim 6, fig. 3 of KANAMORI discloses wherein the cell substrate comprises a source layer, and a bottom surface of a channel pattern of the channel structure is in contact (indirectly) with the source layer.
Regarding claim 10, fig. 3 of KANAMORI discloses wherein the string select channel structure overlaps a part of the channel structure, and wherein the insulating pattern surrounds the anti-arcing contact and extends continuously in a vertical direction through the plurality of gate electrodes.
Regarding claim 11, fig. 3 of KANAMORI discloses wherein the string select channel structure comprises a filling pattern (pattern filled by 222), a channel pattern 222 on the filling pattern, and a channel insulating pattern 224 between the filling pattern and the string select line, and the channel pattern is in contact with the channel structure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over KANAMORI.
Regarding claim 9, KANAMORI discloses claim 1. KANAMORI does not discloses wherein the anti-arcing contact comprises a first portion and a second portion on the first portion, and a width of a top surface of the first portion is greater than a width of a top surface of the second portion.
However, the MPEP addresses changes in size, proportion, or shape in MPEP § 2144.04 (IV), which provides guidance on when such modifications may be considered patentably distinct. The key principle is that if a claimed device differs from prior art only in relative dimensions and would perform the same as the prior art device, it is not patentably distinct. This principle was established in Gardner v. TEC Syst., Inc., 725 F.2d 1338 (Fed. Cir. 1984), where the court held that mere recitation of relative dimensions does not confer patentability if the performance remains unchanged.
As such it would have been obvious to form a device comprising wherein the anti-arcing contact comprises a first portion and a second portion on the first portion, and a width of a top surface of the first portion is greater than a width of a top surface of the second portion in order to take into consideration of process variation causing dimensional variation.
Claims 8, 12-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over KANAMORI in view of Gwon et al. 20210287986.
Regarding claim 8, KANAMORI discloses claim 1, but does not discloses further comprising: a peripheral circuit board; a peripheral circuit element on the peripheral circuit board; and a peripheral circuit structure on the peripheral circuit board, wherein the peripheral circuit structure includes a wiring structure electrically connected to the peripheral circuit element, and the mold structure is between the cell substrate and the peripheral circuit structure.
However, fig. 1 of Gwon discloses a semiconductor memory device comprising:
a cell substrate 101/102/104;
a mold structure (structure above 101) including a plurality of gate electrodes 130 stacked on the cell substrate;
a channel structure CH penetrating the mold structure;
a string select line (bottom 130 - see bottom of par [0032] -the gate electrode 130 constituting the string select transistor and/or below a lower portion of the gate electrode 130 constituting the ground select transistor) on the mold structure;
a string select channel structure (layer of multiple CH in fig. 1) penetrating the string select line and contacting the channel structure;
an anti-arcing contact (286/165/172/174/and pad(above174) (inherently anti-arcing as charges are transfer through 165/172/174/and pad to 286 then to 276 then 272 and then to 201 which is substrate is ground – see GI in 201) penetrating the mold structure;
an insulating pattern 192/120 between the anti-arcing contact and the plurality of gate electrodes; and
an anti-arcing insulating pattern 118 penetrating the string select line and contacting the anti-arcing contact;
a peripheral circuit board (elements above 192 is a type of board); a peripheral circuit element 184 on the peripheral circuit board; and a peripheral circuit structure 176 on the peripheral circuit board, wherein the peripheral circuit structure includes a wiring structure 176 electrically connected to the peripheral circuit element 184, and the mold structure is between the cell substrate and the peripheral circuit structure.
In view of such teaching, it would have been obvious to form device further comprising: a peripheral circuit board; a peripheral circuit element on the peripheral circuit board; and a peripheral circuit structure on the peripheral circuit board, wherein the peripheral circuit structure includes a wiring structure electrically connected to the peripheral circuit element, and the mold structure is between the cell substrate and the peripheral circuit structure such as taught by Gwon in order to reduce area consumption.
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Regarding claim 12, fig. 3 of KANAMORI discloses a semiconductor memory device comprising:
a cell substrate 200 including a cell array region (region of fig. 3);
a mold structure ST including a plurality of gate electrodes GEn stacked on the cell array region, the plurality of gate electrodes being stacked;
a channel structure 180 penetrating the mold structure, the channel structure on the cell array region;
a string select line SSL2/SSL1 on the mold structure;
a string select channel structure SCP1/SCP2 penetrating the string select line and contacting (indirectly contacting) the channel structure;
an anti-arcing contact VC (inherently anti-arcing as electrons travel to 100 form VC) on the cell array region, the anti-arcing contact penetrating the mold structure, and
a structure of the anti-arcing contact being different from a structure of the channel structure; and
an insulating pattern DS between the anti-arcing contact and the plurality of gate electrodes,
wherein the anti-arcing contact overlaps the string select line in a direction from the cell substrate toward the mold structure, and
a lower surface of the anti-arcing contact is above the string select line.
KANAMORI does not disclose that the cell substrate including an extension region and does not disclose that the plurality of gate electrodes being stacked in a stepwise manner on the extension region and each including a connection region having a top surface exposed.
However, fig. 1A of Gwon discloses a semiconductor memory device comprising:
a cell substrate 101/012/104 including a cell array region CELL and an extension region PERI;
a mold structure (structure above 101) including a plurality of gate electrodes stacked on the cell array region, the plurality of gate electrodes being stacked in a stepwise manner on the extension region and each including a connection region having a top surface exposed (see top surface of fig. 1A);
a channel structure CH penetrating the mold structure, the channel structure on the cell array region;
a string select line on the mold structure;
a string select channel structure penetrating the string select line and contacting the channel structure;
an anti-arcing contact (286/165/172/174/and pad(above174) (inherently anti-arcing as charges are transfer through 165/172/174/and pad to 286 then to 276 then 272 and then to 201 which is substrate is ground – see GI in 201) on the cell array region, the anti-arcing contact penetrating the mold structure, and
a structure of the anti-arcing contact being different from a structure of the channel structure; and
an insulating pattern 192/120 between the anti-arcing contact and the plurality of gate electrodes.
As such it would have been obvious form a device of KANAMORI comprising the cell substrate including an extension region and does not disclose that the plurality of gate electrodes being stacked in a stepwise manner on the extension region and each including a connection region having a top surface exposed such as taught by Gwon in order to be able to form gate contact to the gate electrodes.
Regarding claim 13, KANAMORI discloses wherein the insulating pattern surrounds the anti-arcing contact and extends continuously in a vertical direction through the plurality of gate electrodes.
Regarding claim 14, fig. 3 of KANAMORI further comprising: an anti-arcing insulating pattern (all combination of insulating layers are anti-arcing insulating pattern) on the cell array region, wherein the anti-arcing insulating pattern penetrates the string select line and contacts the lower surface of the anti-arcing contact.
Regarding claim 15, fig. 1A of Gwon discloses further comprising: a cell contact 162 electrically connected to the connection region (region where 162 contact 130) of a corresponding one of the plurality of gate electrodes on the extension region, wherein the cell contact penetrates the mold structure.
As such it would have been obvious to form a device further comprising: a cell contact electrically connected to the connection region of a corresponding one of the plurality of gate electrodes on the extension region, wherein the cell contact penetrates the mold structure in order to electrical connection.
Regarding claim 17, fig. 3 of KANAMORI discloses further comprising: a plurality of string isolation structures (all isolation layer between SSL1 and SSL2 including 172, 210, 212, 200), wherein the string select line is among a plurality of string selecting lines in the semiconductor memory device, the plurality of string isolation structures isolate the plurality of string select lines, and the anti-arcing contact is between two of the plurality of string isolation structures adjacent to each other.
Claims 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over KANAMORI and Gwon in view of Choi et al. 20220285302.
Regarding claim 19 (see rejection of claim 1 above), figs. 1 and 3 of KANAMORI An electronic system comprising:
a main substrate 100;
a semiconductor memory device on the main substrate; and
wherein the semiconductor memory device includes a cell substrate 200, a mold structure ST, a channel structure, a string select line, a string select channel structure, an anti-arcing contact, an insulating pattern, an anti-arcing insulating pattern, and a plurality of cell contacts WL (see fig. 1),
the cell substrate includes a cell array region,
the mold structure includes a plurality of gate electrodes stacked on the cell array region,
the plurality of gate electrodes are stacked,
the channel structure penetrates the mold structure on the cell array region,
the string select line is on the mold structure,
the string select channel structure penetrates the string select line and contacts the channel structure,
the anti-arcing contact penetrates the mold structure on the cell array region,
the insulating pattern is between the anti-arcing contact and the plurality of gate electrodes,
the anti-arcing insulating pattern penetrates the string select line and contacts a lower surface of the anti-arcing contact, and the plurality of cell contacts electrically connected to the connection regions of the plurality of gate electrodes on the extension region, and the lower surface of the anti-arcing contact is above the string select line.
KANAMORI does not disclose that the cell substrate includes a controller electrically connected to the semiconductor memory device, an extension region, that the plurality of gate electrodes are stacked in a stepwise manner on the extension region and each include a connection region having a top surface exposed such that the plurality of gate electrodes respectively include connection regions.
However, fig. 1A of Gwon discloses an electronic system comprising:
a main substrate 201;
a semiconductor memory device on the main substrate; and
wherein
the semiconductor memory device includes a cell substrate 201, a mold structure, a channel structure, a string select line, a string select channel structure, an anti-arcing contact, an insulating pattern, an anti-arcing insulating pattern, (see rejection of claims 1 and 12 above) and a plurality of cell contacts (gate contacts 162 – fig. 1A),
the cell substrate includes a cell array region (top surface region for CELL) and an extension region (bottom surface region for PERI) , the mold structure includes a plurality of gate electrodes stacked on the cell array region,
the plurality of gate electrodes are stacked in a stepwise manner on the extension region and each include a connection region having a top surface exposed such that the plurality of gate electrodes respectively include connection regions (see fig. 1A – regions where 162s contact 130s),
the channel structure CH penetrates the mold structure on the cell array region,
the string select line is on the mold structure,
the string select channel structure (portion of CH for that layer of 130 for the select transistor) penetrates the string select line 130 (for the string select 130) and contacts the channel structure (portion of CH for that layer of 130 for the select transistor contact the whole CH),
the anti-arcing contact 165 penetrates the mold structure on the cell array region,
the insulating pattern 192/120 is between the anti-arcing contact and the plurality of gate electrodes,
the anti-arcing insulating pattern 118 penetrates the string select line and contacts the anti-arcing contact, and
the plurality of cell contacts 162 electrically connected to the connection regions of the plurality of gate electrodes on the extension region.
As such it would have been obvious to form a device of KANAMORI an extension region, that the plurality of gate electrodes are stacked in a stepwise manner on the extension region and each include a connection region having a top surface exposed such that the plurality of gate electrodes respectively include connection regions in order to produce region for making gate contacts to the plurality of gate electrodes.
KANAMORI and Gwon do not disclose of a controller electrically connected to the semiconductor memory device.
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However, fig. 16 of Choi discloses a controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.
In view of such teaching, it would have been obvious to form an electronic system of KANAMORI and Gwon further comprising of a controller electrically connected to the semiconductor memory device such as taught by Choi in order to be able to controller the semiconductor device.
Regarding claim 20, KANAMORI discloses wherein the anti-arcing insulating pattern has a single layer structure.
Regarding claim 21, KANAMORI discloses wherein the anti- arcing contact has a single layer structure, and the insulating pattern surrounds the anti-arcing contact and extends continuously in a vertical direction through the plurality of gate electrodes.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
