Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments, filed 3/9/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Takuma et al., JP2022104705A (hereinafter referred to as Takuma) and in view of Tonomura et al., US Patent 9270128 (hereinafter referred to as Tonomura) and in view of Fukuda US Patent 11450752 (hereinafter referred to as Fukuda). Argued below is Takuma’s “region separation structure 8” as the claimed trench separation structure with the details of the structure’s depth from Fukuda.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-14 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takuma et al., JP2022104705A (hereinafter referred to as Takuma) in view of Fukuda US Patent 11450752 (hereinafter referred to as Fukuda).
In regards to claim 1, Takuma teaches a semiconductor device (semiconductor equipment; [Title]) comprising: a semiconductor chip (semiconductor device 1; [Fig. 1]); a trench separation structure (region separation structure 8; [Pg. 62, Para. 10] & [Fig. 1]) which is formed in (implicit; [Fig. 1]) the semiconductor chip and demarcates a device region (internal region bounded by region separation structure 8; [Fig. 1]); a main transistor (power MISFET 9; [Fig. 23]) which is formed in (implicit; [Fig. 1]) the device region includes a first system transistor (internal transistor of MISFET 9 tied to gate G14; [Fig. 23]) generating a first system current and a second system transistor (internal transistor of MISFET 9 tied to gate G13; [Fig. 23]) connected in parallel to the first system transistor (implicit; [Fig. 23]),
[AltContent: textbox (1st System Transistor
with 1st System Current)][AltContent: arrow][AltContent: textbox (2nd System Transistor
with 2nd System Current)][AltContent: arrow][AltContent: arrow]
PNG
media_image1.png
153
34
media_image1.png
Greyscale
and generating a second system current independently of the first system transistor (implicit; [Fig. 23]), and which generates an output current (current IOUT; [Fig. 23]) including the first system current and the second system current (implicit because the summation of all 4 currents through the shown internal transistors is the total current IOUT; [Fig. 23]); a first system monitor transistor (internal transistor of MISFET 21 tied to gate G14; [Fig. 23]) which generates a first system monitor current that corresponds to the first system current; and a second system monitor transistor which generates a second system monitor current that corresponds to the second system current,
[AltContent: textbox (1st System Monitor Transistor
with 1st System Monitor Current)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (2nd System Monitor Transistor
with 2nd System Monitor Current)]
PNG
media_image2.png
140
162
media_image2.png
Greyscale
PNG
media_image1.png
153
34
media_image1.png
Greyscale
wherein each of the first system transistor and the second system transistor has a gate (gate G14 & G13; [Fig. 23]), the gate of the first system transistor being a first system gate that is configured to be controlled by a first gate signal (voltage of gate G14; [Fig. 23]), the gate of the second system transistor being a second system gate that is configured to be controlled by a second gate signal (voltage of gate G13; [Fig. 23]), the first and second gate signals being electrically independent from each other (individual control of the plurality of gate signals; [Pg. 84, Para. 9]), so that the first and second system gates are controlled separately (controlled in four ways; [Pg. 84, Para. 9]), and the first system transistor and the second system transistor each have a trench gate structure (first trench gate structure 60 and second trench gate structure 70; [Pg. 67, Para. 16]) formed in the device region (implicit; [Fig. 1]).
Takuma does not teach a depth of the trench gate structure being less than a depth of the trench separation structure.
Fukuda teaches a depth of the trench gate structure (separation trench 404; [Col. 45, Ln. 19-22]) (first trench gate structure 60 and second trench gate structure 70, Takuma) being less than a depth (DT1 ≤ DS; [Col. 45, Ln. 19-22]) of the trench separation structure (separation trench 404; [Col. 45, Ln. 19-22]) (region separation structure 8, Takuma).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Takuma in order to incorporate a depth of the trench gate structure being less than a depth of the trench separation structure as taught by Fukuda. The motivation for doing so would be to apply a known trench separation structure as a substitute for the region separation structure 8 as taught by Takuma.
In regards to claim 2, Takuma teaches wherein on/off control (voltage on gate G14; [Fig. 23]) of the first system monitor transistor is performed in conjunction with the first system transistor (implicit the upper gate of both MISFET 9 & 21 are joined together at G14; [Fig. 23]), and on/off control (voltage on gate G13; [Fig. 23]) of the second system monitor transistor is performed in conjunction with the second system transistor (implicit the second gate of both MISFET 9 & 21 are joined together at G13; [Fig. 23]).
In regards to claim 3, Takuma teaches wherein the first system monitor current is less than the first system current (Is:IOUT = 1:α; [Pg. 86, Para. 8]), and the second system monitor current is less than the second system current (The sense current needs to be less than the power current in order for the system to work correctly and not have the protection circuitry damaged. Therefore, α is a number larger than 1.).
In regards to claim 4, Takuma teaches wherein the first system monitor transistor is electrically connected to the first system transistor (implicit the upper gate of both MISFET 9 & 21 are joined together at G14; [Fig. 23]), and the second system monitor transistor is electrically connected to the second system transistor (implicit the second gate of both MISFET 9 & 21 are joined together at G13; [Fig. 23]).
In regards to claim 5, Takuma teaches wherein a drain of the first system monitor transistor is electrically connected to a drain of the first system transistor (implicit; [Fig. 23]), and a drain of the second system monitor transistor is electrically connected to a drain of the second system transistor (implicit; [Fig. 23]).
In regards to claim 6, Takuma teaches wherein a source of the first system monitor transistor is electrically separated from a source of the first system transistor (implicit because the source of MISFET 21 is tied to Vs instead of source electrode 12; [Fig. 23]), and a source of the second system monitor transistor is electrically separated from a source of the second system transistor (implicit because the source of MISFET 21 is tied to Vs instead of source electrode 12; [Fig. 23]).
In regards to claim 7, Takuma teaches wherein a source of the second system monitor transistor is electrically connected to a source (source of MISFET 21; [Fig. 23]) of the first system monitor transistor (implicit; [Fig. 23]).
In regards to claim 8, Takuma teaches wherein a gate of the first system monitor transistor is electrically connected to the first system gate of the first system transistor (implicit the upper gate of both MISFET 9 & 21 are joined together at G14; [Fig. 23]), and a gate of the second system monitor transistor is electrically connected to the second system gate of the second system transistor (implicit the second gate of both MISFET 9 & 21 are joined together at G13; [Fig. 23]).
[AltContent: textbox (1st System Transistor
with 1st System Current)]In regards to claim 9, Takuma teaches wherein the first system transistor outputs the first system current to a first system current path (implicit; [Fig. 23]); the second system transistor outputs the second system current to a second system current path (implicit; [Fig. 23]);
[AltContent: arrow][AltContent: textbox (2nd System Transistor
with 2nd System Current)][AltContent: arrow][AltContent: arrow]
PNG
media_image1.png
153
34
media_image1.png
Greyscale
the first system monitor transistor is electrically connected to the first system transistor, and outputs the first system monitor current to a first system monitor current path that is electrically independent of the first system current path (implicit; [Fig. 23]); and the second system monitor transistor is electrically connected to the second system transistor, and outputs the second system monitor current to a second system monitor current path that is electrically independent of the second system current path (implicit; [Fig. 23]).
[AltContent: textbox (2nd System Monitor Transistor
with 2nd System Monitor Current)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (1st System Monitor Transistor
with 1st System Monitor Current)]
PNG
media_image2.png
140
162
media_image2.png
Greyscale
PNG
media_image1.png
153
34
media_image1.png
Greyscale
In regards to claim 10, Takuma teaches further comprising: a monitor transistor (MISFET 21; [Fig. 23]) which includes the first system monitor transistor and the second system monitor transistor (implicit, Fig. 20 shows a breakdown of how the 4 gate transistor is a culmination of 4 individual transistors and how the system monitor transistors are within the monitor transistor; [Fig. 20 & 23]), and which generates an output monitor current including the first system monitor current and the second system monitor current.
In regards to claim 11, Takuma teaches wherein the main transistor is configured so that the first system transistor in an on state coexists with the second system transistor in an off state (individual control of the plurality of gate signals; [Pg. 84, Para. 9]), and the monitor transistor is configured so that the first system monitor transistor in an on state coexists with the second system monitor transistor in an off state (MISFET 21 is a gate division type; [Pg. 86, Para. 9]) (Examiner’s Note: Since MISFET 21 is like MISFET 9, the description of the gate control of MISFET 9 applies to MISFET 21.).
In regards to claim 12, Takuma teaches wherein the main transistor is configured so as to be changed in on-resistance (on-resistance RON; [Pg. 84, Para. 9]) by individually controlling (individual control of the plurality of gate signals; [Pg. 84, Para. 9]) the first system transistor and the second system transistor, and the monitor transistor is configured so as to be changed in on-resistance by individually controlling (individual control of the plurality of gate signals; [Pg. 84, Para. 9]) the first system monitor transistor and the second system monitor transistor (MISFET 21 is a gate division type; [Pg. 86, Para. 9]) (Examiner’s Note: Since MISFET 21 is like MISFET 9, the description of the gate control of MISFET 9 applies to MISFET 21.).
In regards to claim 13, Takuma teaches wherein the monitor transistor is configured so as to be changed (individual control of the plurality of gate signals; [Pg. 84, Para. 9]) in on-resistance (on-resistance RON; [Pg. 84, Para. 9]) in conjunction with the main transistor (MISFET 21 is a gate division type; [Pg. 86, Para. 9]) (Examiner’s Note: The gates of MISFET 9 & 21 are tied together. Therefore, the change in on-resistance is the same between the transistors.).
In regards to claim 14, Takuma teaches wherein the main transistor is controlled so that an on-resistance during an active clamp operation (active clamping circuit; [Pg. 61, Para. 6]) exceeds an on-resistance (raise the on-resistance; [Pg. 61, Para. 6]) during a normal operation, and the monitor transistor (MISFET 21 is a gate division type; [Pg. 86, Para. 9]) is controlled so that an on-resistance during the active clamp operation exceeds an on-resistance (raise the on-resistance; [Pg. 61, Para. 6]) during the normal operation (Examiner’s Note: The gates of MISFET 21 are tied directly to the gates of MISFET 9 and MISFET 21 is also a gate division type of transistor. Therefore, the on-resistance will be raised like what is taught of MISFET 9.).
In regards to claim 18, Takuma teaches wherein the first system transistor includes one or a plurality of first unit transistors which are systematized as an individually controlled object (the first system transistor is one transistor; [Fig. 23]), the second system transistor includes one or a plurality of second unit transistors which are systematized as an individually controlled object (the second system transistor is one transistor; [Fig. 23]), the first system monitor transistor includes one or a plurality of first unit monitor transistors which are systematized as an individually controlled object (the first system monitor transistor is one transistor; [Fig. 23]), and the second system monitor transistor includes one or a plurality of second unit monitor transistors which are systematized as an individually controlled object (the second system monitor transistor is one transistor; [Fig. 23]).
In regards to claim 19, Takuma teaches a semiconductor device (semiconductor equipment; [Title]) comprising: a semiconductor chip (semiconductor device 1; [Fig. 1]); a trench separation structure (region separation structure 8; [Pg. 62, Para. 10] & [Fig. 1]) which is formed in (implicit; [Fig. 1]) the semiconductor chip and demarcates a device region (internal region bounded by region separation structure 8; [Fig. 1]); a main transistor (power MISFET 9; [Fig. 23]) which is formed in (implicit; [Fig. 1]) the device region and includes a plurality of system transistors (a quantity of 4 internal transistors of power MISFET 9; [Fig. 20 & 23]) that are connected in parallel (implicit; [Fig. 23]) with one another and individually subjected to on/off control (individual gate connections G11-G14; [Fig. 23]) and each generate a system current (IOUT; [Fig. 23]), and which generates an output current including a plurality of the system currents (implicit, the individual internal transistors are in parallel and create 4 separate current paths; [Fig. 23]); and a monitor transistor (MISFET 21; [Fig. 23]) which includes at least one (qty of 4; [Fig. 20 & 23]) system monitor transistor generating a system monitor current that corresponds to at least one of the system currents (implicit, the individual internal transistors are in parallel and create 4 separate current paths; [Fig. 23]), wherein the plurality of system transistors each includes a gate (gates G11-G14; [Fig. 23]) that is a system gate, the plurality of system gates being electrically separated from one another (implicit; [Fig. 23]), and being configured to be controlled by a plurality of gate signals (voltages of G11-G14; [Fig. 23]), respectively, the plurality of gate signals being electrically independent from one another (individual control of the plurality of gate signals; [Pg. 84, Para. 9]), and the first system transistor and the second system transistor each have a trench gate structure (first trench gate structure 60 and second trench gate structure 70; [Pg. 67, Para. 16]) formed in the device region (implicit; [Fig. 1]).
Takuma does not teach a depth of the trench gate structure being less than a depth of the trench separation structure.
Fukuda teaches a depth of the trench gate structure (separation trench 404; [Col. 45, Ln. 19-22]) (first trench gate structure 60 and second trench gate structure 70, Takuma) being less than a depth (DT1 ≤ DS; [Col. 45, Ln. 19-22]) of the trench separation structure (separation trench 404; [Col. 45, Ln. 19-22]) (region separation structure 8, Takuma).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Takuma in order to incorporate a depth of the trench gate structure being less than a depth of the trench separation structure as taught by Fukuda. The motivation for doing so would be to apply a known trench separation structure as a substitute for the region separation structure 8 as taught by Takuma.
In regards to claim 20, Takuma teaches wherein the system monitor transistor generates each of the at least one system monitor current (Is:IOUT = 1:α; [Pg. 86, Para. 8]) in conjunction with one of the at least one system current corresponding thereto (implicit, Takuma teaches the gates of MISFET 9 & 21 being respectively tied to one another. Therefore, internal current paths will be ratios of one another; [Fig. 23]).
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takuma et al., JP2022104705A (hereinafter referred to as Takuma) in view of Fukuda US Patent 11450752 (hereinafter referred to as Fukuda) and in further view of Tonomura et al., US Patent 9270128 (hereinafter referred to as Tonomura).
In regards to claim 15, Takuma & Fukuda do not teach wherein the first system monitor transistor is provided so as to be mutually adjacent to one of or both of the first system transistor and the second system transistor, and the second system monitor transistor is provided so as to be mutually adjacent to one of or both of the first system transistor and the second system transistor.
Tonomura teaches wherein the first system monitor transistor (part of Area 166; [Fig. 12]) is provided so as to be mutually adjacent to one of or both of the first system transistor (another part of Area 166; [Fig. 12]) and the second system transistor (a third part of Area 166; [Fig. 12]), and the second system monitor transistor (gate wiring line 120; [Fig. 12]) is provided so as to be mutually adjacent to one of or both of the first system transistor and the second system transistor ([Col. 21, Ln. 31-34] & [Fig. 12]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified Takuma & Fukuda in order to incorporate wherein the first system monitor transistor is provided so as to be mutually adjacent to one of or both of the first system transistor and the second system transistor, and the second system monitor transistor is provided so as to be mutually adjacent to one of or both of the first system transistor and the second system transistor as taught by Tonomura. The motivation for doing so would be to apply a known method for building the transistor device.
In regards to claim 16, Takuma & Fukuda do not teach wherein the first system monitor transistor is provided so as to be mutually adjacent to the second system monitor transistor.
Tonomura teaches wherein the first system monitor transistor is provided so as to be mutually adjacent to the second system monitor transistor ([Col. 21, Ln. 31-34] & [Fig. 8 & 12]) (Examiner’s Note: The transistors are adjacent and within the box 5.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified Takuma & Fukuda in order to incorporate wherein the first system monitor transistor is provided so as to be mutually adjacent to the second system monitor transistor as taught by Tonomura. The motivation for doing so would be to apply a known method for building the transistor device.
In regards to claim 17, Takuma & Fukuda do not teach wherein the first system monitor transistor and the second system monitor transistor are provided in the device region together with the first system transistor and the second system transistor.
Tonomura teaches wherein the first system monitor transistor and the second system monitor transistor are provided in the device region together with the first system transistor and the second system transistor (box 5; [Fig. 8]) (Examiner’s Note: All of the transistors are in the protection FET circuit 5, which is in one box.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified Takuma & Fukuda in order to incorporate wherein the first system monitor transistor and the second system monitor transistor are provided in the device region together with the first system transistor and the second system transistor as taught by Tonomura. The motivation for doing so would be to apply a known method for building the transistor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMANTHA L FAUBERT whose telephone number is (703)756-1311. The examiner can normally be reached Monday - Friday 8AM - 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 5712701682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
SAMANTHA LYNETTE FAUBERT
Examiner
Art Unit 2836
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838