DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 5 (Fig. 6) for examination. Claims 1, 7-9, 16-18, 22-23 in the reply filed on 03/27/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-9, 17-18, 22-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by XIE et al. 20240357881.
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Regarding claim 1, figs. 3-4 and 7 of Xie discloses a display device, comprising:
a display area A for displaying an image, comprising a plurality of light emitting element arrays (array A2, in A1(S) and A1-A1(S)); and
a non-display area S in which an image is not displayed,
wherein the display area includes:
a first optical area A2 including a transmittable area A21 (optical element 200 (see fig. 2) on the display substrate 100 may at least partially overlap the element arrangement region A21),
a first optical bezel (A1(S)) area located outside of the first optical area, and
a normal area (A1 – A1(S)) located outside of the first optical bezel area,
wherein each of the plurality of light emitting element arrays includes a plurality of light emitting elements 31,
wherein the first optical area A2, the first optical bezel area A1(S), and the normal area (A1 – A1(S)) include a first light emitting element array, a second light emitting element array, and a third light emitting element array among the plurality of light emitting element arrays (see fig. 7), respectively, and
wherein an arrangement of a plurality of first light emitting elements included in the first light emitting element array (that of A2 - which is differently spaced) is different from at least one of an arrangement of a plurality of second light emitting elements included in the second light emitting element array (that of A1(S) - which is spaced closer than that of A2) or an arrangement of a plurality of third light emitting elements included in the third light emitting element array (that of (A1 – A1(S)) -which is spaced closer than that of A2).
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Regarding claim 17, figs. 3-4 and 7 of Xie discloses a display panel, comprising:
a display area including:
a first optical area,
a first optical bezel area located outside of the first optical area, and
a normal area located outside of the first optical bezel area; and
a non-display area in which an image is not displayed,
wherein the first optical area, the first optical bezel area, and the normal area include a plurality of first light emitting element arrays, a plurality of second light emitting element arrays, and a plurality of third light emitting element arrays, respectively (see rejection of claim 1 above for element matching),
wherein the first optical area includes a plurality of transmission areas (region between 31B light as there is not obstruction by 31B) in which cathode holes are formed (regions between 31B are holes between cathodes of different 31B - these regions are empty of cathodes and therefore are holes formed between cathodes),
wherein each of the plurality of first light emitting element arrays included in the first optical area includes a first light emitting element 31B having a first light emitting area, and
each of the plurality of second light emitting element arrays included in the first optical bezel area includes a second light emitting element 31 having a second light emitting area, and
wherein the first optical bezel area further includes a first subpixel circuit C12 configured to drive the first light emitting element (see figs. 4 and 7) and a second subpixel circuit configured to drive the second light emitting element (see fig. 7 configuration).
Regarding claim 22 (see rejection of claim 17 above), figs. 3-4 and 7 of Xie discloses a display panel, comprising:
a display area including: a first optical area including a transmittable area, a first optical bezel area located outside of the first optical area, and a normal area located outside of the first optical bezel area; and a non-display area in which an image is not displayed, wherein the first optical area and the first optical bezel area includes a plurality of first light emitting elements and a plurality of second light emitting elements, respectively, and wherein the first optical bezel area further includes a first subpixel circuit configured to drive the first light emitting element (see figs. 4 and 7 configurations).
Regarding claims 18 and 23, figs. 4 and 7 of Xie disclose further comprising an anode extension line41 for electrically connecting the first light emitting element in the first optical area to the first subpixel circuit in the first optical bezel area, wherein all or a portion of the anode extension line overlaps the first optical area, and includes a transparent material or includes a transparent line (par [0121]).
Regarding claim 7, fig. 7 of Xie discloses further comprising: a first subpixel circuit for driving a first light emitting element included in the first light emitting element array; a second subpixel circuit for driving a second light emitting element included in the second light emitting element array; and a third subpixel circuit for driving a third light emitting element included in the third light emitting element array, wherein the first light emitting element is disposed in the first optical area, and the first subpixel circuit is disposed in at least one of the first optical bezel area or the normal area, or both the first optical bezel area and the normal area.
Regarding claim 8, figs. 4 and 7 of Xie discloses further comprising an anode extension line electrically connecting the first light emitting element to the first subpixel circuit, wherein all or a portion of the anode extension line is disposed in the first optical area, and the anode extension line includes a transparent material.
Regarding claim 9, fig. 7 of Xie discloses wherein the second light emitting element and the second subpixel circuit are disposed in the first optical bezel area.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Xie.
Regarding claim 16, Xie discloses claim 7, but does not disclose of wherein the first subpixel circuit is configured to drive two or more first light emitting elements simultaneously.
However, it would have been obvious to form a device of Xie comprising wherein the first subpixel circuit is configured to drive two or more first light emitting elements simultaneously in order to form parallel circuit design which basic circuit configuration instead of series configuration.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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