DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 6, 8-9, and 11-12 of U.S. Patent No. 11526380 in view of KATIYAR further in view of Lee.
Instant Application
11526380 Patent
3. The method of claim 1, wherein the resource management unit communicates with at least one of a processor or the first memory for storing the configuration state of the operating system using a low-latency communication data link or a high-speed interface bus, or by being integrated with a same integrated circuit die as the processor.
2. The method of claim 1, wherein the resource management unit communicates with at least one of the processor or the first memory for obtaining the configuration state of the operating system using a low-latency communication data link or a high-speed interface bus, or by being integrated with a same integrated circuit die as the processor.
4. The method of claim 1, wherein processing the task associated with the resource comprises managing the resource to improve at least one of:a performance of the computing system; a security aspect of the computing system; or a processing of an overhead management activity of the computing system.
3. The method of claim 1, wherein processing the task associated with the resource comprises altering the resource to improve at least one of: a performance of the computing system; a security aspect of the computing system; or a processing of an overhead management activity of the computing system.
5. The method of claim 1, wherein identifying the resource in the stored data is based on at least one of memory usage, memory need, secondary memory usage, scheduling, process run queue, process wait queue, process priority data, process run- time remaining data, process scheduling data, or hypervisor or virtual machine activity.
6. The method of claim 1, wherein: identifying the resource identifies a hypervisor or a virtual machine in the second memory that is configured to use the resource to execute; and processing the task comprises modifying a clock rate of a component of the computing system based on the hypervisor or the virtual machine.
7. The method of claim 1, wherein the determined score is indicative of the resource or other resources used by the respective process.
8. The method of claim 7, further comprising detecting a first score associated with the first process or assigning a first score to the first process, the first score indicative of the resource or other resources used by the first process, and modifying the clock rate of the component based on the first score.
8. The method of claim 1, further comprising: determining a second score associated with a second respective process of the one or more processes of the computing system, the second score indicative of resources used by the second respective process.
9. The method of claim 8, further comprising detecting a second score associated with a second process of the computing system or assigning a second score to the second process, the second score indicative of resources used by the second process, and modifying the clock rate of the component based on the first score of the first process relative to the second score of the second process.
9. The method of claim 8, wherein modifying the clock rate of the component based on the determined score of the respective process is relative to the second determined score of the second respective process.
9. The method of claim 8, further comprising . . . modifying the clock rate of the component based on the first score of the first process relative to the second score of the second process.
11. The computing system of claim 10, wherein the first and second memory are a shared memory in which the instructions are stored.
11. The computing system of claim 10, wherein the first and second memory are a shared memory in which the instructions are stored.
12. The computing system of claim 10, wherein the resource management unit is comprised within a system-on-chip, an application-specific integrated circuit, or an application-specific standard product.
12. The computing system of claim 10, wherein the resource management unit is comprised within a system-on-chip, an application-specific integrated circuit, or an application-specific standard product.
As per claim 1, 380 Patent teaches:
A method of managing a computing system, the method comprising:
determining, by a resource management unit having access to a first memory, a configuration state of an operating system in the first memory, the configuration state comprising a process queue of one or more processes to be executed (380 Patent Claim 1);
storing, by the resource management unit, data relating to the configuration state of the operating system into a second memory (380 Patent Claim 1);
identifying, in the stored data and by the resource management unit, a resource of the computing system to be used by the one or more processes in the process queue when executed (380 Patent, claim 1), the identifying the resource identifies at least one of a hypervisor or a virtual machine in the computing system that is configured to use the resource to execute (380 Patent, claim 6); and
processing, by the resource management unit, a task associated with the resource (380 Patent claim 1);
380 Patent does not expressly teach:
the processing of the task comprising modifying a clock rate of a component of the computing system based on at least one of a status of the hypervisor or the virtual machine, metrics associated with a respective process of the one or more processes relative to the resource or other resources used by the computing system, a determined score associated with the respective process, or process priority data.
However, KATIYAR discloses:
the processing of the task comprising modifying a clock rate of a component of the computing system based on at least one of a status of the hypervisor or the virtual machine, metrics associated with a respective process of the one or more processes relative to the resource or other resources used by the computing system, a determined score associated with the respective process, or process priority data (KATIYAR, [0010]-- modifying a clock rate . . . based on . . . metrics associated with a respective process . . . relative to the resource or other resources used by the computing system can be load);
Both KATIYAR and 380 Patent pertain to the art of resource management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use KATIYAR’s method to modify clocks because it is well-known in the art that as the clock frequency increases power consumption of the CPU increases and as the clock frequency decreases the power consumption of the CPU decreases. Power consumption can be efficiently managed this way.
As per claim 2, 380 Patent/KATIYAR teaches:
The method of claim 1 (see rejection on claim 1).
further comprising: detecting a transaction event of the operating system, and wherein determining a configuration state is responsive to the detection of the transaction event.
380 Patent/KATIYAR does not expressly teach:
further comprising: detecting a transaction event of the operating system, and wherein determining a configuration state is responsive to the detection of the transaction event.
However, Lee discloses:
further comprising: detecting a transaction event of the operating system, and wherein determining a configuration state is responsive to the detection of the transaction event (Lee, [0150]).
Both Lee and 380 Patent/KATIYAR pertain to the art of resource management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Lee’s method detect transaction event and determine a configuration state because …
As per claim 6, 380 Patent/KATIYAR teaches:
The method of claim 1 (See rejection on claim 1), wherein modifying the clock rate of component of the computing system comprises modifying the clock rate of at least one of a processor, the first memory, the second memory, or another clock-controlled component of the computing system (KATIYAR, [0151]).
As per claim 10, see rejection on claim 1.
As per claim 13, see rejection on claim 3.
As per claim 14, see rejection on claim 2.
As per claim 15, see rejection on claim 4.
As per claim 16, see rejection on claim 5.
As per claim 17, see rejection on claim 6.
As per claim 18, see rejection on claim 7.
As per claim 19, see rejection on claim 8.
As per claim 20, see rejection on claim 9.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter.
Claims 1-8, and 10-19 are rejected under 35 U.S.C. 101.
As per claim 1, the claim recites a series of step, therefore is a process.
The claim recites the limitation of “determining, by a resource management unit having access to a first memory, a configuration state of an operating system in the first memory, the configuration state comprising a process queue of one or more processes to be executed . . . identifying, in the stored data and by the resource management unit, a resource of the computing system to be used by the one or more processes in the process queue when executed . . . identifies at least one of a hypervisor or a virtual machine in the computing system that is configured to use the resource to execute”. These limitations, as drafted, are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
The limitation of “storing, by the resource management unit, data relating to the configuration state of the operating system into a second memory . . . ” is a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). “processing . . . “ does not require any particular application of the recited “processing...” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. (see MPEP 2106.05(f)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
As discussed above, “storing . . .”, amounts to generic transmission which is considered to be insignificant extra solution activity (MPEP 2106.05(g). ). “processing . . . “ does not require any particular application of the recited “processing...” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. (see MPEP 2106.05(f)). The claim is ineligible.
As per claim 2, see rejection on claim 1. “detecting a transaction event of the operating system . . . determining a configuration state is responsive to the detection of the transaction event” are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
As per claim 3, see rejection on claim 1. “the resource management unit communicates . . . storing the configuration state of the operating system using a low-latency communication data link or a high-speed interface bus, or by being integrated with a same integrated circuit die as the processor” amounts to generic transmission which is considered to be insignificant extra solution activity (MPEP 2106.05(g). The claim is ineligible.
As per claim 4, see rejection on claim 1. “managing the resource to improve at least one of: a performance of the computing system; a security aspect of the computing system; or a processing of an overhead management activity of the computing system” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See US 2021/0141435 . The claim is ineligible.
As per claim 5, see rejection on claim 1. “identifying the resource in the stored data is based on at least one of memory usage, memory need, secondary memory usage, scheduling, process run queue, process wait queue, process priority data, process run- time remaining data, process scheduling data, or hypervisor or virtual machine activity” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See US 10680969. The claim is ineligible.
As per claim 6, see rejection on claim 1. “modifying the clock rate of component of the computing system comprises modifying the clock rate of at least one of a processor, the first memory, the second memory, or another clock-controlled component of the computing system” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See US 2021/0141435 . The claim is ineligible.
As per claim 7, see rejection on claim 1. “the determined score is indicative of the resource or other resources used by the respective process” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See US 2016/0380905. The claim is ineligible.
As per claim 8, “determining . . . “ are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
As per claim 10, see rejection on claim 1.
As per claim 11, see rejection on claim 10. “the first and second memory are a shared memory in which the instructions are stored” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See US 12470263. The claim is ineligible.
As per claim 12, see rejection on claim 10. “. . . a system,-on-chip . . . product” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See US 2021/0141435. The claim is ineligible.
As per claim 13, see rejection on claim 3.
As per claim 14, see rejection on claim 2.
As per claim 15, see rejection on claim 4.
As per claim 16, see rejection on claim 5.
As per claim 17, see rejection on claim 6.
As per claim 18, see rejection on claim 7.
As per claim 19, see rejection on claim 8.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1, it is not clear what “the configuration state comprising a process queue of one or more processes to be executed” should be construed as. [0027] of spec recites “The OS configuration state 114 captured into the OS configuration state database 116 may include information associated with a process run queue, a process wait queue, active devices, and virtual memory tables.” This appears to suggest that the state is info associated with queues. Information associated with a queue is different from a queue. A state is “the particular condition that someone or something is in at a specific time.” How can a state comprise a queue? In this rejection, it is assumed that configuration state comprising info relating to queues.
As per claim 10, see rejection on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, 8, 10, 12, 14-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2017/0205863) (hereinafter Lee) in view of Quinn et al (US 10680969) (hereinafter Quinn) further in view of KATIYAR et al (US 2021/0141435 ) (hereinafter KATIYAR).
As per claim 1, Lee teaches:
A method of managing a computing system, the method comprising:
determining, by a resource management unit having access to a first memory, a configuration state of an operating system in the first memory, the configuration state comprising a process queue of one or more processes to be executed (Lee, [0151]—under BRI, a process queue of one or more processes can be including load/store queue information, cache hit/miss information, memory latency information, and memory bandwidth information, a configuration state of an operating system can be information incoming from the various cores including load/store queue information, cache hit/miss information, memory latency information, and memory bandwidth information; a 1st memory can be configuration storage 1780);
storing, by the unit, data relating to the configuration state of the operating system into a second memory (Lee, [0151]—under BRI, a 2nd memory can be the memory that characteristics buffer is at, data relating to the configuration state can be cache hit/miss information) ;
Lee does no expressly teach:
identifying, in the stored data and by the unit, a resource of the computing system to be used by the one or more processes in the process queue when executed, the identifying the resource identifies at least one of a hypervisor or a virtual machine in the computing system that is configured to use the resource to execute; and
processing, by the resource management unit, a task associated with the resource, the processing of the task comprising modifying a clock rate of a component of the computing system based on at least one of a status of the hypervisor or the virtual machine, metrics associated with a respective process of the one or more processes relative to the resource or other resources used by the computing system, a determined score associated with the respective process, or process priority data;
However, Quinn discloses:
identifying, in the stored data and by the resource management unit, a resource of the computing system to be used by the one or more processes in the process queue when executed (Not Required: The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met), the identifying the resource identifies at least one of a hypervisor or a virtual machine in the computing system that is configured to use the resource to execute (Quinn, claim 13—under BRI, at least one of a hypervisor or a virtual machine in the computing system that is configured to use the resource to execute can be the respective VM);
Both Quinn and Lee pertain to the art of resource management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Quinn’s method to identify VM that use the resources to execute because it is well-known in the art that knowing resources used by all processes allow the system to add/remove resources to improve efficiencies.
Lee/Quinn does no expressly teach:
processing, by the resource management unit, a task associated with the resource, the processing of the task comprising modifying a clock rate of a component of the computing system based on at least one of a status of the hypervisor or the virtual machine, metrics associated with a respective process of the one or more processes relative to the resource or other resources used by the computing system, a determined score associated with the respective process, or process priority data;
However, KATIYAR discloses:
processing, by the resource management unit, a task associated with the resource, the processing of the task comprising modifying a clock rate of a component of the computing system based on at least one of a status of the hypervisor or the virtual machine, metrics associated with a respective process of the one or more processes relative to the resource or other resources used by the computing system, a determined score associated with the respective process, or process priority data (KATIYAR, [0010]-- modifying a clock rate . . . based on . . . metrics associated with a respective process . . . relative to the resource or other resources used by the computing system can be load);
Both KATIYAR and Lee/Quinn pertain to the art of resource management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use KATIYAR’s method to modify clocks because it is well-known in the art that as the clock frequency increases power consumption of the CPU increases and as the clock frequency decreases the power consumption of the CPU decreases. Power consumption can be efficiently managed this way.
As per claim 2, Lee/Quinn/KATIYAR teaches:
The method of claim 1 (see rejection on claim 1) , further comprising: detecting a transaction event of the operating system (Lee, [0150]—under BRI, detecting a transaction event of the operating system can be discovering that characteristic information to a power controller 1750 is provided) and wherein determining a configuration state is responsive to the detection of the transaction event (Lee, [0150]).
As per claim 4, Lee/Quinn/KATIYAR teaches:
The method of claim 1 (see rejection on claim 1), wherein processing the task associated with the resource comprises managing the resource to improve at least one of:
a performance of the computing system (KATIYAR, [0010]—under BRI, improving performance can be increasing clock rate); a security aspect of the computing system; or a processing of an overhead management activity of the computing system.
As per claim 5, Lee/Quinn/KATIYAR teaches:
The method of claim 1 (see rejection on claim 1), wherein identifying the resource in the stored data is based on at least one of memory usage, memory need, secondary memory usage, scheduling, process run queue, process wait queue, process priority data, process run- time remaining data, process scheduling data, or hypervisor or virtual machine activity (Quinn, claim 13—under BRI, virtual machine activity can be there is a placement request for a virtual machine (VM) to be launched).
As per claim 6, Lee/Quinn/KATIYAR teaches:
The method of claim 1 (See rejection on claim 1), wherein modifying the clock rate of component of the computing system comprises modifying the clock rate of at least one of a processor (KATIYAR, [0151]), the first memory, the second memory, or another clock-controlled component of the computing system.
As per claim 8, Lee/Quinn/KATIYAR teaches:
The method of claim 1 (See rejection on claim 1), further comprising:
determining a second score associated with a second respective process of the one or more processes of the computing system, the second score indicative of resources used by the second respective process (mere duplication of parts has no patentable significance unless a new and unexpected result is produced. See MPEP 2144.04).
As per claim 10, see rejection on claim 1.
As per claim 12, Lee/Quinn/KATIYAR teaches:
The computing system of claim 10 (see rejection on claim 10), wherein the resource management unit is comprised within a system-on-chip, an application-specific integrated circuit(KATIYAR, [0111]) , or an application-specific standard product.
As per claim 14, see rejection on claim 2.
As per claim 15, see rejection on claim 4.
As per claim 16, see rejection on claim 5.
As per claim 17, see rejection on claim 6.
As per claim 19, see rejection on claim 8.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee/Quinn/KATIYAR as applied above, and further in view of Chien et al (US 2018/0095792) (hereinafter Chien).
As per claim 3, Lee/Quinn/KATIYAR teaches:
The method of claim 1 (see rejection on claim 1), wherein the resource management unit communicates with at least one of a processor or the first memory for storing the configuration state of the operating system using a low-latency communication data link or a high-speed interface bus (Lee, [0151]—a bus exists in order to store states), or by being integrated with a same integrated circuit die as the processor.
Lee/Quinn/KATIYAR does not expressly teach:
Wherein the bus is a high-speed interface bus;
However, Chien discloses:
Wherein the bus is a high-speed interface bus (Chien, Abstract);
Both Chien and Lee/Quinn/KATIYAR pertain to the art of resource management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Chien’s method to use a high-speed bus because it is well-known in the art that a high-speed interface bus faster data transfer that improves throughput.
As per claim 13, see rejection on claim 3.
Claims 7 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee/Quinn/KATIYAR as applied above, further in view of Wang et al (US 2016/0380905) (hereinafter Wang).
As per claim 7, Lee/Quinn/KATIYAR teaches:
The method of claim 1 (see rejection on claim 1).
Lee/Quinn/KATIYAR does not expressly teach:
wherein the determined score is indicative of the resource or other resources used by the respective process.
However, Wang discloses:
wherein the determined score is indicative of the resource or other resources used by the respective process (Wang, [0039]) .
Both Wang and Lee/Quinn/KATIYAR pertain to the art of resource management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Wang’s method to use a score indicative of a resources because it is well-known in the art that resource allocation weight score that indicates the relative priority or importance of the resource node allows the system to plan resource allocation efficiently.
As per claim 18, see rejection on claim 7.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee/Quinn/KATIYAR as applied above, and further in view of Delfeld et al (US 12470263) (hereinafter Delfeld).
As per claim 11, Lee/Quinn/KATIYAR teaches:
The computing system of claim 10 (see rejection on claim 10).
Lee/Quinn/KATIYAR does not expressly teach:
wherein the first and second memory are a shared memory in which the instructions are stored.
However, Delfeld discloses:
wherein the first and second memory are a shared memory in which the instructions are stored (Delfeld, col 49, ll36).
Both Delfeld and Lee/Quinn/KATIYAR pertain to the art of memory access.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Delfeld’s method to use a shared instruction memory because it is well-known in the art that shared cache offers benefits including reduced data redundancy, lower main memory traffic, and better resource utilization, and improving overall performance for many applications by avoiding slow trips to RAM.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2011/0088038 teaches a method of using process affinity scores.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vital Pierre can be reached at (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHARLIE SUN/Primary Examiner, Art Unit 2198