DETAILED ACTION
This action is responsive to U.S. Patent Application No. 18/471,875 filed on 21 September 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election of the Species 2 embodiment in the reply filed on 22 January 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Accordingly, claim 8 is withdrawn from further consideration, as it is drawn to a nonelected species.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed features:
Of claim 4: “and the via protection layer encloses a circumference of the TSV protruding from the first inactive face of the first semiconductor chip”
Of claim 5: “wherein the molding layer is in contact with all side surfaces of the first semiconductor chip and all side surfaces of the via protection layer”
Of claim 13: “wherein a cross-sectional area of the TSV on the first active face is larger than a cross-sectional area of the TSV on the first inactive face”
Of claim 18: “and the via protection layer encloses a circumference of the TSV protruding from the first inactive face of the first semiconductor chip”
Of claim 19: “the molding layer is in contact with all side surfaces of the first semiconductor chip and all side surfaces of the via protection layer”
Of claim 19: “and the via protection layer encloses a circumference of the TSV protruding from the first inactive face of the first semiconductor chip”
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 2 is objected to because of the following informalities:
Claim 2 contains a typo and should read: “wherein a surface extending from a side surface of the first semiconductor chip is the same as a surface extending from a side surface of the via protection layer.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 16, 17, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.’” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313 (Fed. Cir. 2014)).
Regarding claim 1: claim 1 states, in relevant part, “a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure by at least partially penetrating the via protection layer, the first substrate, and the first active face . . . .” It is unclear whether the phrase “at least” modifies either (1) the “partially penetrating” limitation (i.e., such that the claim may encompass more than “partially penetrating,” such as fully penetrating), (2) the layers that are penetrated (i.e., at least the via protection layer, the first substrate, and the first active face), or (3) both the “partially penetrating” limitation and the layers that are penetrated. For the purposes of examination, the relevant phrase has been interpreted in accordance with interpretation (2).
Claims 2-7 and 9-15 are also rejected under 112(b) as they depend from base claim 1.
Regarding claim 3: claim 3 states, in relevant part, “wherein an overlap shape of the first semiconductor chip with respect to the upper surface of the connection structure is same as an overlap shape of the via protection layer with respect to the connection structure.” It is unclear precisely what claim 3 encompasses, including whether Applicant is claiming a configuration wherein two features overlap as well as what features overlap such that the “overlap shape” may be properly understood. Particularly unclear is whether the “overlap shape” limitation refers to (1) a configuration wherein the first semiconductor chip and via protection layer overlap the connection structure, but not necessarily wherein the first semiconductor chip and via protection layer overlap, or (2) a configuration wherein the first semiconductor chip and via protection layer overlap the connection structure, and further wherein the first semiconductor chip and via protection layer overlap. For the purposes of examination, the relevant phrase has been interpreted such that Applicant is claiming that the first semiconductor chip and via protection layer overlap with the connection structure, further wherein (2) the first semiconductor chip and via protection layer overlap.
Claims 4, 7, 9, and 10 are also rejected under 112(b) as they depend from base claim 3.
Regarding claim 16: claim 16 states, in relevant part, “a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure by at least partially penetrating the via protection layer, the first substrate, and the first active face . . . .” It is unclear whether the phrase “at least” modifies either (1) the “partially penetrating” limitation (i.e., such that the claim may encompass more than “partially penetrating,” such as fully penetrating), (2) the layers that are penetrated (i.e., at least the via protection layer, the first substrate, and the first active face), or (3) both the “partially penetrating” limitation and the layers that are penetrated. For the purposes of examination, the relevant phrase has been interpreted in accordance with interpretation (2).
Further regarding claim 16: claim 16 states, in relevant part, “wherein an overlap shape of the first semiconductor chip with respect to the upper surface of the connection structure is same as an overlap shape of the via protection layer with respect to the connection structure.” It is unclear precisely what claim 16 encompasses, including whether Applicant is claiming a configuration wherein two features overlap as well as what features overlap such that the “overlap shape” may be properly understood. Particularly unclear is whether the “overlap shape” limitation refers to (1) a configuration wherein the first semiconductor chip and via protection layer overlap the connection structure, but not necessarily wherein the first semiconductor chip and via protection layer overlap, or (2) a configuration wherein the first semiconductor chip and via protection layer overlap the connection structure, and further wherein the first semiconductor chip and via protection layer overlap. For the purposes of examination, the relevant phrase has been interpreted such that Applicant is claiming that the first semiconductor chip and via protection layer overlap with the connection structure, further wherein (2) the first semiconductor chip and via protection layer overlap.
Claims 17 and 18 are also rejected under 112(b) as they depend from base claim 16.
Regarding claim 17: claim 17 states, in relevant part, “wherein at least a portion of an upper surface of the structure protection layer, excluding an overlap area overlapping with the via protection layer, is in direct contact with the molding layer.” It is unclear precisely what claim 17 encompasses, including whether Applicant is claiming a configuration wherein two features overlap, as well as what features overlap such that the “overlap area overlapping with the via protection layer” may be properly understood. Particularly unclear is whether the “overlap area” refers to (1) the via protection layer, (2) the connection structure, (3) the via protection layer, (4) the first semiconductor chip, (5) the TSV, (6) the second semiconductor chip, (8) the conductive post, (9) the structure protection layer, etc. For the purposes of examination, the relevant phrase has been interpreted such that Applicant is claiming that the via protection layer and the structure protection layer overlap, and that the area in which they overlap to defines the overlap area of claim 17.
Claim 18 is also rejected under 112(b) as it depends from base claim 17.
Regarding claim 19: claim 19 states, in relevant part, “a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure by at least partially penetrating the via protection layer, the first substrate, and the first active face . . . .” It is unclear whether the phrase “at least” modifies either (1) the “partially penetrating” limitation (i.e., such that the claim may encompass more than “partially penetrating,” such as fully penetrating), (2) the layers that are penetrated (i.e., at least the via protection layer, the first substrate, and the first active face), or (3) both the “partially penetrating” limitation and the layers that are penetrated. For the purposes of examination, the relevant phrase has been interpreted in accordance with interpretation (2).
Further regarding claim 19: claim 19 states, in relevant part, “wherein an overlap shape of the first semiconductor chip with respect to the upper surface of the connection structure is same as an overlap shape of the via protection layer with respect to the connection structure.” It is unclear precisely what claim 19 encompasses, including whether Applicant is claiming a configuration wherein two features overlap as well as what features overlap such that the “overlap shape” may be properly understood. Particularly unclear is whether the “overlap shape” limitation refers to (1) a configuration wherein the first semiconductor chip and via protection layer overlap the connection structure, but not necessarily wherein the first semiconductor chip and via protection layer overlap, or (2) a configuration wherein the first semiconductor chip and via protection layer overlap the connection structure, and further wherein the first semiconductor chip and via protection layer overlap. For the purposes of examination, the relevant phrase has been interpreted such that Applicant is claiming that the first semiconductor chip and via protection layer overlap with the connection structure, further wherein (2) the first semiconductor chip and via protection layer overlap.
Claim 20 is also rejected under 112(b) as it depends from base claim 19.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 11, 12, 14, and 16-19 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by U.S. Patent Publication No. 2022/0093524 (filed Dec. 6, 2021) (hereinafter “Lin”).
Regarding independent claim 1, Lin discloses: A semiconductor package (FIG. 44, chip package 309, [0763]) comprising:
a connection structure (FIG. 44, interposer 551, [0693]);
a via protection layer on the connection structure (FIG. 44, underfill 564, i.e., polymer layer, [0695]);
a first semiconductor chip on the via protection layer (FIG. 44, e.g., centrally depicted semiconductor chip 100, [0695]) and including a first substrate having a first active face and a first inactive face opposite to each other (FIGS. 34D/44, depicting wherein the semiconductor chip 100 has a semiconductor substrate 2 including a first active face, e.g., a face of the semiconductor substrate 2 below the top surface of the semiconductor substrate 2, and further including a first inactive face, e.g., a bottom surface of the semiconductor substrate 2, [0665]), and the first semiconductor chip including a first back end of line (BEOL) layer on the first active face (FIGS. 34D/44, depicting wherein the semiconductor chip 100 includes a first BEOL layer on the top surface of the semiconductor substrate 2, e.g., the layer below the bonding layer 52 but above the bottom surface of the semiconductor substrate 2);
a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure by at least partially penetrating the via protection layer, the first substrate, and the first active face (FIG. 44, depicting a TSV 157 configured to electrically connect the semiconductor chip 100 to the interposer 551, by at least partially penetrating each of the underfill 564, the semiconductor substrate 2, and the face of the semiconductor substrate 2 below the top surface of the semiconductor substrate 2, [0665]);
a second semiconductor chip on the first semiconductor chip (FIG. 44, e.g., logic IC chip 326, [0718]) and electrically connected to the first semiconductor chip (FIG. 44, depicting wherein the logic IC chip 326 is electrically connected to the semiconductor chip 100), the second semiconductor chip including a second substrate having a second active face and a second inactive face opposite to each other (FIG. 44, disclosing wherein the logic IC chip 326 comprises a semiconductor substrate, and further depicting wherein the logic IC chip 326 includes a second active face, e.g., a face of the semiconductor substrate of the logic IC chip 326 below the top surface of semiconductor substrate of the logic IC chip 326, and further including a second inactive face, e.g., a top surface of the silicon substrate of the logic IC chip 326, [0276]), and the second semiconductor chip including a second BEOL layer on the second active face (FIG. 44, depicting wherein the logic IC chip 326 includes a second BEOL layer on the bottom surface of the semiconductor substrate of the logic IC chip 326, e.g., the layer above the bonding layer 52 but below the top surface of the logic IC chip 326);
a conductive post configured to electrically connect the second semiconductor chip and the connection structure with each other (FIG. 44, depicting a TSV 157 configured to electrically connect the logic IC chip 326 and the interposer 551); and
a molding layer filling a space between an upper surface of the connection structure and the second semiconductor chip, and the molding layer enclosing the conductive post (FIG. 44, depicting a polymer layer 92/192, further depicting wherein the polymer layer 92/192 filling a space between an upper surface of the interposer 551 and the logic IC chip 326, further depicting wherein the polymer layer 92/192 encloses the TSV 157 electrically connecting the logic IC chip 326 and the interposer 551, [0676]).
Regarding claim 2, Lin further discloses wherein a surface extending from a side surface of the first semiconductor chip is same as a surface extending from a side surface of the via protection layer (FIG. 44, depicting wherein the underfill 564 extends from a side surface of the semiconductor chip 100).
Regarding claim 3, Lin further discloses wherein an overlap shape of the first semiconductor chip with respect to the upper surface of the connection structure is same as an overlap shape of the via protection layer with respect to the connection structure (FIG. 44, depicting wherein in the region where the semiconductor chip 100 overlaps the upper surface of the interposer 551, the overlap shapes of the semiconductor chip 100 and the portion of the underfill 564 overlapping the semiconductor chip 100 on the upper surface of the interposer 551 are the same).
Regarding claim 4, Lin further discloses wherein the via protection layer includes an insulation material, and the via protection layer encloses a circumference of the TSV protruding from the first inactive face of the first semiconductor chip (FIG. 44, depicting wherein the underfill 564 encloses a circumference of the TSV 157 protruding from the bottom surface of the semiconductor substrate 2; [0767]: “The ninth type of chip package 309 may further include (1) an underfill 564, i.e., polymer layer, between each of its fourth type of semiconductor chips 100”).
Regarding claim 5, Lin further discloses wherein the molding layer is in contact with all side surfaces of the first semiconductor chip and all side surfaces of the via protection layer (FIG. 44, depicting wherein the polymer layer 92 is in contact with all side surfaces of the semiconductor chip 100 and all side surfaces of the underfill 564).
Regarding claim 6, Lin further discloses wherein the via protection layer includes curable polymer (FIG. 44, [0767]: “The ninth type of chip package 309 may further include (1) an underfill 564, i.e., polymer layer, between each of its fourth type of semiconductor chips 100”; [0765]: “Referring to FIG. 44, the ninth type of chip package 309 for the first alternative may include a polymer layer 92, such as molding compound, epoxy-based material or polyimide, filled into multiple gaps each between neighboring two of its fourth type of semiconductor chips 100 and second type of vertical-through-via (VTV) connectors 467.”).
Regarding claim 7, Lin further discloses wherein the first inactive face of the first semiconductor chip faces the via protection layer (FIG. 44, depicting wherein the bottom surface of the semiconductor substrate 2 faces the underfill 564).
Regarding claim 11, Lin further discloses wherein a thickness of the via protection layer is greater than or equal to a thickness of the first semiconductor chip in a vertical direction (FIG. 44, depicting wherein a thickness of the underfill 564 is greater than a thickness of the semiconductor chip 100).
Regarding claim 12, Lin further discloses a first bonding pad on a surface of the first semiconductor chip (FIG. 44, e.g., copper layer 24 on a surface of the semiconductor chip 100, [0652]); and a second bonding pad on a surface of the second semiconductor chip (FIG. 44, e.g., copper layer 24 on a surface of the logic IC chip 326), wherein the first bonding pad and the second bonding pad are diffusion bonded to each other to define an integrated bonding pad (FIG. 44, depicting wherein the copper layers are bonded and thus form an “integrated bonding pad”, [0764]).
Moreover, to the extent claim 12 claims process limitations, the Examiner respectfully notes that claim 12 is directed to a product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. MPEP § 2113(I) (quoting In re Thorpe 777 F.2d 695, 698 (Fed. Cir. 1985)). Moreover, “because validity is determined based on the requirements of patentability, a patent is invalid if a product made by the process recited in a product-by-process claim is anticipated by or obvious from prior art products, even if those prior art products are made by different processes.” MPEP § 2113(I) (quoting Amgen Inc. v. F. Hoffmann-La Roche Ltd., 580 F.3d 1340, 1370 n. 14 (Fed. Cir. 2009).
In the instant case, Lin anticipates the product of claim 12. Moreover, the claimed process step wherein “wherein the first bonding pad and the second bonding pad are diffusion bonded” does not appear to impart or imply any distinctive structural characteristics to the final semiconductor package device, and the claimed semiconductor package device product is capable of definition other than by the process steps by which it is made. See MPEP § 2113(I) (citing In re Garnero, 412 F.2d 276 (C.C.P.A. 1979) and In re Nordt Dev. Co., 881 F.3d 1371, 1375-76 (Fed. Cir. 2018)). Accordingly, the claimed process step wherein “wherein the first bonding pad and the second bonding pad are diffusion bonded” has not been given any patentable weight, insofar as claim 12 claims a process, technique, or steps of diffusion bonding the bonding pads.
Regarding claim 14, Lin further discloses the connection structure includes a redistribution structure (FIGS. 37/44, e.g., dielectric layer 585 and interconnection metal layers 27, [0693]), the connection structure includes a redistribution line pattern (FIGS. 37/44, e.g., the part of the interconnection metal layers 27 further from the dielectric layer 585) and a redistribution via (FIGS. 37/44, e.g., the part of the interconnection metal layers 27 closest to the dielectric layer 585), and the redistribution via has a tapered shape which narrows in a direction towards the via protection layer (FIGS. 37/44, depicting wherein the part of the interconnection metal layers 27 closest to the dielectric layer 585 has a tapered shape which narrows in a direction toward the underfill 564).
Regarding independent claim 16, Lin discloses: A semiconductor package (FIG. 44, chip package 309, [0763]) comprising:
a connection structure (FIG. 44, interposer 551, [0693]);
a via protection layer on the connection structure (FIG. 44, underfill 564, i.e., polymer layer, [0695]);
a first semiconductor chip on the via protection layer (FIG. 44, e.g., centrally depicted semiconductor chip 100, [0695]) and including a first substrate having a first active face and a first inactive face opposite to each other (FIGS. 34D/44, depicting wherein the semiconductor chip 100 has a semiconductor substrate 2 including a first active face, e.g., a face of the semiconductor substrate 2 below the top surface of the semiconductor substrate 2, and further including a first inactive face, e.g., a bottom surface of the semiconductor substrate 2, [0665]), and the first semiconductor chip including a first back end of line (BEOL) layer on the first active face (FIGS. 34D/44, depicting wherein the semiconductor chip 100 includes a first BEOL layer on the top surface of the semiconductor substrate 2, e.g., the layer below the bonding layer 52 but above the bottom surface of the semiconductor substrate 2);
a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure by at least partially penetrating the via protection layer, the first substrate, and the first active face (FIG. 44, depicting a TSV 157 configured to electrically connect the semiconductor chip 100 to the interposer 551, by at least partially penetrating each of the underfill 564, the semiconductor substrate 2, and the face of the semiconductor substrate 2 below the top surface of the semiconductor substrate 2, [0665]);
a second semiconductor chip on the first semiconductor chip (FIG. 44, e.g., logic IC chip 326, [0718]) and electrically connected to the first semiconductor chip (FIG. 44, depicting wherein the logic IC chip 326 is electrically connected to the semiconductor chip 100), the second semiconductor chip including a second substrate having a second active face and a second inactive face opposite to each other (FIG. 44, disclosing wherein the logic IC chip 326 comprises a semiconductor substrate, and further depicting wherein the logic IC chip 326 includes a second active face, e.g., a face of the semiconductor substrate of the logic IC chip 326 below the top surface of semiconductor substrate of the logic IC chip 326, and further including a second inactive face, e.g., a top surface of the silicon substrate of the logic IC chip 326, [0276]), and the second semiconductor chip including a second BEOL layer on the second active face (FIG. 44, depicting wherein the logic IC chip 326 includes a second BEOL layer on the bottom surface of the semiconductor substrate of the logic IC chip 326, e.g., the layer above the bonding layer 52 but below the top surface of the logic IC chip 326);
a conductive post configured to electrically connect the second semiconductor chip and the connection structure with each other (FIG. 44, depicting a TSV 157 configured to electrically connect the logic IC chip 326 and the interposer 551);
a molding layer filling a space between an upper surface of the connection structure and the second semiconductor chip, and the molding layer enclosing the conductive post (FIG. 44, depicting a polymer layer 92/192, further depicting wherein the polymer layer 92/192 filling a space between an upper surface of the interposer 551 and the logic IC chip 326, further depicting wherein the polymer layer 92/192 encloses the TSV 157 electrically connecting the logic IC chip 326 and the interposer 551, [0676]); and
a structure protection layer between the first semiconductor chip and the connection structure, and the structure protection layer covering a surface of the connection structure adjacent the molding layer (FIG. 44, e.g., dielectric layer 112 between the interposer 551 and the semiconductor chip 100, the dielectric layer 112 covering the surface of the interposer 551, [0693]),
wherein an overlap shape of the first semiconductor chip with respect to the upper surface of the connection structure is same as an overlap shape of the via protection layer with respect to the upper surface of the connection structure (FIG. 44, depicting wherein in the region where the semiconductor chip 100 overlaps the upper surface of the interposer 551, the overlap shapes of the semiconductor chip 100 and the portion of the underfill 564 overlapping the semiconductor chip 100 on the upper surface of the interposer 551 are the same).
Regarding claim 17, Lin further discloses wherein at least a portion of an upper surface of the structure protection layer, excluding an overlap area overlapping with the via protection layer, is in direct contact with the molding layer (FIG. 44, depicting wherein at least a portion, e.g., the bottom portion of the polymer layer 192, directly contacts the dielectric layer 112, excluding an overlap area of the).
Regarding claim 18, Lin further discloses wherein the via protection layer includes an insulation material, and the via protection layer encloses a circumference of the TSV protruding from the first inactive face of the first semiconductor chip (FIG. 44, depicting wherein the underfill 564 encloses a circumference of the TSV 157 protruding from the bottom surface of the semiconductor substrate 2; [0767]: “The ninth type of chip package 309 may further include (1) an underfill 564, i.e., polymer layer, between each of its fourth type of semiconductor chips 100”).
Regarding independent claim 19, Lin further discloses: A semiconductor package (FIG. 44, chip package 309, [0763]) comprising:
a connection structure (FIG. 44, interposer 551, [0693]);
a via protection layer on the connection structure (FIG. 44, underfill 564, i.e., polymer layer, [0695]);
a first semiconductor chip on the via protection layer (FIG. 44, e.g., centrally depicted semiconductor chip 100, [0695]) and including a first substrate having a first active face and a first inactive face opposite to each other (FIGS. 34D/44, depicting wherein the semiconductor chip 100 has a semiconductor substrate 2 including a first active face, e.g., a face of the semiconductor substrate 2 below the top surface of the semiconductor substrate 2, and further including a first inactive face, e.g., a bottom surface of the semiconductor substrate 2, [0665]), and the first semiconductor chip including a first back end of line (BEOL) layer on the first active face (FIGS. 34D/44, depicting wherein the semiconductor chip 100 includes a first BEOL layer on the top surface of the semiconductor substrate 2, e.g., the layer below the bonding layer 52 but above the bottom surface of the semiconductor substrate 2);
a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure by at least partially penetrating the via protection layer, the first substrate, and the first active face (FIG. 44, depicting a TSV 157 configured to electrically connect the semiconductor chip 100 to the interposer 551, by at least partially penetrating each of the underfill 564, the semiconductor substrate 2, and the face of the semiconductor substrate 2 below the top surface of the semiconductor substrate 2, [0665]);
a second semiconductor chip on the first semiconductor chip (FIG. 44, e.g., logic IC chip 326, [0718]) and electrically connected to the first semiconductor chip (FIGS. 3C/4D, depicting wherein the logic IC chip 326 is electrically connected to the semiconductor chip 100), the second semiconductor chip including a second substrate having a second active face and a second inactive face opposite to each other (FIG. 44, disclosing wherein the logic IC chip 326 comprises a semiconductor substrate, and further depicting wherein the logic IC chip 326 includes a second active face, e.g., a face of the semiconductor substrate of the logic IC chip 326 below the top surface of semiconductor substrate of the logic IC chip 326, and further including a second inactive face, e.g., a top surface of the silicon substrate of the logic IC chip 326, [0276]), and the second semiconductor chip including a second BEOL layer on the second active face (FIG. 44, depicting wherein the logic IC chip 326 includes a second BEOL layer on the bottom surface of the semiconductor substrate of the logic IC chip 326, e.g., the layer above the bonding layer 52 but below the top surface of the logic IC chip 326);
a conductive post configured to electrically connect the second semiconductor chip and the connection structure with each other (FIG. 44, depicting a TSV 157 configured to electrically connect the logic IC chip 326 and the interposer 551); and
a molding layer filling a space between an upper surface of the connection structure and the second semiconductor chip, and the molding layer enclosing the conductive post (FIG. 44, depicting a polymer layer 92, further depicting wherein the polymer layer 92 filling a space between an upper surface of the interposer 551 and the logic IC chip 326, further depicting wherein the polymer layer 92 encloses the TSV 157 electrically connecting the logic IC chip 326 and the interposer 551, [0676]),
wherein an overlap shape of the first semiconductor chip with respect to the upper surface of the connection structure is same as an overlap shape of the via protection layer with respect to the connection structure (FIG. 44, depicting wherein in the region where the semiconductor chip 100 overlaps the upper surface of the interposer 551, the overlap shapes of the semiconductor chip 100 and the portion of the underfill 564 overlapping the semiconductor chip 100 on the upper surface of the interposer 551 are the same),
the molding layer is in contact with all side surfaces of the first semiconductor chip and all side surfaces of the via protection layer (FIG. 44, depicting wherein the polymer layer 92 is in contact with all side surfaces of the semiconductor chip 100 and all side surfaces of the underfill 564), and
wherein the via protection layer includes an insulation material, and the via protection layer encloses a circumference of the TSV protruding from the first inactive face of the first semiconductor chip (FIG. 44, depicting wherein the underfill 564 encloses a circumference of the TSV 157 protruding from the bottom surface of the semiconductor substrate 2; [0767]: “The ninth type of chip package 309 may further include (1) an underfill 564, i.e., polymer layer, between each of its fourth type of semiconductor chips 100”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 10, 13, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of U.S. Patent Publication No. 2011/0183464 (filed Jan. 26, 2011) (hereinafter “Takahashi”).
Regarding claim 9, does not specifically disclose wherein a first end surface of the TSV protruding from the first inactive face is at a same level as a second surface of the via protection layer, and the second surface is opposite to a first surface of the via protection layer that is in contact with the first inactive face.
In the same field of endeavor, Takahashi discloses a semiconductor package device including a through-silicon via (TSV) (FIGS. 3G/3H, TSVs 203, [0026]) configured to electrically connect a first semiconductor chip to a connection structure (FIGS. 3G/3H, depicting wherein the TSVs 203 electrically connect IC die 2 218 to substrate 301, [0033]). Regarding the TSV configuration, in [0009], Takahashi states: “Since the TSV wafer is supported by the second carrier wafer during bonding of the singulated IC die or wafer, warpage/bow is significantly reduced which reduces the contact resistance of the joints, and as a result improves circuit performance and reliability of singulated stacked IC die generated by singulation (e.g. sawing) of the stacked TSV wafer comprising electronic article.” Takahashi further states in [0031]: “Metallic joints are not formed at this step. As described below, the CDF enables heat pressing to form an underfill layer and provides bonding in a single assembly step.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed chip package of Lin by substituting the TSV configuration of Takahashi in order to improve circuit reliability and performance, as well as minimize process steps required to connect various chips.
Moreover, substitution would result in a configuration wherein a first end surface of the TSV protruding from the first inactive face is at a same level as a second surface of the via protection layer, and the second surface is opposite to a first surface of the via protection layer that is in contact with the first inactive face (Lin FIG. 44; Takahashi FIGS. 3G/3H; depicting wherein the TSVs 203 of Takahashi, substituted for the TSVs 157, uppermost dielectric 112, metal contacts 563, and metal pads 6b/micropillars 34 of Lin, would result in a configuration wherein an end surface of the TSVs 203 are at a same level as a second surface of the underfill 564, wherein the second surface of the underfill 564 is opposite a first surface of the underfill 564 that is in contact with the bottom surface of the semiconductor substrate 2).
Regarding claim 10, Lin in view of Takahashi further discloses wherein a surface of the molding layer is at a same level as the first end surface and the second surface (Lin FIG. 44; Takahashi FIGS. 3G/3H; depicting wherein the polymer layer 92/192 includes a surface, e.g., the bottom surface of the polymer layer 192, that would be at a same level as an end surface of the TSVs 203, which are at a same level as a second surface of the underfill 564, wherein the second surface of the underfill 564 is opposite a first surface of the underfill 564 that is in contact with the bottom surface of the semiconductor substrate 2).
Regarding claim 13, Lin does not specifically disclose wherein a cross- sectional area of the TSV on the first active face is larger than a cross-sectional area of the TSV on the first inactive face.
In the same field of endeavor, Takahashi discloses a semiconductor package device including a through-silicon via (TSV) (FIGS. 3G/3H, TSVs 203, [0026]) configured to electrically connect a first semiconductor chip to a connection structure (FIGS. 3G/3H, depicting wherein the TSVs 203 electrically connect IC die 2 218 to substrate 301, [0033]). Regarding the TSV configuration, in [0009], Takahashi states: “Since the TSV wafer is supported by the second carrier wafer during bonding of the singulated IC die or wafer, warpage/bow is significantly reduced which reduces the contact resistance of the joints, and as a result improves circuit performance and reliability of singulated stacked IC die generated by singulation (e.g. sawing) of the stacked TSV wafer comprising electronic article.” Takahashi further states in [0031]: “Metallic joints are not formed at this step. As described below, the CDF enables heat pressing to form an underfill layer and provides bonding in a single assembly step.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed chip package of Lin by substituting the TSV configuration of Takahashi in order to improve circuit reliability and performance, as well as minimize process steps required to connect various chips.
Moreover, substitution would result in a configuration wherein a cross-sectional area of the TSV on the first active face is larger than a cross-sectional area of the TSV on the first inactive face (Lin FIG. 44; Takahashi FIGS. 3G/3H; depicting wherein the TSVs 203 are shaped such that the cross-sectional area of the TSVs 203 on the first active face, e.g., a face of the semiconductor substrate 2 below the top surface of the semiconductor substrate 2 would be larger than the cross-sectional area of the TSVs 203 on the first inactive face, e.g., a bottom surface of the semiconductor substrate 2).
Regarding claim 15, Lin does not specifically disclose wherein a thickness of the via protection layer in a vertical direction is in a range of 3 μm to 20 μm.
In the same field of endeavor, Takahashi discloses a semiconductor package device including a through-silicon via (TSV) (FIGS. 3G/3H, TSVs 203, [0026]) configured to electrically connect a first semiconductor chip to a connection structure (FIGS. 3G/3H, depicting wherein the TSVs 203 electrically connect IC die 2 218 to substrate 301, [0033]), and further discloses a via protection layer (FIGS. 3G/3H, e.g., CDF film 321, [0031]). Regarding the thickness of the CDF film 321, in [0031], Takahashi states: “The thickness of the CDF 213 is generally calculated to fill nominal underfill gap area with an additional thickness amount to reflect a manufacturability margin. For example, if the underfill gap is 10 μm, the thickness of the CDF can be from 15 to 20 μm.” Thus, noted in Takahashi, the thickness of an underfill is a result-effective variable for optimizing underfill gap size and manufacturability.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of the underfill 564, identified by Takahashi as a result-effective variable. One of ordinary skill in the art would have had a reasonable expectation of success to arrive at a underfill 564 thickness ranging from 3 μm to 20 μm in order to achieve a desired balance between underfill gap and manufacturability as disclosed in Takahashi in [0031]. See MPEP § 2144.05 (“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.”) (quoting In re Aller, 220 F.2d 454, 456 (C.C.P.A. 1955)).
Furthermore, the Applicant has not presented persuasive evidence that the claimed range is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 20, Lin further discloses a first bonding pad on a surface of the first semiconductor chip (FIG. 44, e.g., copper layer 24 on a surface of the semiconductor chip 100, [0652]); and a second bonding pad on a surface of the second semiconductor chip (FIG. 44, e.g., copper layer 24 on a surface of the logic IC chip 326), wherein the first bonding pad and the second bonding pad are diffusion bonded to each other to define an integrated bonding pad (FIG. 44, depicting wherein the copper layers are bonded and thus form an “integrated bonding pad”, [0764]), and the via protection layer includes a curable polymer (FIG. 44, [0767]: “The ninth type of chip package 309 may further include (1) an underfill 564, i.e., polymer layer, between each of its fourth type of semiconductor chips 100”; [0765]: “Referring to FIG. 44, the ninth type of chip package 309 for the first alternative may include a polymer layer 92, such as molding compound, epoxy-based material or polyimide, filled into multiple gaps each between neighboring two of its fourth type of semiconductor chips 100 and second type of vertical-through-via (VTV) connectors 467.”).
Lin does not specifically disclose wherein a first end surface of the TSV protruding from the first inactive face is at a same level as a second surface of the via protection layer, the second surface is opposite to a first surface of the via protection layer that is in contact with the first inactive face.
In the same field of endeavor, Takahashi discloses a semiconductor package device including a through-silicon via (TSV) (FIGS. 3G/3H, TSVs 203, [0026]) configured to electrically connect a first semiconductor chip to a connection structure (FIGS. 3G/3H, depicting wherein the TSVs 203 electrically connect IC die 2 218 to substrate 301, [0033]). Regarding the TSV configuration, in [0009], Takahashi states: “Since the TSV wafer is supported by the second carrier wafer during bonding of the singulated IC die or wafer, warpage/bow is significantly reduced which reduces the contact resistance of the joints, and as a result improves circuit performance and reliability of singulated stacked IC die generated by singulation (e.g. sawing) of the stacked TSV wafer comprising electronic article.” Takahashi further states in [0031]: “Metallic joints are not formed at this step. As described below, the CDF enables heat pressing to form an underfill layer and provides bonding in a single assembly step.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed chip package of Lin by substituting the TSV configuration of Takahashi in order to improve circuit reliability and performance, as well as minimize process steps required to connect various chips.
Moreover, substitution would result in a configuration wherein a first end surface of the TSV protruding from the first inactive face is at a same level as a second surface of the via protection layer, and the second surface is opposite to a first surface of the via protection layer that is in contact with the first inactive face (Lin FIG. 44; Takahashi FIGS. 3G/3H; depicting wherein the TSVs 203 of Takahashi, substituted for the TSVs 157, uppermost dielectric 112, metal contacts 563, and metal pads 6b/micropillars 34 of Lin, would result in a configuration wherein an end surface of the TSVs 203 are at a same level as a second surface of the underfill 564, wherein the second surface of the underfill 564 is opposite a first surface of the underfill 564 that is in contact with the bottom surface of the semiconductor substrate 2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos.: 2020/0343223; 2020/0168528.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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