DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 21-31 and 33-40 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 21-31 and 33-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (NPL document entitled “Binary Neural Network with 16 Mb RRAM Macro Chip for Classification and Online Training”), Frazao et al (NPL: “Weighted Convolutional Neural Networks Ensemble”) and Jung et al (NPL: “Design of a large-scale storage class RRAM system”).
For claim 21, Yu teaches a system (BNN implemented on a 16Mb RRAM macro chip, Figure 1 and Abstract), comprising:
a host (although not explicitly stated, a host is required to input the handwritten digit images to the binary neural network of Figure 1, as understood by Figures 5 and 8); and
a memory device (Figure 1) comprising a plurality of memory banks (16 blocks, Figure 1), each memory bank of the plurality of memory banks comprising:
one or more memory arrays (each block has two 512x1024 arrays, Figure 1 and §II); and
a controller on a same chip as the one or more memory arrays (the portion of Figure 1 which performs the computations of sigmoid activation and subtraction, see Figure 8 and §III), wherein the controller is configured to operate a neural network (BNN classifier, Abstract) on a portion of data representing an image, sound, or emotion (images of a handwritten digits cropped to 20x20 pixels, Figure 5), wherein the controller is configured to operate the neural network using instructions that are based at least in part on one or more commands received from the host (e.g., selection of I/O Width to 8-bit, Table 1 and §II; loading pre-trained weight matrices into array, §III) via a control bus between the controller and the host (Dobus, as understood by examination of Figure 1) each command of the one or more commands associated with an address of the one or more memory arrays (as understood by examination of the Figures), and wherein the neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data (redundant and massively parallel networks, §III) .
Yu fails to teach:
a controller on a same chip as the one or more memory arrays, wherein the controller is configured to operate each neural network using instructions;
wherein each neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data.
However, Frazao teaches combining the output probabilities of a plurality of parallel neural networks trained differently from one another (§1) to create a weighted neural network (Abstract, Figure 4).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to classify handwritten digits using a weighted combination of a plurality of Yu’s BNN classifiers, each BNN classifier being independently trained and on separate chips from one another in order to improve classification results (Abstract).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of invention.
The combination of Yu and Frazao as cited above fails to teach a single chip as claimed.
However, Jung teaches macro level parallelism for RRAM (§4.2.3) such that a plurality of dies can be packaged into a single chip (Figure 11).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement the plurality of Yu’s BNN classifiers on a single chip instead of a plurality of chips in order to provide a high level of internal parallelism (§4.2.3).
Furthermore, the particular known technique (multiple RRAM dies in a single chip) was recognized as part of the ordinary capabilities of one skilled in the art, as evidenced by Jung.
For claim 22, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 21 and Yu further teaches:
each neural network is configured to include processing in memory (PIM) architecture (§II, Figures 1 and 8).
For claim 23, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 21 and Yu further teaches:
each neural network includes sensing circuitry including a sense amplifier (each block has a corresponding sense amplifier, §II) and a compute component (that which performs subtraction and activation in Figure 8).
For claim 24, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 21 and Frazao further teaches:
each neural network is independently trained (§3.1).
For claim 25, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 21 and Jung further teaches:
each neural network is configured to simultaneously receive the instructions to operate on the portion of data (each die corresponding to Yu’s BNN is capable of simultaneous reception of host instructions, §4.2.3).
For claim 26, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 21 and Yu further teaches:
each neural network is configured to operate in a fixed point or binary weighted network (binary, Abstract).
For claim 27, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 21 and Yu further teaches:
each neural network is a single-bit network (single bit classification output, Abstract).
For claim 28, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 21 and further teaches:
the controller comprises control logic (that which performs subtraction and activation in Yu’s Figure 8; “command interface and control logic” of Jung’s Figure 11), sequencers (plurality of 3-stage gates in Yu’s Figure 1, decoders of Jung’s Figure 11), and timing circuitry (data buffer of Yu, I/O logic of Jung’s Figure 11).
For claim 29, Yu teaches a (BNN implemented on a 16Mb RRAM macro chip, Figure 1 and Abstract), comprising:
a host (although not explicitly stated, a host is required to input the handwritten digit images to the binary neural network of Figure 1, as understood by Figures 5 and 8); and
a memory device (Figure 1) comprising a plurality of memory banks (16 blocks, Figure 1), each memory bank of the plurality of memory banks comprising:
one or more memory arrays (each block has two 512x1024 arrays, Figure 1 and §II); and
a controller (the portion of Figure 1 which at least performs the computations of sigmoid activation and subtraction, see Figure 8 and §III) coupled to the host (required to receive input handwritten image, Figure 5) and the one or more memory arrays (as understood by examination of Figures 1 and 8), the controller located on a same chip as the one or more memory arrays (Abstract), wherein the controller is configured to:
operate a neural network (BNN classifier, Abstract) on a portion of data, wherein the portion of data represents an image, sound, or emotion (images of a handwritten digits cropped to 20x20 pixels, Figure 5), and the neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data (redundant and massively parallel networks, §III), wherein the controller is configured to operate the neural network using instructions that are based at least in part on one or more commands received from the host (e.g., selection of I/O Width to 8-bit, Table 1 and §II; loading pre-trained weight matrices into array, §III), each command of the one or more commands associated with an address of the one or more memory arrays (as understood by examination of the Figures); and
weigh an accuracy of data recognition based on results of each neural network (Figures 6, 7, 10 and 11).
Yu fails to teach:
a controller on a same chip as the one or more memory arrays, wherein the controller is configured to operate each neural network using instructions;
wherein each neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data.
However, Frazao teaches combining the output probabilities of a plurality of parallel neural networks trained differently from one another (§1) to create a weighted neural network (Abstract, Figure 4).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to classify handwritten digits using a weighted combination of a plurality of Yu’s BNN classifiers, each BNN classifier being independently trained and on separate chips from one another in order to improve classification results (Abstract).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of invention.
The combination of Yu and Frazao as cited above fails to teach a single chip as claimed.
However, Jung teaches macro level parallelism for RRAM (§4.2.3) such that a plurality of dies can be packaged into a single chip (Figure 11).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement the plurality of Yu’s BNN classifiers on a single chip instead of a plurality of chips in order to provide a high level of internal parallelism (§4.2.3).
Furthermore, the particular known technique (multiple RRAM dies in a single chip) was recognized as part of the ordinary capabilities of one skilled in the art, as evidenced by Jung.
For claim 30, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 29 and Jung further teaches:
a high speed interface (HSI) configured to receive the one or more commands and the portion of data from the host (Command Interface & Control Logic and I/O Logic, Figure 11).
For claim 31, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 30 and Jung further teaches:
the HSI is coupled to a bank arbiter (X Decoders and Y Decoder & Multiplexer, Figure 11).
For claim 33, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 30 and Frazao further teaches:
the controller is configured to receive a vote from each neural network (Figure 4).
For claim 34, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 30 and Frazao further teaches:
the vote from each neural network is weighted by the controller (Figure 4).
For claim 35, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 34 and Frazao further teaches:
the vote from each neural network is weighted based on type of particular portion of data and particular training of each neural network (the accuracy is based on validation data and how each model is trained, Figure 4).
For claim 36, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 29 and Frazao further teaches:
the controller is configured to weigh the accuracy of the data recognition using a voting scheme (as understood by examination of Figure 4).
For claim 37, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 36 and Frazao further teaches:
the voting scheme is a majority rule or an average (weighted mean, §4).
For claim 38, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 29 and Yu further teaches:
an output is provided by the controller (handwritten digit classification) based on the accuracy of the data recognition (Figure 7 and §V).
For claim 39, the combination of Yu, Frazao and Jung as cited above teaches the limitations of claim 38 and Frazao further teaches:
the output is discarded if there is no uniform decision on the accuracy of the data recognition among each neural network (random subset of activations are dropped when training with DropOut; when overfitting occurs, less epochs are used, §6).
For claim 40, Yu teaches a method comprising:
operating a neural network (BNN, Abstract) using one or more compute components (Figure 1) located on a same chip (16Mb RRAM macro chip, Abstract) as each of a plurality of memory banks of a processing in memory (PIM) device (16 blocks, Figure 1), wherein operating the neural network is based at least in part on one or more instructions that are based at least in part on one or more commands received from a host (e.g., selection of I/O Width to 8-bit, Table 1 and §II; loading pre-trained weight matrices into array, §III) coupled with a controller associated with one or more memory arrays of the PIM device (the portion of Figure 1 which performs the computations of sigmoid activation and subtraction, see Figure 8 and §III), each command of the one or more commands associated with an address of the one or more memory arrays (each block has two 512x1024 arrays, Figure 1 and §II);
receiving a portion of data representing an image, sound, or emotion at each neural network (images of a handwritten digits cropped to 20x20 pixels, Figure 5); and
determining a characteristic of the portion of data simultaneously on the neural network (redundant and massively parallel networks, §III).
Yu fails to teach:
operating a neural network using one or more compute components located on a same chip; and
determining a characteristic of the portion of data simultaneously on each neural network.
However, Frazao teaches combining the output probabilities of a plurality of parallel neural networks trained differently from one another (§1) to create a weighted neural network (Abstract, Figure 4).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to classify handwritten digits using a weighted combination of a plurality of Yu’s BNN classifiers, each BNN classifier being independently trained and on separate chips from one another in order to improve classification results (Abstract).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of invention.
The combination of Yu and Frazao as cited above fails to teach a single chip as claimed.
However, Jung teaches macro level parallelism for RRAM (§4.2.3) such that a plurality of dies can be packaged into a single chip (Figure 11).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement the plurality of Yu’s BNN classifiers on a single chip instead of a plurality of chips in order to provide a high level of internal parallelism (§4.2.3).
Furthermore, the particular known technique (multiple RRAM dies in a single chip) was recognized as part of the ordinary capabilities of one skilled in the art, as evidenced by Jung.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849
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