DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 21-31 and 33-40 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 21-29 and 33-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (NPL: “A single 1.5-V Digital Chip for a 106 Synapse Neural Network”) in view of Frazao (NPL: “Weighted Convolutional Neural Network Ensemble”).
For claim 21, Watanabe teaches a system (memory and processing circuits on a single chip, Abstract), comprising:
a host (external circuit not shown which generates input signals to data bus and Φs1- Φs8, as understood by examination of Figures 3 and 5-7); and
a memory device (Figures 3 and 5-7), comprising:
one or more dynamic random access memory arrays (512-kbit DRAM cell array; Figures 5-7); and
a controller (x decoder, y decoder and dynamic data transfer circuit, Figures 5-6) on a same chip as the one or more DRAM arrays (Abstract), wherein the controller is configured to:
receive one or more commands from the host via a control bus (combination of signal lines Φs1- Φs8 and input data to data bus) between the controller and the host (as understood by Figures 6-7 and §III-D), wherein each command of the one or more commands is associated with a data sense operation for an address of the one or more DRAM arrays (as understood by Figure 7 and §III-D); and
operate, using one or more compute components (processing circuits, Figures 5-7), a neural network (plurality of synaptic weights, Abstract) on a portion of data representing an image, sound, or emotion (e.g., speech or vision, §I), wherein the controller is configured to operate each neural network using instructions (selection of which synapses to perform calculations on) that are based at least in part on the one or more commands received from the host (Φs1- Φs8) via the control bus between the controller and the host (as understood by examination of the Figures).
Watanabe fails to teach:
a memory device comprising a plurality of memory banks;
wherein each neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data.
However, Frazao teaches combining the output probabilities of a plurality of parallel neural networks trained differently from one another (§1) to create a weighted neural network (Abstract, Figure 4).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement a weighted neural network by a combination of a plurality of independently trained neural networks, each independently trained neural network implemented using Watanabe’s single chip respectively, in order to improve accuracy (Abstract, Frazao).
The combination of Watanabe and Frazao teaches:
a memory device comprising a plurality of memory banks (each instance of Watanabe’s chip corresponding to each neural network of the weighted neural network), each memory bank of the plurality of memory banks comprising:
one or more dynamic random access memory arrays (512-kbit DRAM cell array; Figures 5-7, Watanabe); and
a controller (dynamic data transfer circuit, Figure 7) on a same chip as the one or more DRAM arrays (Abstract), wherein the controller is configured to:
receive one or more commands from the host via a control bus (combination of signal lines Φs1- Φs8) between the controller and the host (as understood by Figures 6-7 and §III-D), wherein each command of the one or more commands is associated with a data sense operation for an address of the one or more DRAM arrays (as understood by Figure 7 and §III-D); and
operate, using one or more compute components (processing circuits, Figures 5-7), a neural network (plurality of synaptic weights, Abstract) on a portion of data representing an image, sound, or emotion (e.g., speech or vision, §I), wherein the controller is configured to operate each neural network using instructions (Φs1- Φs8) that are based at least in part on the one or more commands received from the host (training data) via the control bus between the controller and the host (as understood by the combination as cited above), and wherein each neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data (parallel processing, §III-A; each neural network is capable of simultaneous operation).
For claim 22, Watanabe in view of Frazao teaches the limitations of claim 21 and Watanabe further teaches:
each neural network is configured to include processing in memory (PIM) architecture (as understood by examination of Figures 3-7).
For claim 23, Watanabe in view of Frazao teaches the limitations of claim 21 and Watanabe further teaches:
each neural network includes sensing circuitry including a sense amplifier (SA, Figure 6) and a compute component (processing circuit, Figure 6).
For claim 24, Watanabe in view of Frazao teaches the limitations of claim 21 and Frazao further teaches:
each neural network is independently trained (see rejection of claim 21 above).
For claim 25, Watanabe in view of Frazao teaches the limitations of claim 21 and Frazao further teaches:
each neural network is configured to simultaneously receive the instructions to operate on the portion of data (each individually trained neural network is capable of both simultaneous and successive operation).
For claim 26, Watanabe in view of Frazao teaches the limitations of claim 21 and Watanabe further teaches:
each neural network is configured to operate in a fixed point or binary weighted network (binary weighted network, §III-B).
For claim 27, Watanabe in view of Frazao teaches the limitations of claim 21 and Watanabe further teaches:
each neural network is a single-bit network (synapse weight is a binary voltage, §III-B).
For claim 28, Watanabe in view of Frazao teaches the limitations of claim 21 and Watanabe further teaches:
the controller comprises control logic (x decoder, y decoder, Figure 5), sequencers (TG, Figure 6), and timing circuitry (Buffer, Figure 6).
For claim 29, Watanabe teaches a system (memory and processing circuits on a single chip, Abstract), comprising:
a host (external circuit not shown which generates input signals to data bus and Φs1- Φs8, as understood by examination of Figures 3 and 5-7); and
a memory device (Figures 3 and 5-7), comprising:
one or more dynamic random access memory arrays (512-kbit DRAM cell array; Figures 5-7); and
a controller (x decoder, y decoder and dynamic data transfer circuit, Figures 5-6) located on a same chip as the one or more DRAM arrays (Abstract), wherein the controller is configured to:
receive one or more commands from the host via a control bus (combination of signal lines Φs1- Φs8 and input data to data bus) between the controller and the host (as understood by Figures 6-7 and §III-D), wherein each command of the one or more commands is associated with a data sense operation for an address of the one or more DRAM arrays (as understood by Figure 7 and §III-D);
operate, using one or more compute components (processing circuits, Figures 5-7), a neural network (plurality of synaptic weights, Abstract) on a portion of data representing an image, sound, or emotion (e.g., speech or vision, §I), wherein the controller is configured to operate the neural network using instructions (selection of which synapses to perform calculations on) that are based at least in part on the one or more commands received from the host (Φs1- Φs8).
Watanabe fails to teach:
each neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data, wherein the controller is configured to operate each neural network using instructions that are based at least in part on the one or more commands received from the host and
weigh an accuracy of data recognition based on results of each neural network.
However, Frazao teaches combining the output probabilities of a plurality of parallel neural networks trained differently from one another (§1) to create a weighted neural network (Abstract, Figure 4).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement a weighted neural network by a combination of a plurality of independently trained neural networks, each independently trained neural network implemented using Watanabe’s single chip respectively, in order to improve accuracy (Abstract, Frazao).
The combination of Watanabe and Frazao teaches:
a memory device comprising a plurality of memory banks (each instance of Watanabe’s chip corresponding to each neural network of the weighted neural network), each memory bank of the plurality of memory banks comprising:
one or more dynamic random access memory arrays (512-kbit DRAM cell array; Figures 5-7, Watanabe); and
a controller (dynamic data transfer circuit, Figure 7) on a same chip as the one or more DRAM arrays (Abstract), wherein the controller is configured to:
receive one or more commands from the host via a control bus (combination of signal lines Φs1- Φs8) between the controller and the host (as understood by Figures 6-7 and §III-D), wherein each command of the one or more commands is associated with a data sense operation for an address of the one or more DRAM arrays (as understood by Figure 7 and §III-D); and
operate, using one or more compute components (processing circuits, Figures 5-7), a neural network (plurality of synaptic weights, Abstract) on a portion of data representing an image, sound, or emotion (e.g., speech or vision, §I), wherein the controller is configured to operate each neural network using instructions (Φs1- Φs8) that are based at least in part on the one or more commands received from the host (training data) via the control bus between the controller and the host (as understood by the combination as cited above), and wherein each neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data (parallel processing, §III-A; each neural network is capable of simultaneous operation); and
weigh an accuracy of data recognition based on results of each neural network (Abstract, Frazao).
For claim 33, Watanabe in view of Frazao teaches the limitations of claim 29 and Frazao further teaches:
the controller is configured to receive a vote from each neural network (Figure 4).
For claim 34, Watanabe in view of Frazao teaches the limitations of claim 33 and Frazao further teaches:
the vote from each neural network is weighted by the controller (Figure 4).
For claim 35, Watanabe in view of Frazao teaches the limitations of claim 34 and Frazao further teaches:
the vote from each neural network is weighted based on type of particular portion of data and particular training of each neural network (the accuracy is based on validation data and how each model is trained, Figure 4).
For claim 36, Watanabe in view of Frazao teaches the limitations of claim 34 and Frazao further teaches:
the controller is configured to weigh the accuracy of the data recognition using a voting scheme (as understood by examination of Figure 4).
For claim 37, Watanabe in view of Frazao teaches the limitations of claim 36 and Frazao further teaches:
the voting scheme is a majority rule or an average (weighted mean, §4).
For claim 38, Watanabe in view of Frazao teaches the limitations of claim 29 and Frazao further teaches:
an output is provided by the controller based on the accuracy of the data recognition (as understood by the combination of references as cited above).
For claim 39, Watanabe in view of Frazao teaches the limitations of claim 38 and Frazao further teaches:
the output is discarded if there is no uniform decision on the accuracy of the data recognition among each neural network (random subset of activations are dropped when training with DropOut, when overfitting occurs, less epochs are used, §6).
For claim 40, Watanabe teaches a method comprising:
receiving one or more commands from a host (external circuit not shown which generates input signals to data bus and Φs1- Φs8, as understood by examination of Figures 3 and 5-7) via a control bus (combination of signal lines Φs1- Φs8 and input data to data bus) between a controller (x decoder, y decoder and dynamic data transfer circuit, Figures 5-6) and the host (as understood by Figures 6-7 and §III-D), wherein each command of the one or more commands is associated with a data sense operation for an address of one or more dynamic random access memory arrays (512-kbit DRAM cell array; Figures 5-7) of a processing in memory (PIM) device (Abstract and as understood by examination of the Figures);
operating a neural network using one or more compute components (processing circuits, Figures 5-7) located on a same chip a memory bank of the PIM device (Abstract and as understood by examination of the Figures), wherein operating the neural network on each of the plurality of memory banks is based at least in part on one or more instructions (selection of which synapses to perform calculations on) that are based at least in part on the one or more commands received from the host (Φs1- Φs8);
receiving a portion of data representing an image, sound, or emotion at the neural network (e.g., speech or vision, §I).
Watanabe fails to teach:
the PIM device comprising a plurality of memory banks; and
determining a characteristic of the portion of data simultaneously on each neural network.
However, Frazao teaches combining the output probabilities of a plurality of parallel neural networks trained differently from one another (§1) to create a weighted neural network (Abstract, Figure 4).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement a weighted neural network by a combination of a plurality of independently trained neural networks, each independently trained neural network implemented using Watanabe’s single chip respectively, in order to improve accuracy (Abstract, Frazao).
The combination of Watanabe and Frazao teaches:
a memory device comprising a plurality of memory banks (each instance of Watanabe’s chip corresponding to each neural network of the weighted neural network), each memory bank of the plurality of memory banks comprising:
one or more dynamic random access memory arrays (512-kbit DRAM cell array; Figures 5-7, Watanabe); and
a controller (dynamic data transfer circuit, Figure 7) on a same chip as the one or more DRAM arrays (Abstract), wherein the controller is configured to:
receive one or more commands from the host via a control bus (combination of signal lines Φs1- Φs8) between the controller and the host (as understood by Figures 6-7 and §III-D), wherein each command of the one or more commands is associated with a data sense operation for an address of the one or more DRAM arrays (as understood by Figure 7 and §III-D); and
operate, using one or more compute components (processing circuits, Figures 5-7), a neural network (plurality of synaptic weights, Abstract) on a portion of data representing an image, sound, or emotion (e.g., speech or vision, §I), wherein the controller is configured to operate each neural network using instructions (Φs1- Φs8) that are based at least in part on the one or more commands received from the host (training data) via the control bus between the controller and the host (as understood by the combination as cited above), and wherein each neural network of the plurality of memory banks is configured to operate simultaneously to classify the portion of data (parallel processing, §III-A; each neural network is capable of simultaneous operation).
Claim(s) 30-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe, Frazao and Zawodny et al (US 2017/0337126).
For claim 30, the combination of Watanabe and Frazao as cited above teaches the limitations of claim 29 but fails to teach a high speed interface as claimed.
However, Zawodny teaches a DRAM memory device (120, Figure 1B and [36]) that communicates with a host (110) via a high speed interface (141) and bank arbiter (145).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use a high speed interface between the host and the combination circuit of Watanabe and Frazao for the advantage of high speed operation.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art, as evidenced by Zawodny.
For claim 31, the combination of Watanabe, Frazao and Zawodny as cited above teaches the limitations of claim 30 and further teaches:
the HSI is coupled to a bank arbiter (145).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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