DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1A directed to Figure 25 and claim 14. Claims 1-13 are generic to all species, as such claims 1-14 are presented for examination in the reply filed on 01/20/2026 is acknowledged. All other claims are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. 20210351109.
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Regarding claim 1, fig. 16A of Sato discloses a three-dimensional memory device, comprising:
a pair of alternating stacks of insulating layers 32 and electrically conductive layers 46, the pair of alternating stacks being laterally spaced from each other by a lateral isolation trench 79’ that generally extends along a first horizontal direction (across the page);
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memory openings vertically extending through a respective one of the pair of alternating stacks (opening occupied by 20 and 58 in fig. 15A, 49 in figs. 5A/5B);
memory opening fill structures 55 (fig. 5H) located in a respective one of the memory openings and comprising a respective vertical semiconductor channel 60 and a respective vertical stack of memory elements 55 located at levels of the electrically conductive layers; and
a lateral isolation trench fill structure located in the lateral isolation trench and comprising a peripheral spacer (172/74 – fig. 15A) and a conductive fill structure 76,
wherein the lateral isolation trench fill structure has a width modulation at levels of both the insulating layers and the electrically conductive layers (see width thickness variation of 74 and 172 which is a width modulation of some type) along a second horizontal direction (into the page) that is perpendicular to the first horizontal direction as a function of a lateral distance along the first horizontal direction (see variation width in across the page in fig. 16A).
Regarding claim 2, fig. 16A of Sato discloses wherein a first vertical cross-sectional view of the lateral isolation trench fill structure in a first vertical plane that is perpendicular to the first horizontal direction comprises: an outer periphery of the peripheral spacer which comprises a horizontal top surface segment located in a first horizontal plane (top surface of 172); and
an inner periphery of the peripheral spacer that is vertically spaced from and located entirely below the first horizontal plane (that of 74 in fig. 16A).
Regarding claim 8, fig. 16A of Sato discloses wherein the lateral isolation trench fill structure comprises a periodic laterally alternating sequence of neck regions having a minimum width along the second horizontal direction and bulging regions having a maximum width along the second horizontal direction.
Regarding claim 13, par [0112] of Sato discloses wherein the conductive fill structure consists essentially of titanium or titanium nitride.
Regarding claim 14, fig. 16A of Sato discloses wherein the peripheral spacer comprises at least one dielectric material.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OKino et al. 20230284443.
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Regarding claim 1 and 7, figs. 14A of Okino discloses a three-dimensional memory device, comprising:
a pair of alternating stacks of insulating layers 32 and electrically conductive layers 46, the pair of alternating stacks being laterally spaced from each other by a lateral isolation trench 79 (fig. 9) that generally extends along a first horizontal direction;
memory openings vertically extending through a respective one of the pair of alternating stacks; memory opening fill structures located in a respective one of the memory openings and comprising a respective vertical semiconductor channel 60 and a respective vertical stack of memory elements 50 located at levels of the electrically conductive layers; and
a lateral isolation trench fill structure located in the lateral isolation trench and comprising a peripheral spacer 74 and a conductive fill structure 76, wherein the lateral isolation trench fill structure has a width modulation (constant modulation as the width is constant) at levels of both the insulating layers and the electrically conductive layers along a second horizontal direction that is perpendicular to the first horizontal direction as a function of a lateral distance along the first horizontal direction (constant as function distance), and
further comprising: bonding pads98 located over the pair of alternating stacks;
a logic die 700 (par [0113]) containing a peripheral circuit bonded to the bonding pads; and
a semiconductor source layer 14 located below the pair of alternating stacks in contact with ends of the vertical semiconductor channels.
Allowable Subject Matter
Claims 3-6 and 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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